JPH01196849A - Formation of isolation region of semiconductor device - Google Patents
Formation of isolation region of semiconductor deviceInfo
- Publication number
- JPH01196849A JPH01196849A JP2223388A JP2223388A JPH01196849A JP H01196849 A JPH01196849 A JP H01196849A JP 2223388 A JP2223388 A JP 2223388A JP 2223388 A JP2223388 A JP 2223388A JP H01196849 A JPH01196849 A JP H01196849A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- trench
- type
- epitaxial layer
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002955 isolation Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 239000006185 dispersion Substances 0.000 abstract 5
- 238000009792 diffusion process Methods 0.000 description 22
- 238000000926 separation method Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体基板上に堆積されたエピタキシャル層
中において、基板との界面に存在する他導電形の埋込み
層およびエピタキシャル層表面からその埋込み層に達す
る他導電形の拡散層によって囲むことによる一導電形の
半導体素子分離領域の形成方法に関する。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a buried layer of a different conductivity type existing at the interface with the substrate in an epitaxial layer deposited on a semiconductor substrate, and a buried layer from the surface of the epitaxial layer. The present invention relates to a method of forming a semiconductor element isolation region of one conductivity type by surrounding it with a diffusion layer of a different conductivity type that reaches the layer.
(従来の技術〕
エピタキシャル層中の分離領域としては、従来第2図に
示すような構造のものが知られている。(Prior Art) As an isolation region in an epitaxial layer, a structure as shown in FIG. 2 is conventionally known.
このような構造は、例えばP形シリコン基板1上に島状
にN°埋込み拡散N2を形成した後、P形シリコンエピ
タキシャル層3を堆積し、その後エピタキシャル層3表
面より島状に埋込まれた拡散11i2に到達するN0拡
散層4を形成することにより、P形基板内にN゛拡散層
でとり囲まれた分離領域5を形成する方法で得られる。Such a structure is constructed by, for example, forming an island-shaped buried diffusion N2 on a P-type silicon substrate 1, depositing a P-type silicon epitaxial layer 3, and then depositing an island-shaped buried diffusion N2 from the surface of the epitaxial layer 3. By forming the N0 diffusion layer 4 that reaches the diffusion 11i2, a separation region 5 surrounded by the N2 diffusion layer is formed in the P-type substrate.
しかし、電力用素子のように第2図でDで示す分離層4
の深さが比較的深いことが要求される場合には、埋込み
層に到達する拡散層の形成が困難となるという欠点があ
った。困難な理由として、長時間の拡散時間を要するこ
と、さらに長時間の拡散に伴い埋込み層2および分離拡
散層4からの外方向拡散が大きくなり、実効的な分離9
M域5の容積が小さくなることであった。However, like a power device, the separation layer 4 shown as D in FIG.
If a relatively deep depth is required, there is a drawback that it becomes difficult to form a diffusion layer that reaches the buried layer. The reason for this difficulty is that it requires a long diffusion time, and furthermore, as the diffusion takes a long time, outward diffusion from the buried layer 2 and the separation diffusion layer 4 increases, making it difficult to achieve effective separation.
The problem was that the volume of M region 5 became smaller.
本発明の課題は、上述の欠点を除去し、高温長時間の拡
散処理に伴って発生する結晶欠陥など素子特性を低下さ
せる要因を排除し、容易に任意の深さを有する半導体素
子分離領域の形成方法を提供することにある。The object of the present invention is to eliminate the above-mentioned drawbacks, eliminate factors that degrade device characteristics such as crystal defects that occur with high-temperature and long-time diffusion processing, and easily form semiconductor device isolation regions with arbitrary depths. The object of the present invention is to provide a forming method.
上述の課題を解決するために、本発明の方法は他導電形
の埋込み層を有する一導電形の基板上に−it形のエピ
タキシャル層を形成し、その後エピタキシャル層表面よ
り埋込み層の周縁部に向けて溝を堀り、その溝の側壁お
よび底部より不純物を拡散して埋込み層に連結する他導
電形の層を形成するものである。In order to solve the above-mentioned problems, the method of the present invention is to form an -it type epitaxial layer on a substrate of one conductivity type having a buried layer of another conductivity type, and then to form a -it type epitaxial layer from the surface of the epitaxial layer to the periphery of the buried layer. A trench is dug toward the buried layer, and impurities are diffused from the sidewalls and bottom of the trench to form a layer of a different conductivity type that connects to the buried layer.
エピタキシャル層表面から堀られた溝の側壁および底部
よりの不純物拡散層を埋込み層に連結させるための拡散
時間は、従来のエピタキシャル層表面から埋込み層に達
するまで行った不純物拡散時間に比して著しく短い時間
ですむ。The diffusion time required to connect the impurity diffusion layer from the sidewalls and bottom of the trench dug from the epitaxial layer surface to the buried layer is significantly longer than the conventional impurity diffusion time from the epitaxial layer surface to the buried layer. It only takes a short time.
第1図は本発明の一実施例によって形成された分M 9
M域を含む断面図で、第2図と共通の部分には同一の符
号が付されている0図から明らかなようにP形基板1上
のP形エピタキシャル層3の表面からほとんどN゛埋込
層2に達する深さの溝6が形成されている。この溝6は
、ウェットエツチング法によっても形成できるし、溝が
せまくて深い場合にはドライエツチング法により形成す
るのが有利である。この溝6の形成のために用いたマス
クをそのまま利用してイオン注入法により溝の側壁およ
び底部にN形化のための不純物を導入し、ドライブ拡散
することによりN4拡散層7を形成する。この拡散層7
は浅くても埋込み層2と連結させることができ、エピタ
キシャル層3内にN形の埋込み層2と溝部6およびN膨
拡散層7によって分離されたP影領域5を形成すること
ができる。エピタキシャル層表面の平坦であることが望
ましいときには溝6に半導体表面保護膜と同一の絶縁材
料で充填してもよいが、特に絶縁性あるいは気泡率につ
いては重要でないから他の材料で充填してもよい。FIG. 1 shows a portion M 9 formed according to an embodiment of the present invention.
This is a cross-sectional view including the M region, and as is clear from FIG. 0, in which parts common to those in FIG. A groove 6 deep enough to reach the layer 2 is formed. This groove 6 can also be formed by wet etching, but if the groove is narrow and deep, it is advantageous to form it by dry etching. Using the same mask used to form the trench 6, impurities for making the trench N-type are introduced into the side walls and bottom of the trench by ion implantation, and the N4 diffusion layer 7 is formed by drive diffusion. This diffusion layer 7
can be connected to the buried layer 2 even if it is shallow, and a P shadow region 5 can be formed in the epitaxial layer 3, separated from the N type buried layer 2 by the trench 6 and the N expansion diffusion layer 7. If it is desired that the surface of the epitaxial layer be flat, the grooves 6 may be filled with the same insulating material as the semiconductor surface protective film, but since the insulation properties or the bubble rate are not particularly important, they may be filled with other materials. good.
本発明によれば、−導電形のエピタキシャル層中に他導
電形の埋込み層とエピタキシャル層表面からその埋込み
暦に達する他導電形の拡散層によってpn接合分離され
る領域を形成する際に、予めエピタキシャル層表面から
埋込み層付近に達する溝を堀っておき、溝の側壁および
底部からの浅い拡散層により埋込み層と連結することに
よって、分離層のための長時間拡散時間が不要となり、
深い分離層を必要とする電力用素子あるいはMO3素子
作成などの際のように、大きな容積の分離領域を得るた
めに比較的高温長時間のドライブ熱処理を嫌う場合の素
子分離に極めて有効である。According to the present invention, - when forming in an epitaxial layer of a conductivity type a region separated by a pn junction from a buried layer of a different conductivity type and a diffusion layer of a different conductivity type reaching from the surface of the epitaxial layer to the buried layer, By digging a trench from the surface of the epitaxial layer to the vicinity of the buried layer and connecting it to the buried layer through a shallow diffusion layer from the sidewalls and bottom of the trench, a long diffusion time for the separation layer is no longer required.
This method is extremely effective for device separation when a drive heat treatment at a relatively high temperature and for a long period of time is undesirable in order to obtain a large-volume separation region, such as in the production of power devices or MO3 devices that require deep separation layers.
第1図は本発明の一実施例により得られた素子分離領域
の断面図、第2図は従来の素子分離領域の断面図である
。FIG. 1 is a cross-sectional view of an element isolation region obtained according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a conventional element isolation region.
Claims (1)
導電形のエピタキシャル層を形成し、その後該エピタキ
シャル層表面より埋込み層の周縁部に向けて溝を堀り、
該溝の側壁および底部より不純物を拡散して前記埋込み
層に連結される他導電形の層を形成することを特徴とす
る半導体素子分離領域の形成方法。1) Forming an epitaxial layer of one conductivity type on a substrate of one conductivity type having a buried layer of another conductivity type, and then digging a groove from the surface of the epitaxial layer toward the periphery of the buried layer,
A method for forming a semiconductor element isolation region, characterized in that a layer of a different conductivity type connected to the buried layer is formed by diffusing impurities from the sidewalls and bottom of the trench.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2223388A JPH01196849A (en) | 1988-02-02 | 1988-02-02 | Formation of isolation region of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2223388A JPH01196849A (en) | 1988-02-02 | 1988-02-02 | Formation of isolation region of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01196849A true JPH01196849A (en) | 1989-08-08 |
Family
ID=12077073
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2223388A Pending JPH01196849A (en) | 1988-02-02 | 1988-02-02 | Formation of isolation region of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01196849A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6569730B2 (en) * | 1999-09-27 | 2003-05-27 | Taiwan Semiconductor Manufacturing Company | High voltage transistor using P+ buried layer |
-
1988
- 1988-02-02 JP JP2223388A patent/JPH01196849A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6569730B2 (en) * | 1999-09-27 | 2003-05-27 | Taiwan Semiconductor Manufacturing Company | High voltage transistor using P+ buried layer |
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