JPH0119649B2 - - Google Patents
Info
- Publication number
- JPH0119649B2 JPH0119649B2 JP57023697A JP2369782A JPH0119649B2 JP H0119649 B2 JPH0119649 B2 JP H0119649B2 JP 57023697 A JP57023697 A JP 57023697A JP 2369782 A JP2369782 A JP 2369782A JP H0119649 B2 JPH0119649 B2 JP H0119649B2
- Authority
- JP
- Japan
- Prior art keywords
- stage
- adjustment
- circuit
- frequency
- amplification
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000003321 amplification Effects 0.000 claims description 24
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 24
- 230000001105 regulatory effect Effects 0.000 claims description 10
- 230000001276 controlling effect Effects 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 2
- 230000003111 delayed effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
- H03G3/3068—Circuits generating control signals for both R.F. and I.F. stages
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
- Circuits Of Receivers In General (AREA)
- Superheterodyne Receivers (AREA)
- Noise Elimination (AREA)
Description
【発明の詳細な説明】
本発明はラジオ−およびテレビジヨン受信機に
おける高周波−および中間周波段の増幅度を制御
する回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit arrangement for controlling the amplification of high-frequency and intermediate-frequency stages in radio and television receivers.
この場合、最初に中間周波段の調整を行い、そ
れから高周波段の調整が行うようにされている。 In this case, the intermediate frequency stage is first adjusted, and then the high frequency stage is adjusted.
ラジオ受信機およびテレビジヨン受信装置の場
合、過制御を回避するため、通常は増幅段が制御
される。これにより増幅段の出力信号の非直線歪
みが回避される。 In the case of radio and television receivers, the amplification stages are usually controlled to avoid overcontrol. This avoids non-linear distortion of the output signal of the amplification stage.
公知技術の場合は、制御電圧（AGC）を中間
周波増幅器から取り出すようにし、この制御電圧
が個々の中間周波段ならびにチユーナにおける入
力増幅段を、アンテナ信号が増加するにつれて、
その増幅度を低下させるように調整する。そのた
め回路段をすでに比較的小さい入力電圧の場合に
も調整することができる。しかし入力電圧がより
高い値になると制御開始時点がおくれてしまうこ
とがある（遅延されて調整される）。前者の場合
は非直線歪み、相互変調等に関しては殆んど問題
がない。しかし後者の場合はＳ／Ｎ比が著しく小
さくなる。Ｓ／Ｎ比は公知のように、入力電圧が
一定の場合は、制御開始時点に反比例する。Ｓ／
Ｎ比の最大値は、入力電圧が一層大きい場合には
じめて得られる。 In the prior art, a control voltage (AGC) is taken from an intermediate frequency amplifier, which controls the individual intermediate frequency stages as well as the input amplification stage in the tuner as the antenna signal increases.
Adjust to reduce the degree of amplification. Therefore, the circuit stage can already be adjusted even in the case of relatively small input voltages. However, when the input voltage becomes a higher value, the control start point may be delayed (adjustment is delayed). In the former case, there are almost no problems with nonlinear distortion, intermodulation, etc. However, in the latter case, the S/N ratio becomes extremely small. As is well known, when the input voltage is constant, the S/N ratio is inversely proportional to the control start point. S/
The maximum value of the N ratio is only obtained at higher input voltages.
例えば米国特許第3454721号に、高周波段およ
び中間風波段の増幅度を調整する回路が示されて
いる。しかしこの回路においても調整用信号を中
間周波段の出力側以降から取り出すようにされて
いる。そのため中間周波段は、チユーナの調整開
始が遅れると、過制御されるおそれが生ずる。し
かしチユーナの調整開始が遅れることは、良好な
Ｓ／Ｎ比にとつては望ましいことである。 For example, US Pat. No. 3,454,721 shows a circuit for adjusting the amplification of the high frequency stage and the intermediate wind wave stage. However, even in this circuit, the adjustment signal is extracted from the output side of the intermediate frequency stage and thereafter. Therefore, if the start of adjustment of the tuner is delayed, the intermediate frequency stage may be over-controlled. However, a delay in the start of tuner adjustment is desirable for a good signal-to-noise ratio.
新しい郵便規則にもとづいて、受信装置たとえ
ばテレビジヨン受信機およびラジオ受信機の構成
の場合、大信号特性を改善する問題が再び生じて
いる。この新しい規則によれば、個々の回路段の
過制御を阻止するために増幅度の調整を一層早く
開始させることが必要とされる。しかし増幅度調
整を一層早く行うとＳ／Ｎ比が犠性にされる、何
故ならばＳ／Ｎ比は、制御開始時点が早いほどそ
れだけ一層低下されるからである。増幅段の非直
線周波数特性のため、増幅度は受信周波数帯域に
わたり一定ではない。例えば増幅装置が、所定の
制御開始時点に周波数1において制御されるとす
る。増幅度が1の場合よりも一層小さくなる周波
数たとえば2の場合、調整が一層遅れて開始され
ると過制御の危険が再び生ずるであろうし、反対
に1の場合よりも増幅度の一層大きい別の周波数
3の場合は、調整が著しく一層早く開始する。し
かしその結果、Ｓ／Ｎ比は著しく遅れて即ちアン
テナ入力電圧が一層大きくなつてから、十分に大
きくなる。 Due to the new postal regulations, the problem of improving the large signal characteristics has arisen again in the design of receiving devices, such as television and radio receivers. This new regulation requires that the adjustment of the amplification be started earlier in order to prevent overcontrol of the individual circuit stages. However, if the amplification adjustment is made earlier, the signal-to-noise ratio is sacrificed, since the signal-to-noise ratio is reduced the earlier the control is started. Due to the non-linear frequency characteristics of the amplification stage, the degree of amplification is not constant over the receive frequency band. For example, assume that the amplifier is controlled at frequency 1 at a predetermined control start point. If the amplification is smaller than in the case of 1 , for example 2 , the risk of overcontrol will arise again if regulation is started later, and conversely, if the amplification is smaller than in the case of 1 , the risk of overcontrol will arise again. frequency of
In case 3 , adjustment starts significantly earlier. However, as a result, the signal-to-noise ratio becomes sufficiently large only after a significant delay, ie, when the antenna input voltage becomes larger.
そのため本発明の課題は、Ｓ／Ｎ比を低下させ
ることなく制御を著しく早く開始することによ
り、新しい郵便規則を満たすことである。この課
題は特許請求の範囲の第１項に示されている技術
構成により解決されている。本発明の利点は装置
の全体の増幅度のばらつきが低減されることであ
る。この制御方式は一層正確に動作する。このこ
とは、最大のＳ／Ｎ比が早く得られるためには極
めて重要である。 The object of the invention is therefore to meet the new postal regulations by starting the control significantly earlier without reducing the signal-to-noise ratio. This problem is solved by the technical arrangement indicated in the first claim. An advantage of the present invention is that the overall amplification variation of the device is reduced. This control scheme works more accurately. This is extremely important in order to quickly obtain the maximum S/N ratio.
本発明の認識の基礎は、過制御されるおそれの
ある回路部分−たとえば中間周波増幅器−を、チ
ユーナの制御が開始される前に保護すべきである
ということである。チユーナの増幅特性は、入力
電圧が一層大きくなつても依然として直線的であ
る。しかもそのためにＳ／Ｎ比が著しく迅速に増
加する、そのため増幅器全体にわたり（高周波段
および中間周波段も）、測定されると最大のＳ／
Ｎ比が、増幅器の雑音指数に応じて入力電圧の２
分の１から３分の１において既に得られる。本発
明により制御の開始点は著しく正確に固定するこ
とができる。何故ならばチユーナの入力トランジ
スタは、アンテナ電圧が一層高くなるとはじめ
て、動作点シフトが行われるからである。 The recognition basis of the invention is that circuit parts that are likely to be overcontrolled, for example intermediate frequency amplifiers, should be protected before control of the tuner is initiated. The tuner's amplification characteristics remain linear even at higher input voltages. Moreover, this causes the signal-to-noise ratio to increase very quickly, so that throughout the entire amplifier (also high-frequency and intermediate-frequency stages) the maximum S/N ratio is measured.
The N-ratio varies by 2 of the input voltage depending on the noise figure of the amplifier.
Already obtained in 1/3 to 1/3. With the invention, the starting point of the control can be fixed with great precision. This is because the input transistor of the tuner undergoes an operating point shift only when the antenna voltage is higher.
次に本発明の実施例につき図面を用いて説明す
る。 Next, embodiments of the present invention will be described with reference to the drawings.
図示されている回路装置は、ラジオ受信機また
はテレビジヨン受信機における高周波段および中
間周波段およびその増幅度を調整する回路を有す
る。この調整回路はまず最初に中間周波段の調整
を行い、その後に高周波段の調整を行うように構
成されている。 The circuit arrangement shown has a high-frequency stage and an intermediate-frequency stage in a radio or television receiver and a circuit for adjusting their amplification. This adjustment circuit is configured to first adjust the intermediate frequency stage and then adjust the high frequency stage.
この回路装置において入力信号がアンテナ１を
介してチユーナ２の入力側へ達する。チユーナに
おける高周波段３においてこの信号は増幅され次
に混合段４において、発振器５を取り出された信
号を用いて中間周波となるように混合される。本
発明によればチユーナ２の混合段４の出力側と中
間周波段６の入力側との間に、調整素子７が挿入
接続されている。この調整素子が、中間周波増幅
段６に対する入力信号を低減するように調整す
る。この調整素子を制御するための制御情報を形
成するために、チユーナ２の混合段４の出力側
に、場合によりフイルタ８を介して、自動増幅度
調整（AGC）用の電圧を発生するための回路９
が設けられている。調整が開始されるとこの調整
電圧発生回路９は、まず最初に調整素子７を、そ
の増幅度を約10dB低下させるように調整する。
そのため中間周波増幅段に対する入力信号が最小
値へ低減される。このように中間周波増幅段に対
する入力信号が最大の減少調整を受けた時にはじ
めて、チユーナ２における高周波段３に対する調
整が、閾値段１０を用いて遅延されて、開始され
る。即ち、調整電圧発生回路からの調整電圧が閾
値段１０を介して高周波段３を調整する。 In this circuit arrangement, an input signal reaches the input side of a tuner 2 via an antenna 1 . This signal is amplified in the high frequency stage 3 in the tuner, and then mixed in the mixing stage 4 to produce an intermediate frequency using the signal extracted from the oscillator 5. According to the invention, a regulating element 7 is inserted and connected between the output side of the mixing stage 4 and the input side of the intermediate frequency stage 6 of the tuner 2. This adjustment element adjusts the input signal to the intermediate frequency amplification stage 6 to reduce it. In order to form the control information for controlling this regulating element, a voltage for automatic amplification control (AGC) is generated at the output of the mixing stage 4 of the tuner 2, if necessary via a filter 8. circuit 9
is provided. When the adjustment is started, the adjustment voltage generating circuit 9 first adjusts the adjustment element 7 so as to reduce its amplification degree by about 10 dB.
The input signal to the intermediate frequency amplification stage is therefore reduced to a minimum value. Only when the input signal to the intermediate frequency amplification stage has thus undergone the maximum reduction adjustment can the adjustment to the high frequency stage 3 in the tuner 2, delayed by means of a threshold value 10, be initiated. That is, the regulated voltage from the regulated voltage generation circuit regulates the high frequency stage 3 via the threshold value 10.
この場合このAGC回路は通常の様に構成でき
る。調整素子７に対しては、PINダイオードから
構成される減衰器または電界効果トランジスタを
有する回路段を設けることができる。 In this case, this AGC circuit can be configured as usual. The regulating element 7 can be provided with an attenuator consisting of a PIN diode or a circuit stage with a field-effect transistor.
アンテナ入力電圧が1.5ｍＶの場合、Ｓ／Ｎ比
は4dBも改善される。 When the antenna input voltage is 1.5 mV, the S/N ratio is improved by 4 dB.
上述の回路装置の場合、チユーナの混合器出力
側において形成される調整信号は、必要に応じて
選択的にまたは広帯域用に形成できる。この種の
調整により、アンテナから復調器までの増幅路全
体において生ずる増幅度の変動がチユーナだけに
制限できるようになる。そのためこの構成によ
り、直線性に対する要求が充足され、かつ同時に
Ｓ／Ｎ比も改善される。 In the case of the circuit arrangement described above, the regulation signal generated at the mixer output of the tuner can be configured selectively or broadband as required. This type of adjustment makes it possible to limit the amplification variations that occur throughout the amplifier path from the antenna to the demodulator to the tuner only. Therefore, this configuration satisfies the requirement for linearity and at the same time improves the S/N ratio.
図は本発明による回路装置の実施例のブロツク
図である。
１……アンテナ、２……チユーナ、３……前置
段、４……混合段、５……発振器、６……中間周
波増幅器、７……制御段、８……フイルタ、９…
…AGC回路、１０……閾値段。
The figure shows a block diagram of an embodiment of the circuit arrangement according to the invention. 1... Antenna, 2... Tuner, 3... Prestage, 4... Mixing stage, 5... Oscillator, 6... Intermediate frequency amplifier, 7... Control stage, 8... Filter, 9...
...AGC circuit, 10...Threshold price.
Claims (1)
高周波−および中間周波段の増幅度を調整するた
めの回路装置であつて、この場合まず最初に中間
周波段の調整を行いその後に高周波段の遅延調整
を行うようにされている回路装置において、遅延
調整を行うために混合段４と中間周波段６との間
に調整用の調整素子７を挿入接続し、該調整素子
は制御情報を、混合段４と調整素子７との間に接
続された調整電圧発生回路９から供給されるよう
にし、調整が開始されると調整電圧発生回路はま
ず最初に調整素子７を、その増幅度を10dBだけ
低下させるように調整し、次にこの調整電圧発生
回路９からの調整電圧が閾値段１０を介して高周
波段３の調整を行うようにしたことを特徴とする
ラジオ−およびテレビジヨン受信機における高周
波−および中間周波段の増幅度を制御する回路装
置。 ２ 調整素子７を、PINダイオードを用いて構成
される減衰器として実施した特許請求の範囲第１
項に記載の回路装置。 ３ 調整素子７を、電界効果トランジスタにより
構成した回路段により形成した特許請求の範囲第
１項に記載の回路装置。 ４ 調整回路から送出される制御電圧が、選択的
にフイルタ回路８を介して混合段４から供給され
るようにした特許請求の範囲第１項記載の回路装
置。[Scope of Claims] 1. A circuit device for adjusting the amplification degree of high frequency and intermediate frequency stages in radio and television receivers, in which case the intermediate frequency stage is first adjusted and then the high frequency stage is adjusted. In a circuit device configured to perform stage delay adjustment, an adjustment element 7 for adjustment is inserted and connected between the mixing stage 4 and the intermediate frequency stage 6 in order to perform delay adjustment, and the adjustment element transmits control information. is supplied from the adjustment voltage generation circuit 9 connected between the mixing stage 4 and the adjustment element 7, and when adjustment is started, the adjustment voltage generation circuit first controls the adjustment element 7 and its amplification degree. A radio and television receiver characterized in that the regulated voltage from the regulated voltage generating circuit 9 is adjusted to reduce the voltage by 10 dB, and then the regulated voltage from the regulated voltage generating circuit 9 adjusts the high frequency stage 3 via a threshold value 10. circuit device for controlling the amplification of high-frequency and intermediate-frequency stages in a machine; 2 Claim 1 in which the adjustment element 7 is implemented as an attenuator configured using a PIN diode
The circuit device described in Section. 3. The circuit device according to claim 1, wherein the adjustment element 7 is formed by a circuit stage composed of field effect transistors. 4. The circuit arrangement according to claim 1, wherein the control voltage delivered from the regulating circuit is selectively supplied from the mixing stage 4 via the filter circuit 8.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19813105928 DE3105928C2 (en) | 1981-02-18 | 1981-02-18 | Circuit arrangement for regulating the gain of HF and IF stages in radio and television receivers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57184311A JPS57184311A (en) | 1982-11-13 |
| JPH0119649B2 true JPH0119649B2 (en) | 1989-04-12 |
Family
ID=6125161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2369782A Granted JPS57184311A (en) | 1981-02-18 | 1982-02-18 | Circuit device for controlling amplifification degree of high and intermediate frequency stages in radio and television receivers |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS57184311A (en) |
| DE (1) | DE3105928C2 (en) |
| FI (1) | FI74844C (en) |
| FR (1) | FR2500235B1 (en) |
| GB (1) | GB2093291B (en) |
| SE (1) | SE454226B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0338906A (en) * | 1989-07-05 | 1991-02-20 | Pioneer Electron Corp | Receiver |
| DE4011650A1 (en) * | 1990-04-11 | 1991-10-17 | Licentia Gmbh | CONTROL CIRCUIT FOR A OVERLAY RECEIVER |
| JP5429259B2 (en) | 2011-10-27 | 2014-02-26 | コニカミノルタ株式会社 | Screw fall prevention structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS531007A (en) * | 1976-06-24 | 1978-01-07 | Matsushita Electric Ind Co Ltd | Manufacture of magnetic head |
| JPS5350959A (en) * | 1976-10-20 | 1978-05-09 | Matsushita Electric Ind Co Ltd | Automatic gain control device |
| JPS54140858A (en) * | 1978-04-24 | 1979-11-01 | Hitachi Ltd | Delay agc circuit |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE657528C (en) * | 1938-03-07 | Marconi Wireless Telegraph Co | Receiver with automatic shrinkage control | |
| FR1391976A (en) * | 1964-01-31 | 1965-03-12 | Ribet & Desjardins | Improvements to television receivers |
| DE1297705B (en) * | 1966-02-08 | 1969-06-19 | Siemens Ag | Multi-stage amplifier arrangement with automatic control |
| US3454721A (en) * | 1966-05-31 | 1969-07-08 | Admiral Corp | Transistorized agc system |
| US3579112A (en) * | 1969-03-03 | 1971-05-18 | Rca Corp | Automatic gain control systems |
| US3697883A (en) * | 1970-09-10 | 1972-10-10 | Motorola Inc | Automatic gain control circuit |
| DE2460602C2 (en) * | 1974-12-20 | 1982-08-19 | Siemens AG, 1000 Berlin und 8000 München | Receiver for high-frequency electromagnetic oscillations with gain control and monitoring circuit |
| JPS55121520U (en) * | 1979-02-16 | 1980-08-28 |
-
1981
- 1981-02-18 DE DE19813105928 patent/DE3105928C2/en not_active Expired
-
1982
- 1982-02-15 FI FI820502A patent/FI74844C/en not_active IP Right Cessation
- 1982-02-16 SE SE8200921A patent/SE454226B/en not_active IP Right Cessation
- 1982-02-17 GB GB8204617A patent/GB2093291B/en not_active Expired
- 1982-02-18 JP JP2369782A patent/JPS57184311A/en active Granted
- 1982-02-18 FR FR8202703A patent/FR2500235B1/en not_active Expired
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS531007A (en) * | 1976-06-24 | 1978-01-07 | Matsushita Electric Ind Co Ltd | Manufacture of magnetic head |
| JPS5350959A (en) * | 1976-10-20 | 1978-05-09 | Matsushita Electric Ind Co Ltd | Automatic gain control device |
| JPS54140858A (en) * | 1978-04-24 | 1979-11-01 | Hitachi Ltd | Delay agc circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3105928C2 (en) | 1986-09-11 |
| FI74844B (en) | 1987-11-30 |
| GB2093291A (en) | 1982-08-25 |
| JPS57184311A (en) | 1982-11-13 |
| GB2093291B (en) | 1984-09-19 |
| FR2500235B1 (en) | 1986-10-10 |
| FI74844C (en) | 1988-03-10 |
| SE8200921L (en) | 1982-08-19 |
| SE454226B (en) | 1988-04-11 |
| FR2500235A1 (en) | 1982-08-20 |
| FI820502L (en) | 1982-08-19 |
| DE3105928A1 (en) | 1982-09-09 |
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