JPH01192100A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To perform an electric field acceleration test by setting an ON state and supplying a source voltage to a bit line in a test mode by providing a switching means between the bit line and the source voltage. CONSTITUTION:A T13 is provided between a node ND between a FETT4 and a node NB in a sense amplifier 1 consisting of an E<2>PROM and the source voltage Vcc, and a test signal TE is added on the gate of the T13. In the test mode, the signal TE and a sense amplifier activation signal, the inverse of SE are set at 'H's, and a T12 and the T13 are turned ON, and a T3 is turned OFF, and a T5 and a T7 keep OFF states, and the sense amplifier 1 is inactivated. When the T13 is turned ON and the potential of the NB goes to the Vcc and a selection signal Y and a word line are set at the Vcc, a bit line BL and the drain of a memory device Mq go to the Vcc. Therefore, it is easy to extract negative charge accumulated in the floating gate of the MQ, and it is possible to detect a defective product by performing the cleaning of the E<2>PROM which performs non-volatile storage in a short period.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device that includes a memory transistor that has a floating gate and performs nonvolatile storage.

[Conventional technology]

FIG. 2 is a circuit diagram showing the area around the sense amplifier of a conventional E2PROM. As shown in the figure, the drain of the memory transistor MQ is connected to the bit line BL via the selection transistor T1, and the source and control gate are grounded. Bit line BL is connected to sense amplifier 1 via transistor T2. Further, a column selection signal Y is supplied to the gate of the transistor T2 from a column decoder (not shown).
is applied.

Sense amplifier 1 includes two p-channel transistors T3
．． T6. Four n-channel transistors T4. T5. T
7. It is a current sensing type configured by transistors T12, and is connected from node N to bit line 8m via transistor T2. Based on the current change of the bit line due to conduction/non-conduction of memory transistor MQ, transistors 76.
Reading is sensed by causing a potential change in the node NA between the nodes 77 and 77.

Sense amplifier 1 is connected to buffer 2 via node NA. Buffer 2 is a p-channel transistor T8. T
10, n-channel transistors T9, T11 to 22 CMo5 inverters [transistors T8. T9] and [transistors T10° and T111 are provided in series, and the node N,
The read data RD is output by amplifying the potential of 1 to "H" and LN level.

The memory transistor MQ of the E2FROM normally stores '1' (positive) or '0' (negative) in a nonvolatile manner depending on the positive or negative threshold voltage.Therefore, when reading, the gate of the memory transistor MQ is closed as shown in the figure. By setting it to the ground level, it becomes non-conductive if it stores 1, and becomes conductive if it stores 0. This is detected by sense amplifier 1, and buffer 2 outputs "I Hl" ul. ``This can be done by amplifying the level.

The read operation by the sense amplifier 1 will be explained below.

At the time of reading, the sense amplifier activation signal SE is set to "L11", the transistor T3 is turned on, and the transistor TI2 is turned on.
By turning off the sense amplifier 1, the sense amplifier 1 is activated. When the memory transistor MQ stores "1", the bit line B is in a floating state, and when the potential of the node NB is not charged, such as when the power is turned on, the transistor T4 is off and the node N. Start charging.

And node N. The potential of transistor T5. Threshold voltage of T7 V15. ■When it rises to about 1□, transistor T5. T7 turns on and node N is charged. Thereafter, when the potential of the node N rises to the threshold voltage V14 of the transistor T4, the transistor T4 is turned on, and the potential of the node N rises to the threshold voltage V14 of the transistor T4. The potential of transistor T5. T7 is turned off. At this time, since memory transistor MQ is off, node N maintains the potential at the v14 level. Note that due to leakage to the substrate, the potential of the node N becomes v1.
4 or less, transistor T4 is turned off and transistor T5.4 is turned off again. T7 turns on and the potential of node N becomes V1
Raise it to level 4 and turn it off.

As a result, since the transistor T7 is off, the potential of the node NA is approximately 5V (power supply voltage), and the read data RD via the buffer 2 is reliably amplified to the "H" level.

On the other hand, when the memory transistor MQ stores O'', the memory transistor MQ becomes conductive and 1tFE flows to the bit line BL, so the potential of the node N becomes below the T4 level, so the transistors T6, T7, T2 .T1
．． All MQs turn on. As a result, since the on-resistance of the transistor T6 is set to be higher than that of other transistors, the potential of the node N becomes approximately the potential of the node N.

At this time, the potential of node N is the same as transistor T5. T2°T1. It is determined by the on-resistance ratio of MQ. Therefore, by appropriately setting the size of transistor T5, node N
The potential of can be made near T4. Then, the read data RD is reliably amplified to "L" level by the buffer 2. In this way, by minimizing the change in the potential of the node N, regardless of the data value stored in the memory transistor MQ, data volatilization due to repeated reading can be prevented.

(Problems to be Solved by the Invention) The area around the sense amplifier of the conventional E2PROM is configured as described above, and the potential of bit IQBL is the power supply voltage V during reading. The voltage value was set lower than C.

Incidentally, the charge accumulated during the 70-day period of the memory transistor tends to be lost due to leakage, ion contamination, etc. over a long period of time or when read operations are frequently repeated. E2PRoM, which has this strong property,
Since there is a high possibility of defects occurring in the initial stage of use,
It is necessary to remove defective memory transistors. Therefore, in addition to operating life tests for dynamic RAM, static RAM, etc., E2PROM requires a test to detect memory transistors that cause initial failure.

Therefore, high temperature is applied to the memory transistor (4-bit acceleration)
, the power supply voltage ■ to the drain of the memory transistor, that is, the bit line. 7 by applying C level voltage (electric field acceleration) etc.
By setting a situation in which the charge on the zeroing gate is relatively likely to be lost, an accelerated test is performed to generate an initial failure.

However, in the conventional sense amplifier structure, the applied voltage V
. Even if 0 is made high, the potential of the bit line is only V□4 (about IV), and the drain of the memory transistor is connected to the power supply voltage V. There was a WR problem in that it was not possible to give 0 and the electric field acceleration was small.

This invention was made to solve the above-mentioned problems, and it provides a non-volatile semiconductor memory that can effectively perform electric field acceleration tests by setting the potential of the bit line to about the power supply voltage during test mode. The purpose is to obtain equipment.

[Means to solve the problem]

A nonvolatile semiconductor memory device according to the present invention includes a memory transistor that has a floating gate and performs nonvolatile storage, and is provided between a bit line to which one electrode of the memory transistor is connected and a power supply voltage, and is turned on in a test mode. switching means is provided for applying a potential at the power supply voltage level to the bit line.

[Effect]

The switching means in this invention is provided between the bit line and the power supply voltage and is turned on during the test mode, so that a potential at the power supply voltage level can be applied to the bit line during the test mode.

〔Example〕

11th i! I is an embodiment of this invention 62280M
FIG. 3 is a circuit diagram showing the area around the sense amplifier. As shown in the figure, the present invention differs from the conventional one in that a transistor T13 is provided between the node N between the transistor T4 in the system amplifier 1 and the node N8, and the power supply voltage Vco. The transistor T13 is turned on when the test signal @TE is applied to the gate and the test signal TE is at "H" level, and the impedance at that time is small.

In such a configuration, the test mode is performed by setting the test signal TE and the sense amplifier activation signal SE to the °H" level. With this signal setting, the transistors TI2 and T13 are turned on and the transistor T3 is turned off. As a result, the node NC becomes "L" level, and the transistors T5 and T7 continue to be turned off, so that the sense amplifier 1 becomes inactive.

On the other hand, the transistor T13 is turned on and its impedance is small, so the potential of the node N is the power supply voltage Vo. It will be about. Therefore, the column selection signal Y and the word line are set to V. . By setting the level to V, the potential of the bit line BL and the drain of the memory transistor MQ is set to V. . level voltage can be applied.

Therefore, in the test mode, by setting the test signal TE and the sense amplifier activation signal SE to "H", a voltage approximately equal to the power supply voltage vco is applied to the drain of the memory transistor MQ, and the negative voltage accumulated in the floating gate is removed. It is possible to set a state in which the charge is easily extracted. As a result, electric field acceleration is higher than before, and 12880M with initially defective memory transistors can be found in a short screening time.

In this embodiment, the sense amplifier activation signal SE is set to "H" to deactivate the sense amplifier, but the sense amplifier may be kept activated. However, in order to prevent wasteful power consumption, it is preferable to deactivate the sense amplifier 1.

Further, although the transistor T13 is provided in the sense amplifier 1 as a switching means, it is not limited to a transistor and does not need to be provided in the sense amplifier 1 as long as it has a configuration that can supply a power supply voltage level to the bit line during the test mode.

Moreover, this invention is applicable not only to 12880M but also to EPROM
It is also applicable to other nonvolatile semiconductor memory devices such as.

〔Effect of the invention〕

As explained above, according to the present invention, since the switching means provided between the bit line and the power supply voltage turns on during the test mode, it is not possible to apply a potential at the power supply voltage level to the bit line during the test mode. This has the effect of allowing electric field acceleration tests to be performed in a shorter time than conventional methods.

[Brief explanation of the drawing]

Figure 1 is the fruit of this invention m'! The circuit diagram showing the surroundings of the sense amplifier of 12880M, which is A. Figure 2 is the circuit diagram of the conventional E
FIG. 2 is a circuit diagram showing the periphery of a sense amplifier of a PROM. In the figure, T13 is a transistor, MQ is a memory transistor, BL is a bit line, and TE is a test signal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a nonvolatile semiconductor memory device equipped with a memory transistor that has a floating gate and performs nonvolatile storage, the memory transistor is provided between a bit line connected to one electrode of the memory transistor and a power supply voltage, and is turned on in a test mode. What is claimed is: 1. A nonvolatile semiconductor memory device characterized in that a switching means is provided for applying a potential at a power supply voltage level to a bit line.