JPH01187876A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the connection of an ohmic electrode and a gate electrode without discontinuity while the backward breakdown strength of Schottky characteristics is maintained at a sufficiently high level by a method wherein the cross sections of the necessary parts of a high melting point gate metal layer are so formed as to have tapered sides or vertical sides. CONSTITUTION:After a tungsten silicide layer 2 is deposited on the whole surface of a compound semiconductor substrate 1, a thin silicon film 3 is built up on a part of the tungsten silicide layer 2. Then an organic photoresist pattern 4 is formed to form a gate metal pattern. The silicon thin film 3 and the tungsten silicide layer 2 are subjected to reactive ion etching with fluorine system gas by using the organic photoresist pattern 4 as a mask. At the cross section where the silicon thin film 3 is formed on the tungsten silicide layer 2, the sides of the cross section of the tungsten silicide layer 2 are tapered. On the other hand, at the cross section where the silicon thin film 3 is not formed on the tungsten silicide layer 2, the sides of the cross section of the tungsten silicide layer 2 are approximately vertical. With this constitution, the discontinuity of a wiring metal in a wiring part can be avoided while the Schottky backward breakdown strength of a self-alignment type heat-resistant gate electrode is not degraded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a compound semiconductor device having a high melting point metal electrode, and particularly to a high melting point metal electrode suitable for forming wiring.

[Conventional technology]

GaAs MESFET, the basic element of GFIA5TC
For example, Nikkei Microdevice July 1986 issue P
As described in pages 65 to 84, high performance has been achieved by self-aligned MESFETs in which n+5 ions are implanted using a refractory metal gate electrode as a mask. Tungsten silisandide (WSi), whose Schottky characteristics do not deteriorate even after high-temperature annealing, is used as a high-melting point metal gate electrode for self-aligned MESFETs.
), tungsten, poride (WBx), tungsten nitride (WNX), tungsten aluminum (WAQ), titanium tungsten (T i W ), and other high melting point metals containing tungsten are used. When forming an n layer using self-alignment technology, the cross-sectional shape of the gate electrode must be vertical because ions are implanted into the n middle layer using these high melting point metal gate electrodes as a mask. For example, the cross section is tapered into a trapezoidal shape.

When ions are implanted into the n middle layer, the ions are implanted through the taper bottom of the gate metal, so the gate metal and high concentration n
This is because +75 is in direct contact with the Schottky electrode, and the reverse breakdown voltage of the Schottky electrode is significantly degraded. In order to process a high melting point metal containing tungsten so that its cross section is vertical, for example, the coverage of the wiring metal must be taken into consideration when performing anti-wiring using a fluorine-based gas such as NF3, SF, or CF4. However, there was an interlayer in which the wiring metal broke at the part where it ran over the gate electrode.

The purpose of the present invention is to vertically process the cross section of the gate electrode in the portion formed in self-alignment with the n-middle layer to improve the reverse withstand voltage of Schottky characteristics, and at the same time to improve the cross section of the gate electrode in the portion where the wiring metal rides on the gate electrode. Processing into a tapered shape improves the coverage of the wiring metal and prevents breakage at this part where it runs over.The gate electrode material is made of only melting point metal, while the gate electrode material at the part where the wiring metal runs over is a high melting point metal containing tungsten. Silicon, silicon dioxide, phosphorus glass, boron phosphorus glass 1. Alternatively, after forming a structure in which at least one type of thin film of silicon nitride is laminated, these two sections are masked with photoresist and NF3. CF4.
Alternatively, this can be achieved by dry etching using a fluorine gas such as SF6.

[Effect]

FIG. 1 shows a diagram illustrating the present invention. FIG. 1(a) is a sectional view, and FIG. 1(b) is a plan view.

After depositing tungsten silicide 2 on the entire surface of the compound semiconductor substrate 1, a thin silicon film 3 is deposited on a portion of the tungsten silicide 2.
Laminate. The film thickness of the tungsten silicide 2 at this time is free, but is usually selected to be 1100 nm to 1 μm. Further, the thickness of the thin silicon film 3 may be lnm or more, but lO
~50 nm is effective. After forming the above laminated structure, an organic photoresist pattern 4 is formed to form a gate total bending pattern. This organic photoresist pattern 4
Using as a mask, the silicon thin film 3 and the tungsten silicide 2 are subjected to reactive ion etching using a fluorine gas. For example, introducing NF3 gas at a pressure of 5 Pa into the reaction tank of a parallel plate type reactive ion etching device,
The silicon film 3 and tungsten silicide 2 can be etched by applying a high frequency of 13.56 MHz to a counter electrode with a diameter of 50 cm and generating a discharge with a power of 300 W. FIGS. 2(a) and 2(b) show cross-sectional shapes of tungsten silicide processed by the above method. FIG. 2(a) shows a processed sectional view of the AA' portion shown in FIG. 1(b).

FIG. 2(b) shows a processed sectional view of the BB' portion shown in FIG. 1(b). In the AA' cross section where the silicon thin film 3 is laminated on the tungsten silicide 2, the cross section of the tungsten silicide 2 is processed into a tapered shape as shown in FIG. 2(a). On the other hand, in the BB' cross section where the silicon thin film 3 is not stacked on the tungsten silicide 2, the cross section of the tungsten silicide 2 is processed almost vertically as shown in FIG. 2(b). In general, reactive ion etching results in a vertical processed cross section because (1) ions are accelerated and incident on the substrate in a direction perpendicular to the substrate by a negative self-bias voltage caused by plasma discharge, resulting in anisotropic etching.

(2) Various reactive gas active species generated by the plasma discharge decompose the organic photoresist, and at the same time, polymers (thin film-like products of the photoresist and the reactive gas) are formed one after another on the sidewalls of the processed cross section of the tungsten silicide. Possible causes include anisotropic etching to prevent etching. If the silicon thin film 3 is laminated on the tungsten silicide 2 as shown in FIG. It is believed that the etching speed increases and etching becomes isotropic, resulting in a tapered shape. However, at present, the detailed mechanism has not been elucidated. According to experiments, the tapered cross section of the tungsten silicide 2 due to the laminated silicon film 3 is an extremely local effect. In other words, 1μ from the silicon laminated part.
At a distance of m or more, the effect of inhibiting polymer formation is lost, and the cross section of the tungsten silicide 2 becomes vertical.

The present invention utilizes such a phenomenon, and as shown in FIG. 1(b), the cross section of the gate part BB' of the heat-resistant gate metal is processed vertically, and the wiring connection part AA' is separated by only about 10 μm.
The cross section is processed into a tapered shape. As a result, it is possible to eliminate full bending and disconnection of the wiring at the wiring portion without deteriorating the Schottky reverse breakdown voltage of the self-aligned heat-resistant gate electrode.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 3, 4, and 5. Although this example will be explained only in the case where a GaAs substrate is used, InP.

The content of the present invention is also effective for other compound semiconductors such as GaAuAs, InAQAsP, and InGaAs.

Example 1: GaAa according to the present invention is shown in FIGS. 3(a) to 3(j).
A procedure for forming an integrated circuit element using MESFET will be shown.

First, in FIG. 3(a), a channel active layer 6 is formed on the surface of a semi-insulating GaAs substrate 1 by ion implantation and cap film activation annealing. The cap film 5 is CV
D (Chemical Vapo
Thickness 200 mm formed by r Deposit, 1on) method
It is a 5in2 film of nm. The channel active layer 6 is made of Si+
2 to 5xio”/am of ions at an accelerating voltage of 75KeV
2 ions were implanted, and the cap annealing method was used to 800% ions in hydrogen.
Anneal at °C for 20 minutes. Next, in FIG. 3(b), after removing the cap film 5, a tungsten silicide WSiX2 and a silicon thin film 3 are laminated by sputtering. The appropriate composition ratio of WSix is Xα0.4,
The film thickness may be 1100n"1μm, but in order to make the resistance sufficiently small and to be suitable for the planar process, it should be 300n" to 1μm.
500 nm is optimal.

Silicon thin film 3 is WSix with silicon as the target.
Conveniently, subsequent sputter deposition is performed. The sputtering conditions at this time are that the substrate temperature is from room temperature to 450°C.
, the discharge gas is Ar, the pressure is 5 m Torr + the discharge power is 0.5 W/am at a high frequency of 13.56 MHz.
The thickness of the silicon thin film 3 may be 1 nm or more, but considering that it is suitable for a planar process and has excellent process controllability, it is optimal to have a thickness of 10 nm to 50 nm.

Next, move to FIG. 3(c). The silicon thin film 3 described above is removed with a predetermined portion remaining by a normal photolithography technique. To remove this silicon thin film, use NF3. A reactive ion etching technique using a common fluorine gas such as CF4 or SF6 is used. However, in reactive ion etching using fluorine-based gas, W is etched at the same time as silicon.
Since Si x is also etched, the silicon thin film 3
When performing reactive ion etching, it is necessary to control the silicon layer for one hour so that only the silicon layer is removed.

Next, in FIG. 3(d), an organic photoresist 4 is deposited on a portion where a gate electrode is to be formed. Next, in FIG. 3(R), using the organic photoresist 4 as a mask, the WSix 2 is processed by reactive dry etching using a fluorine gas. The reaction gas was Nt7.0 at a pressure of 5 Pa. 500 W was applied to an electrode with a diameter of 100 cm at a high frequency of 13.56 MHz. In this case, the negative DC self-bias voltage applied to the wafer is 65V. The tungsten silicide in the part where the silicon thin film 3 is not laminated is processed to have a vertical cross-sectional shape, but the cross-sectional shape in the part where the silicon thin film is laminated (the part marked E in FIG. 3(e)) is tapered. processed into shapes. In FIG. 3(f), Si+ ions 8 are implanted using the photoresist 7 as a mask. The accelerating voltage at this time was 100KV and the implantation amount was 3
Moving to FIG. 3(g), the zeroth order is set to X10' pieces/cm2.

After depositing the surface protective film 9 on the entire surface, it was heated in hydrogen at 800°C.
Annealing is performed for 15 minutes to activate the high concentration active layer 10. The surface protective film was deposited with a thickness of 300 mm using plasma vapor phase chemical growth using S x H4, N, and O as source gases.
A nm SiO2 film is suitable. Next, move to FIG. 3(h). After forming a resist pattern 11 with openings in areas where ohmic electrodes are to be formed by photolithography, the surface protection film 9 is etched by reactive ion etching. Etching gas is CHF 3+
C2F B is preferably used at a pressure of 60 mTorr.

Next, moving to Figure 3 (+), the entire surface is covered with AuGe (60 nm
) /Nt (10nm)/Au (200nm)
ohmic electrode 12 is deposited. The thickness of the ohmic electrode is determined so that it can be easily lifted off in the next process.
The photoresist 11 is removed using a primary photoresist remover, preferably having a thickness of 250 to 300 nm, and unnecessary portions of the ohmic electrode are removed by a lift-off method to complete the structure as shown in FIG. 3(j).

In the part indicated by E in FIG. 3(j), the tungsten silicide 2 is processed into a tapered shape, so that the ohmic electrode 12 which is wired over the top can be connected without disconnection. Figure 4 shows the GaAs MES explained in Figure 3.
1 shows a plan view of an integrated circuit using FETs. The sectional view of FIG. 3 shows the CC' section of FIG. 4. Fourth
In the figure, the gate electrode of the MESFET indicated by the symbol T1 and the drain electrode of the MESFET indicated by the symbol T2 are connected through a tapered connection portion D. Also, T2
The drain and gate of the FET are seated through a tapered connection E. According to this embodiment, at the point where the high melting point gate metal and the ohmic electrode are directly connected,
Since the cross section of the high melting point gate is tapered, there is no possibility of wire breakage at the part that runs over the step. Further, the silicon thin film 3 having a thickness of inn to 50 nm is polycrystallined by high-temperature annealing at 800° C. and has a low resistance, so that electrical connection is also good. In order to further reduce electrical resistance, phosphorus,
Alternatively, it is also effective to use a silicon thin film doped with boron. In this example, the case of tungsten silicide was explained as the high melting point gate, but in addition, tungsten silicide (WBx), tungsten nitride (
WNx).

Similar effects can be obtained by using tungsten aluminum (W A Q x ) = titanium tungsten (Tie).

Moreover, instead of the silicon thin film 3, 5i02. A similar effect can be obtained using phosphorus glass, boron phosphorus glass, or silicon nitride. However, when using these insulating films,
In the process shown in FIG. 3(e), it is necessary to process the high melting point gate metal after first etching these insulating films, and in the process shown in FIG. 3(i), these insulating films must be etched before depositing the ohmic electrode 12. It is necessary to remove the insulating film by etching.

Example 2゜LDD (Danightly Dopped Danrain
) structure is used.

The manufacturing process is shown in Figures 3(a) to 3(e) and 3(g).
~The steps in FIG. 3(j) are the same and will therefore be omitted.

That is, moving from FIG. 3(e) to FIG. 5(a),
SiO213 is deposited to a thickness of 300 nm over the entire surface. Next, as shown in FIG. 5(b), CHF a at a pressure of 60 mTorr
A side wall 14 is formed on the side surface of the tungsten silicide 2 by anisotropic dry etching of the SiO2 13 using +C2Fg gas. The side wall 14 is formed only in a portion where the cross-sectional shape of the tungsten silicide 2 is vertical.

Since the silicon thin film 3 is laminated, it is not formed in the tapered portion. Next, move to FIG. 5(C).

Using the photoresist 7 as a mask, Si+ ions 8 are implanted. The accelerating voltage at this time is 100 KV, and the implantation amount is 5×1013 pieces/cm2. In the area where the side wall 14 is formed, the gate gold g2 and the high concentration active layer 10 are approximately O8.3 μmlI! Therefore, the reverse breakdown voltage of the Schottky is improved. The following steps are shown in FIG. 3(g) and are omitted since they are the same. In this example, the reverse withstand voltage of the Schottky electrode can be improved by the LDD structure, and at the same time, since the cross-sectional shape of the gate is tapered in the part where the ohmic electrode rides on the gate electrode, it is possible to prevent wiring from breaking. be.

〔Effect of the invention〕

According to the present invention, since the cross-sectional shape of the portion of the high-melting point gate that requires full bending can be controlled to be tapered or vertical, it is possible to disconnect the ohmic electrode and the gate electrode while maintaining the Schottky characteristic reverse breakdown voltage sufficiently high. It can be connected without any problem.

[Brief explanation of the drawing]

1(a), 2(a) and 2(b) are cross-sectional views for explaining the present invention in detail, FIG. 1(b) is a plan view, and FIG. 3 is a cross-sectional view for explaining the present invention in detail. FIG. 4 is a diagram showing the manufacturing process of the GaAs integrated circuit of Example 1.
FIG. 5 is a plan view of the integrated circuit G of the second embodiment of the present invention.
1 is a diagram showing a manufacturing process of an aAs integrated circuit. 1...GaAs substrate, 2...Tungsten silicide, 3...Silicon thin film, 4,7.11...Organic photoresist, 5...8102 surface protective film, 6...
Channel active layer, 8... Si ion, 9... Cap film, 10... High concentration active layer, 12... Ohmic electrode, 13... SiO2 film, 14... Side wall.

Claims (1)

[Claims] depositing a first layer made of a refractory metal containing at least tungsten on a compound semiconductor substrate, and depositing at least one of silicon, silicon dioxide, phosphorus glass, boron phosphorus glass, or silicon nitride on a portion of the first layer; laminating a second layer made of one type of thin film;
A method for manufacturing a compound semiconductor device, comprising a step of dry etching a portion where the first layer and the second layer are laminated and a portion where only the first layer is formed using a fluorine-based gas using a resist as a mask. , by the dry etching, the processed cross-sectional shape of the first layer in the part where the first layer and the second layer are laminated is processed into a tapered shape, and the processed cross-sectional shape of the part where the first layer is only the first layer is A method for manufacturing a compound semiconductor device, characterized in that the cross-sectional shape of one layer is processed to be more vertical than the taper.