JPH0118609B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wireless communication device, and more particularly to a wireless communication device having a memory in which the frequency of a channel to be selected can be written in advance.

Conventionally, wireless communication devices, etc. can communicate with other devices in various modes such as FM method and SSB method (hereinafter referred to as operation mode) (hereinafter referred to as operation mode).
There are things that have functions. Usually, the frequency bands used in this type of wireless communication equipment are classified into usage categories, and a busy channel or an empty channel is selected from within the frequency band depending on the purpose of operation (hereinafter, busy channels and empty channels are used). When there is no need to differentiate, they are collectively referred to as operational channels). To select an operating channel, the operation panel 8 shown in FIG. 1 is operated. The operation panel 8 is provided with an operation mode button 9 for determining the operation mode, a channel step button 10 for determining the channel step, a frequency switching dial 11, and the like. The operation mode button 9, channel step button 10, and frequency switching dial 11 are operated to determine the conditions for selecting the transmission and reception frequencies. When the conditions are set, frequency division information that determines the frequency division ratio of the programmable counter 5d of the PLL circuit 5 is sent from the transmission/reception frequency selection circuit 6. As a result, the local signal _L according to the frequency division information is sent to the mixer 3, and the operating channel is selected. In addition to the above-mentioned basic circuit, the transmitting/receiving frequency selection means includes additional circuits having various functions. One of the accessory circuits is a random access memory 32 for storing data relating to desired frequencies, and has various uses. To write the frequency data of the operating channel to the random access memory 32, an address is designated with the address designation dial 17 provided on the operation panel 8, and the write button 16 is operated. By operation, the address selection pulse generation circuit 18 to the address bus 3
4 and the control terminal 32'a of the random access memory 32. By sending out the pulse, the random access memory 32 stores the frequency data prepared in the transmission/reception frequency selection circuit 6 via the data bus 33 without performing a write operation. Control terminal 32'a is L
When it is at level, a read operation is performed. That is,
When the read button 15 is operated, a pulse is sent to the address bus 34, and the frequency data stored in the random access memory 32 is sent to the transmitter/receiver circuit selection circuit 6 via the data bus 33. Furthermore, the random access memory 32 may also be used to store frequency data of busy channels or idle channels. When using the random access memory 32 as a table for busy channels, the automatic memory button 12 is operated to start the automatic transmission/reception frequency sweep circuit 7. The transmission/reception frequency automatic sweep circuit 7 controls the transmission/reception frequency selection circuit 6 to sequentially send out frequency division information related to the transmission/reception frequency at frequency intervals set by the operation mode button 9 and channel step button 10. When there is a radio wave in the sequentially selected channels, a signal is sent from the AGC circuit or squelch circuit provided in the intermediate frequency amplification circuit 4 to the busy channel detection circuit 23.
sent to. When the busy channel detection circuit 23 operates, the address register 31 advances and the random access memory 32 enters a write operation, and the frequency data of the corresponding channel is transferred from the transmission/reception frequency selection circuit 6 to the random access memory 32 via the data bus 33. written to. The written frequency data is read out by operating the address designation dial 17 and readout button 15.

As described above, the random access memory 32 provided in a wireless communication device has a wide variety of uses, and can be freely written and read.
For this reason, it has the disadvantage that it cannot deal with the occurrence of data that is not particularly desired to be erased among the data written to an arbitrary address.

The present invention has been made in view of the above points, and an object of the present invention is to provide a wireless communication device in which data in a multi-purpose storage device provided in the wireless communication device is protected.

The present invention provides a flag writing means that writes a flag that prohibits erasure of desired data written in a random access memory together with the desired data, and detects the presence or absence of a flag written together with the data from the contents of each written data. The structure includes a flag detecting means for detecting the flag, and a write address changing means for writing desired data to another area without erasing the desired data when the flag is detected.

Hereinafter, one embodiment of the wireless communication device according to the present invention will be described in detail with reference to FIG.

FIG. 2 is a block diagram including some logic circuits of a wireless communication device according to the present invention. In addition, Figures 1 and 2
Components that are the same in the figures are designated by the same reference numerals, so their explanation will be omitted.

In FIG. 2, 19 is a flag writing circuit. The flag writing circuit 19 is an inverter 20
and a switch 21. Switch 2
1 has a normally open contact and is activated when a flag button 14 provided on the operation panel 8 is pressed. Switch 21
One contact is connected to the highest bit (hereinafter referred to as MSB) of the input data bus 33a of the random access memory 32 via the terminal 19c.
In addition, the flag button 14 is connected to the terminal 19b and the diode 2.
2 and a control terminal 32'a of the random access memory 32 via a terminal 19d. The flag erase button 13 is a terminal on the operation panel 8.
It is connected to the input side of the inverter 20 via _P5 and the terminal 19a of the flag writing circuit 19, and the output side of the inverter 20 is always at H level. When the flag clear button 13 is pressed, the output side of the inverter 20 becomes L level.

The write control circuit 26 is composed of an inverter 30, a flip-flop 27, an AND circuit 28, and an OR circuit 29.

The inverter 30 is a detection means for detecting the presence or absence of a flag.

Flip-flop 27, AND circuit 28 and OR circuit 29 are address changing means.

The input side of the inverter 30 is connected to a terminal 26b, and the terminal 26b is connected to the MSB of the output data bus 33b of the random access memory 32.
The output side of the inverter 30 is connected to the random access memory 3 via an AND circuit 30a and a terminal 26c.
It is connected to the control terminal 32a of No.2.
The other input side of the OR circuit 30a is the terminal 26e,
It is connected to the reading button 15 via the X, X' connection,
It is always at H level.

An input terminal 26a of the write control circuit 26 is connected to an output terminal 23b of the busy channel detection circuit 23. The transmission/reception frequency automatic sweep circuit 7 starts sweeping, and in response to the sweep, a control pulse is sent to the address circuit 2 of the busy channel detection circuit 23 via the terminal 7d.
When the channel selected by the sweep has a current, it is sent to one input side of the AND circuit 25.
becomes active and the terminal 23b becomes H level. When used for empty channel detection, the logic on the input side of the AND circuit 25 is reversed.

The set terminal S of flip-flop 27 is terminal 2.
6b and an AND circuit 30b, and the reset terminal R is connected to the output side of the inverter 30. When the MSB of the output data bus 33b of the random access memory 32 becomes H level, the flip-flop 27 is set via the AND circuit 30b. The other input side of the AND circuit 30b is connected to the write button 16 via the terminal 26f, Y-Y' connection, and is always at H level.
The reset terminal R is reset to the H level via the inverter 30 in which the MSB goes to the L level. That is, depending on whether the MSB of the data read from the random access memory 32 is at the H level or the L level, the flip-flop 27 is set or
It will be reset.

One input side of the AND circuit 28 is connected to the output terminal Q of the flip-flop 27. Also,
A clock pulse φ is input to the other input side.
When the output terminal Q of the flip-flop 27 becomes H level, the AND circuit 28 responds to the clock pulse φ.
becomes active and passes through the OR circuit 29 to the terminal 26d.
becomes H level.

Here, when frequency data is written into the random access memory 32 by operating the write button 16 and address designation dial 17, the previously written frequency data is overwritten with new frequency data. When the automatic memory button 12 is operated, busy channels (or empty channels, not shown in the case of empty channels) among the channels in the transmission/reception frequency band are sequentially written into the random access memory 32. When, for example, address number 5 is designated with the address designation dial and the frequency data of address 5 is read out, the frequency data can be monitored on a display (not shown) and the corresponding channel is selected. If you want to notify the displayed frequency data to the other party and use this channel again, press the flag button 14. When the flag button 14 is pressed, the switch 21 of the flag writing circuit 19 is closed and the incoming data bus 3 is closed.
Set MSB of 3a to H level and control terminal 3
A write operation is performed by 2'a. If you press the read button 15 in this state, the operation panel 8
The _P7 terminal of will be at L level. Therefore, the AND circuit 30a is always inactive regardless of the state of the other input side, and the output side remains at the L level. Therefore, the MSB of the read data is "1"
In either case, the write operation will not start. When the write button 16 is operated, address 5 is selected from the address selection pulse generation circuit 18 via the address bus 34. When address 5 is selected, the data at address 5 is output to the output data bus 33b. The MSB of the output data bus 33b is “1”
However, the other terminal of the AND circuit 30b is inactive because it is at L level, or the AND circuit 30a is
Since the output side of the inverter 30 is at L level, it becomes inactive and no write operation is performed. The data at address 5 remains monitored on the display.

When the automatic memory button 12 is operated, the terminal 23b of the busy channel detection circuit 23 becomes H level and the busy channel is selected. When the terminal 23b becomes H level, the address register 3 is sent via the terminal 26a of the write control circuit 26, the OR circuit 29, and the terminal 26d.
1 is incremented, and address designation information is sent to the address bus 34 corresponding to the incremented value. The random access memory 32 enters a read operation upon designation of an address and sends data to the output data bus 33b. When MSB is “0”, inverter 30
Since the output side of is "1" and the read button 15 is not pressed, the terminal 26e is "1", so the AND circuit 30a becomes active and a write operation begins. When the MSB of the output data bus 33b is "1", one input side of the AND circuit 30a is at L level, and the write operation cannot be started, and the AND circuit 30b becomes active and sets the flip-flop 27. When the flip-flop 27 is set, the output terminal Q becomes H level, and the read operation continues until data without a flag is sequentially read out in synchronization with the clock pulse φ until reset.
When the MSB becomes "0", the AND circuit 30a becomes active and a write operation starts, and at the same time the flip-flop 27 is reset.

When the user wants to erase the flag, the flag erase button 13 and the flag button 15 are pressed at the same time. When pressed, the output side of the inverter 20 of the flag writing circuit 19 goes to L level and the flag is erased.

The wireless communication device according to the present invention includes a flag writing means for writing together with the desired data a flag for prohibiting erasure of the desired data written in the random access memory, and a flag writing means for writing together with the desired data based on the contents of each written data. Since the structure is equipped with a flag detecting means for detecting the presence or absence of a flag, and a write address changing means for writing desired data to another area without erasing it when a flag is detected, it is determined whether writing is possible or not based on the presence or absence of a flag. However, it has some special features. This has the effect of allowing desired data to be saved regardless of the address of the random access memory, and the utilization of the random access memory is improved compared to data processing methods that allow erasure of data only in a specific data area. You can improve.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional wireless communication device, Figure 2 is a block diagram of a conventional wireless communication device.
The figure is a block diagram including part of a logic circuit showing an embodiment of a wireless communication device according to the present invention. Code 1 in the diagram
is an antenna, 2 is a high frequency amplification circuit, 3 is a mixer,
4 is an intermediate frequency amplification circuit, 5 is a PLL circuit, 6 is a transmitting/receiving frequency selection circuit, 7 is a transmitting/receiving frequency automatic sweep circuit, 8 is an operation panel, 9 is an operation mode button, 10
is the channel step button, 11 is the frequency selection dial, 12 is the automatic memory button, 13 is the flag erase button,
14 is a flag button, 15 is a read button, 16 is a write button, 17 is an address designation dial, 18 is an address selection pulse generation circuit, 19 is a flag write circuit, 20 is an inverter, 21 is a switch, 22
is a diode, 23 is a busy channel detection circuit, 2
4 is a voltage detection circuit, 25 is an AND circuit, 26 is a write control circuit, 27 is a flip-flop, 2
8, 30a, and 30b are AND circuits, 30 is an inverter, 29 is an OR circuit, 31 is an address register, and 32 is a random access memory.

Claims (1)

[Claims] 1. In a wireless communication device having a transmitting/receiving frequency selection means for selecting a channel in a transmitting/receiving frequency band, and a random access memory for writing and reading data related to the channel selected by the transmitting/receiving frequency selecting means, Flag writing means for writing together with the desired data a flag that prohibits erasure of the written desired data, and flag detection means for detecting the presence or absence of the flag written together with the data from the contents of each written data. and write address changing means for writing the desired data to another area without erasing it when the flag is detected, so that the channel in the transmitting/receiving frequency band can always be selected according to the desired data. A wireless communication device characterized by comprising: