JPH01184704A - Gain control system - Google Patents

Gain control system

Info

Publication number
JPH01184704A
JPH01184704A JP835988A JP835988A JPH01184704A JP H01184704 A JPH01184704 A JP H01184704A JP 835988 A JP835988 A JP 835988A JP 835988 A JP835988 A JP 835988A JP H01184704 A JPH01184704 A JP H01184704A
Authority
JP
Japan
Prior art keywords
level
gain
gain control
circuit
slice
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP835988A
Other languages
Japanese (ja)
Inventor
Hiromi Matsushige
松重 博実
Toshiharu Kawamura
川村 俊治
Masahiro Sato
昌宏 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Information and Telecommunication Engineering Ltd
Original Assignee
Hitachi Computer Peripherals Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Computer Peripherals Co Ltd, Hitachi Ltd filed Critical Hitachi Computer Peripherals Co Ltd
Priority to JP835988A priority Critical patent/JPH01184704A/en
Publication of JPH01184704A publication Critical patent/JPH01184704A/en
Pending legal-status Critical Current

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  • Digital Magnetic Recording (AREA)

Abstract

PURPOSE:To prevent a gain control amplifier from being disabled at its gain setting, to prevent a data output from being saturated and to prevent a tape mark from being undetected by amplifying the amplitude level of an output signal from an amplitude reference area in stages and comparing the output amplitude with a prescribed reference level. CONSTITUTION:A slice voltage obtained from a slice voltage generating circuit 6 is compared with a signal level outputted from a differentiating circuit 4 for a head output obtained from a magnetic head 1 and a gain control circuit is driven through a gain setting circuit 8 until both the values coincide with each other to automatically execute gradational gain control. The number of steps of the gradational gain is counted up by a prescribed number by a counter 7, and when a slice level can not be obtained, a slice voltage generating circuit 6 is driven to drop the slice level. If a VAL/SNS signal is outputted at the time of dropping the slice level, the count number is reduced down to the previously determined value to allow a program go to the succeeding data block. Consequently, problems such as the undetection of a tape mark due to the excessive amplification of noise can be removed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は利得制御方式に係り、特に磁気テープ装置の利
得制御方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gain control method, and particularly to a gain control method for a magnetic tape device.

〔従来の技術〕[Conventional technology]

従来の磁気テープ装置におけるグループ・コーーfイド
番レコーディング(以下、OCRといつ)モード時にお
いては、磁気テープの開始点BOTの直後に設けた振幅
基準領域(以下、ARAという)内で、読出し回路系の
利得を階段状に上げ。
In the group code number recording (hereinafter referred to as OCR) mode in a conventional magnetic tape device, the readout circuit operates within the amplitude reference area (hereinafter referred to as ARA) provided immediately after the start point BOT of the magnetic tape. Increase the system gain in steps.

利得制御アンプの出力が所定レベルに到達されず。The output of the gain control amplifier does not reach the specified level.

利得設定が不可能になる場合があった。この種の技術と
して関連するものに特開昭57−33416号が〔発明
が解決しようとする褥咎+〕 上記従来技術では、利得の設定が最高ステップ付近で設
定された場合1次のデータブロックで出力の飽和、ノイ
ズの過剰増幅によるテープマークの未検出等の問題があ
った。
In some cases, it became impossible to set the gain. Related to this type of technology is Japanese Patent Application Laid-Open No. 57-33416 [The problem to be solved by the invention +] In the above-mentioned conventional technology, when the gain is set near the highest step, the primary data block There were problems such as output saturation and tape marks not being detected due to excessive noise amplification.

本発明の目的は、磁気テープのARA部の欠陥等に起因
する利得制御アンプのゲイン設定不能を回避することの
できる利得制御方式、及びデータ出力の飽和、テープマ
ークの未検出を回避すると上記目的は、スライスレベル
を下げた時にVAL・’SNS信号が出力されていれば
、カウント数を予め定めた値まで下げて次のデータブロ
ックに進む。
An object of the present invention is to provide a gain control method that can avoid the inability to set the gain of a gain control amplifier due to defects in the ARA section of a magnetic tape, and to avoid saturation of data output and non-detection of tape marks. If the VAL/'SNS signal is output when the slice level is lowered, the count number is lowered to a predetermined value and the process proceeds to the next data block.

もしスライスレベルを下げた時にVAL−8NS信号が
出力されていなければ、5AGC−CHKを立て、書込
みを禁止するので、データ出力の飽和およびノイズの過
剰増幅によるテープマークの未検出等の問題はなくなり
、達成される。
If the VAL-8NS signal is not output when the slice level is lowered, 5AGC-CHK is set and writing is prohibited, eliminating problems such as data output saturation and undetected tape marks due to excessive noise amplification. , achieved.

〔作用〕[Effect]

磁気ヘッドが読出すヘッド出力は、プリアンプおよび利
得制御回路を介して増幅される。レベル比較回路では、
スライス電圧発生回路からのスライス電圧と磁気ヘッド
から得られたヘッド出力の微分回路の信号レベルが比較
され、これらの値が一致するまで利得設定回路を介して
利得制御回路に作用し自動的に階調的利得調整がなされ
てゆく。
The head output read by the magnetic head is amplified via a preamplifier and a gain control circuit. In the level comparison circuit,
The signal level of the differentiating circuit of the slice voltage from the slice voltage generation circuit and the head output obtained from the magnetic head is compared, and the signal level is automatically applied to the gain control circuit via the gain setting circuit until these values match. Tonal gain adjustments are made.

この階調的利得のステップ数をカウンターにて所定のカ
ウント数までカウントアツプし、スライスレベルが得ら
れなければスライス電圧発生回路に作用シスライスレベ
ルを下ケる。スライスレベルを下げた時にVAL−8N
S信号が出力されてぃ九ばカウント数を予め定めた値ま
で下げて次のデータブロックに進む。もしスライスレベ
ルを下げた時に、VAL−8NS信号が出力されていな
ければ、5AGC−CHKを立て書込みを禁止すること
で、データの飽和、ノイズの過剰増幅によるテープマー
ク未検出等の問題はない。
The number of steps of this gradation gain is counted up to a predetermined count number by a counter, and if the slice level is not obtained, the slice voltage generation circuit is operated to lower the slice level. VAL-8N when lowering the slice level
When the S signal is output, the count number is lowered to a predetermined value and the process proceeds to the next data block. If the VAL-8NS signal is not output when the slice level is lowered, by setting 5AGC-CHK and inhibiting writing, problems such as data saturation and non-detection of tape marks due to excessive noise amplification will not occur.

〔実施例〕〔Example〕

以下1本発明の一実施例を第1図により説明する。 An embodiment of the present invention will be described below with reference to FIG.

第1図において、磁気ヘッド1からの信号はプリアンプ
2に入力している。VRIは可変抵抗器であってPEモ
ードでのヘッド回路系の読出し電圧のバラツキを補正す
るためのものである。磁気ヘッド1から続出された信号
はプリアンプ2を経由して更に増幅するため、利得制御
回路3に入力する。この利得制御回路3は利得設定回路
8から伝達されるディジタル信号にもとづいてその利得
が調整されるように構成されている。利得制御回路3で
増幅された信号は微分回路4に入力している。この微分
回路4は利得制御回路3の信号ビークを検出する増幅器
である。微分回路4で微分された信号は次にレベル比較
回路5に接続している。
In FIG. 1, a signal from a magnetic head 1 is input to a preamplifier 2. In FIG. VRI is a variable resistor that is used to correct variations in the read voltage of the head circuit system in PE mode. The signals successively output from the magnetic head 1 are input to a gain control circuit 3 via a preamplifier 2 for further amplification. This gain control circuit 3 is configured so that its gain is adjusted based on a digital signal transmitted from a gain setting circuit 8. The signal amplified by the gain control circuit 3 is input to the differentiation circuit 4. This differentiating circuit 4 is an amplifier that detects the signal peak of the gain control circuit 3. The signal differentiated by the differentiating circuit 4 is then connected to a level comparing circuit 5.

このレベル比較回路5は、微分回路4によって微分され
たアナログ波形振幅が規定値になっているか否かを判別
するものであって、スライス電圧を発生させるスライス
発生回路6から、基準電圧Tsが印加されている。利得
設定回路8は利得制御回路3の利得を調整し、利得アッ
プ信号発生部を内蔵している。この利得アップ信号発生
部は、1α〜15αのステップをもたせるため、4ビツ
トの制御信号をもたせる。そしてこの利得アップ信号発
生部ステップ1α〜15αは前記レベル比較回路5から
伝達される制御信号にもとづきディジタル信号を発生し
、これにより利得制御回路3の利得が制御されるように
構成されている。7はカウンターで利得アップ信号をカ
ウントアツプし、例えばカウント数101CなるまでV
AL−8NS信号が検出されなければスライス電圧発生
回路に作用しスライスレベルを下げる。9はアンドゲー
トであって。
This level comparison circuit 5 determines whether or not the analog waveform amplitude differentiated by the differentiator 4 is a specified value. has been done. The gain setting circuit 8 adjusts the gain of the gain control circuit 3 and includes a gain up signal generating section. This gain up signal generating section has a 4-bit control signal in order to have steps of 1.alpha. to 15.alpha. The gain up signal generator steps 1α to 15α are configured to generate digital signals based on the control signal transmitted from the level comparison circuit 5, thereby controlling the gain of the gain control circuit 3. 7 counts up the gain up signal with a counter, and for example, V until the count number 101C is reached.
If the AL-8NS signal is not detected, it acts on the slice voltage generation circuit to lower the slice level. 9 is an and gate.

利得設定回路7からの出力信号VAL−8NS信舟と書
込み制御信号WRT−Pのアンドを取り。
The output signal VAL-8NS Shinshu from the gain setting circuit 7 and the write control signal WRT-P are ANDed.

5AGC拳CHK信号を出力する。5AGC fist CHK signal is output.

第2図は、階段状利得曲線、VAL−8NS信号および
5AGC−CHK信号のタイミングを示している。
FIG. 2 shows the step gain curve, the timing of the VAL-8NS signal and the 5AGC-CHK signal.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、磁気テープのARA領域に欠陥が存在
しても、磁気テープの性能に応じた範囲で、データの書
込みを可能にすることができるので、他の磁気テープ装
置との互換性を保持した書込み品質のデータをテープ上
に書込むことができる効果がある。また読出し時におい
て、利得の設定値が増加することを防止できるので、デ
ータ出力の飽和およびテープマークの未検出を回避でき
る効果がある。
According to the present invention, even if there is a defect in the ARA area of the magnetic tape, it is possible to write data within a range that corresponds to the performance of the magnetic tape, thereby improving compatibility with other magnetic tape devices. This has the advantage of being able to write data on the tape at a writing quality that maintains the quality. Furthermore, since it is possible to prevent the gain set value from increasing during reading, it is possible to avoid saturation of data output and non-detection of tape marks.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の利得制御方式を実施する装
置の構成図、第2図は第1図に示す構成の動作説明図で
ある。 1・・・磁気ヘッド、    2・・・プリアンプ。 3・・・利得制御回路、  4・・・微分回路。 5・・・レベル比較回路。 6・・・スライス電圧発生回路。 7・・・カウンター、    8・・・利得設定回路。 9・・・アンドゲート。 第 f 図 第 2 図 、−y− 1−」
FIG. 1 is a block diagram of an apparatus implementing a gain control method according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of the structure shown in FIG. 1. 1...Magnetic head, 2...Preamplifier. 3... Gain control circuit, 4... Differential circuit. 5...Level comparison circuit. 6...Slice voltage generation circuit. 7...Counter, 8...Gain setting circuit. 9...and gate. Fig. f Fig. 2, -y- 1-''

Claims (1)

【特許請求の範囲】[Claims] 1、振幅基準領域およびデータブロックを有する磁気テ
ープの利得制御方式において、前記振幅基準領域におけ
る出力信号の振幅レベルを階段状に増幅し、この出力振
幅を所定の基準レベルと比較することにより、所定の時
間内に振幅レベルが基準レベルに到達しない場合には、
基準レベルを所定の範囲で降下させ、振幅レベルが基準
レベルを越えたならば予め定められた設定値に利得を設
定し書込みの禁止を解除することを特徴とする利得制御
方式。
1. In a gain control method for a magnetic tape having an amplitude reference area and a data block, the amplitude level of an output signal in the amplitude reference area is amplified in a stepwise manner, and this output amplitude is compared with a predetermined reference level to obtain a predetermined value. If the amplitude level does not reach the reference level within the time
A gain control method characterized in that the reference level is lowered within a predetermined range, and when the amplitude level exceeds the reference level, the gain is set to a predetermined setting value and write inhibition is canceled.
JP835988A 1988-01-20 1988-01-20 Gain control system Pending JPH01184704A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP835988A JPH01184704A (en) 1988-01-20 1988-01-20 Gain control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP835988A JPH01184704A (en) 1988-01-20 1988-01-20 Gain control system

Publications (1)

Publication Number Publication Date
JPH01184704A true JPH01184704A (en) 1989-07-24

Family

ID=11691037

Family Applications (1)

Application Number Title Priority Date Filing Date
JP835988A Pending JPH01184704A (en) 1988-01-20 1988-01-20 Gain control system

Country Status (1)

Country Link
JP (1) JPH01184704A (en)

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