JPH01181232A - Finite field inverse element circuit - Google Patents

Abstract

PURPOSE:To decrease the quantity of hardware constituting the circuit by constituting the finite field inverse element circuit of an arithmetic circuit applying addition, multiplication and inversion of a subfield GF(2<n>) of the order 2n of a GF(2<2n>). CONSTITUTION:An adder circuit 11 adds outputs of a multiplication circuits 7, 6 to output a result a0(a0+f1a1)+f0a, an inverse element circuit 12 calculates the inverse element to output 1/(a0(a0+f1a1)+f0a }. Finally, the output of the inverse element circuit 12 and the output of the adder circuit 10 are multiplied by a multiplication circuit 8 to output (a0+f1a1)/{a0(a0+f1a1)+f0a }, and the output of the inverse element circuit 12 and the value a1 are multiplied by a multiplication circuit 0 to output a1/{a0(a0+f1a1)+f0a }. Thus, the inverse element circuit of the GF(2<2n>) is obtained by an arithmetic circuit comprising combinations of adder circuits and inverse element circuits on the GF(2<n>).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to finite field source circuits used in encoders and decoders.

[Conventional technology]

In general, the input is a Galois field element expressed as a vector,
If a circuit that outputs the inverse of an input source in a vector representation is constructed as a gate circuit, the amount of hardware increases, so conventionally it has been constructed using a ROM. An example of a finite field source circuit using this ROM is Yoshida et al., "A study on the decoding method of R8 code using Galois arithmetic unit," Proceedings of the 6th Symposium of the Society for Information Theory and Its Applications @P 167-
170. As described in 1986, there was one shown in Figure 6. This shows the case of the Galois field GF(2') of order 2, where Xj 10X'+X''10X2+1 is taken as the primitive polynomial of GF(2') on GF(22n). xo, x..., Xy is the input source, which is means.

Further, yI,, yl, .

Also, this ROM stores contents as shown in Fig. 7, for example (X,, x8, ..., xr).
When =(01000000) is input, its inverse element (y,,yl,...,y7)=(011
01001) is output.

[Problem to be solved by the invention]

A circuit using this ROM has a large number of gates (and is difficult to integrate).

This invention has been made to solve the above-mentioned problems, and aims to significantly reduce the amount of hardware that constitutes a circuit for calculating the inverse of a finite field.

[Means for Solving the Problems] - The finite field inverse element circuit according to the present invention receives as input an element of an order 225 Galois field GF (22fL), and a part of the order 2FL that is included in GF (2''). The element α not included in the field GF(2yL), and the element a0 of GF(2”), “Is usf
By l, a = f, ten f, α, and the input source is a. When expressed as 10a and α, start from the input source and perform addition, multiplication, and inverse element operations. ao + f + at) / (ao (aa
+f, at) 10La",)" and "+'("a
(a, tenf, at) tenf. GF that outputs aZ)
(2”) of arithmetic circuits.

[Effect]

In this invention, the finite field inverse element circuit converts the element of GF(2'') into GF(22n) on GF(22n) which is fixed in advance.
After inputting the expression in terms of the basis of , addition, multiplication, and inverse element operations are performed on GF(2'), and the inverse element of the input element is output.

〔Example〕

FIG. 1 is a logic circuit diagram of an embodiment of a finite field inverse element circuit according to the present invention. (1) is the input GF (22n
), and p, , pH1..., RN-1 each represent O or 1. This changes the input sources to the pre-fixed elements α of GF(22yL) and 2 of GF(2”).
With one element β, β2, ..., β21-5, the basis (βo1β) of GF(22n) on GF(22n)
6,..., β, t-1, β1α, β, lL+l
It is expressed in terms of α, . (22n), (3) is C
Element fa of GF(2n) when 2 is expressed as f, 10f, and a
, f+ on GF (22n), respectively.
') is an input source expressed in terms of an appropriate basis of F,
, F..., F.

and Gos GIi-' and Gn-11 represent 0 and ζ represent 1, respectively.

(41, (5), (6), (7), (8), (9) are G
It is a multiplication circuit on F(2'), and G expressed as a vector
Two elements of F(2”) 5l)N S1% ”’ ”’,
5vt-+ and tos t1'i ''..., t
With %-I as input, the product of two elements is G on GF (22n)
Expressed in terms of an appropriate basis of F(2”), “(1%”
j, . . . are output as LIK-1. (101, (11) are adder circuits on GF (2 large), and vector representations of GF (2”) (7) two, 7
) elements x0, x, ・−・−1x machine−l and yo, y
Take ll ......, y ya, as input, express the sum of the two elements in terms of an appropriate base of GF (2'') on GF (22n), and Zolz ......, z, (122n) is the source circuit on GF(2''), which outputs the element v of GF(2') expressed as a vector.
,, v, , ..., v6-1 is input, and the inverse of the input source is expressed in terms of an appropriate base of GF (2'') on GF (22n), w,, town, . ..., W?L-
It is output as 1. (13) is the output G
F(22n), QOSQl,...
, Q zn-+ represent 0 or 1, respectively. this is,
Multiplication 1 (GF (22) where the output light of 81 is expressed
Let the basis on GF(2
2n) the basis on (ε., C5, -----1---...
..., C5-22n), the output light (13)
This means that Σ(Q,: δj+Q, a, εtα).

Next, it will be shown that the output element (13) is the inverse element of the input element (1). Input source Σll0 (P4: β7 + p, 14. + β subtraction j of GF (22n)) For (22n), input elements a0 and al of GF (2yL), a, = ?
, P7βi% "l=hole PfLhj k+l, the input source can be written as a6+"tα.

a is multiplied by f in the multiplication circuit (4) and becomes f,
Output at. The adder circuit adds io to this and a
, +tla, and the multiplier circuit (7) outputs a.

Multiply by a.

Outputs (aa+f, a,). In addition, al is squared by multiplication # (51), and further multiplied by f in multiplication # (8) to output 1g71〒. In addition # (11), the output of multiplication circuit (7) and the multiplication circuit Add the output of (6) and output io (ao ten f I & +) ten fo ”?
The inverse element is taken in the source circuit (122n) and becomes 1/(aa (
a, -1-t, al) + f. a? ) is output. Finally, the output of the source circuit (122n) and the output of the adder circuit - are multiplied by the multiplier circuit (8) (io + Lat) /
(ao(ao+f, a,) 10f0m", l is output, and the output of the inverse element # (122n) and a are the multiplication circuit (
9) multiplied by a, / (io (ao+fl a
t) Output 10fosi). As a result, output (13)
Then, the element of GF (2”) [(aa+ f+”+) /
(1o(ao+f1ad) + r, a?)) ten [al
ff / (ao(a, 10 Lad) + foa?)) will be obtained, but here this output source and input source ao
It can be easily calculated that it becomes 1 by multiplying by 10a and α, which shows that the output source gives the inverse of the input source.

As a result of the above, the source circuit of GF(2”l) is changed to GF(21
) It has been shown that the above can be obtained by an arithmetic circuit consisting of a combination of an adder circuit, a multiplier circuit, and a source circuit, but an embodiment in which a finite field inverse circuit is configured as a gate circuit based on the above principle will be described below.

FIG. 2 is a logic circuit diagram of an embodiment of a finite field inverse element circuit of GF(28) when n of GF(22n) is set to 4. In Figure 2, (14) is the input G
This is the element of F(2''), which corresponds to the input source (1) in Figure 1.Here, the elements αtL, rGF (
22n) Upper primitive polynomial X'+X'+X''+X21
Take the root of , define the element β of GF(2') as α17, and β
′ is β′. That is, the input source means the element of GF(2'') iμ&β20P44□·β'a).

(]5) multiplies the input GF(2') by β, and
The basis (1, β,
It is a multiplication circuit that expresses and outputs in terms of β', 4,
Consists of exclusive OR gate (36), a2=β+β
This corresponds to the multiplication circuit (4) in FIG. (16) squares the element of the input GF(2') and divides it by β.
This is a multiplication circuit consisting of an exclusive OR game (36) which is expressed in terms of the bases (1, β, β', β1) of This corresponds to the output of (6). (17),
(18) is an adder circuit on the GF (22n), which corresponds to the adder circuits (10) and (11) in FIG. 1, respectively. (19), (20), (21) are GF (22
n), so a multiplier circuit calculates the product of the two input elements as GF(22n
) on the basis of GF (22n) (1, β, β', βB)
The multiplier circuit shown in Figure 1 (
7), (8), and (9), and the logic circuit diagram thereof is shown in FIG. (222n) is GF(2'
), the inverse of the input source is converted to G on GF(22n).
It outputs the bases (1, β, β', β3) of F(2'), and corresponds to the source circuit (122n) in Figure 1, whose logic circuit diagram is shown in Figure 4. . (2
3) is the source of the output GF (22n), which meaningfully satisfies i<Qtβ'+Q4+iβ'd). Figure 3 shows the multiplication circuit on GF(2'),
(22n) base of GF(2') (1, β, β', β
1) GF (22n) (7) expressed in terms of two elements s,,s.

, S, , 33 and t,-tl ,”t,js
7cuo, ul, ut, us of GF (22n) expressed in terms of the basis (1, β, β', β forces)
The output is (24), (25),
(26), respectively, multiply the input source by β to the basis (1, β
, β', β3), and is composed of an exclusive OR game (36). In FIG. 3, (37) is an exclusive OR gate, and (38) is an AND gate.

Figure 4 shows the source circuit on GF(2'), GF(22
7C of GF (22n) expressed in terms of the basis (1, β, β', β3) of GF (2') on n); VO-Vl
-Vz-Va as input, base (1, β, β', βB)
The redundancy W of GF (22n) expressed in terms of.・－・w
The output is B·wB. (27) is a basis conversion circuit that converts the input element expressed in terms of (1, β, β', β1) into (1, γ, β, γβ). (28) is the inverse basis conversion circuit of the basis conversion circuit (27), and the basis (1, γ, β, γβ
) is the input source expressed in terms of (1, β, β′, β′)
It converts into an expression regarding the basis.

(29) takes as input the element of GF(2') expressed in terms of the base (1, γ, β, γβ), and the inverse element of the input element as the base (
1, γ, β, γβ) and outputs the expression, and is an addition [*
(30), (31), multiplication times on GF (222n) #
(322n), (33), (34), and an inverse element #(35) consisting of an exclusive OR gate (36). This can be constructed in the same manner as in FIG. That is, β
Since 2 = γ + β, the circuit corresponding to the multiplication circuit (15) in Fig. 2 is unnecessary in this sending circuit (29), and the circuit corresponding to the multiplication circuit (16) in Fig. 2 is This source circuit (29) only needs to switch the two input signals and output them. Further, the adder circuits (30) and (31) correspond to the adder circuits (17) and (18) in FIG. 2, respectively, and the multiplier circuits (322n), (33), and (34) correspond to the multiplier circuits ( 19), (20), and (21), the source circuit (35) corresponds to the source circuit (222n) in FIG.

Note that the multiplication circuits (322n), (33), and (34) are the third
The logic circuit can be constructed as shown in FIG. 5 using the same concept as shown in the figure.

In this way, in the above embodiment, the inverse element #i of the finite field can be easily constructed, and a ROM is not required in the case of the source circuit of GF (28) as described above.

〔Effect of the invention〕

As mentioned above, the finite field source circuit of this invention is GF(
Since it consists of an arithmetic circuit that performs addition, multiplication, and inversion of the subfield GF(2?L) of order 2n of 2"), the amount of hardware that makes up the circuit can be significantly reduced, making the circuit compact. This improves reliability and consumes less power.

Therefore, it will be convenient to apply it to encoders and decoders related to information transmission, which will be developed in the future.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram of a finite field source circuit showing one embodiment of this invention, and FIG. 2 is a logic circuit diagram of a finite field source circuit showing another embodiment of this invention.
The logic circuit diagram of the finite field source circuit of F (22n), Figure 3 is the logic circuit diagram of the multiplication circuit of GF (22n),
Figure 4 is a logic circuit diagram of a finite field source circuit of GF (2'), Figure 5 is a logic circuit diagram of a multiplier circuit of GF (22n), and Figure 6 is a logic circuit diagram of a finite field source circuit using a conventional ROM. The logic diagram of the circuit, FIG. 7, is an explanatory diagram of the contents stored in this ROM. The code (1) in the figure is the input source of GF (22n), (22
n), (3) are the input sources of GF(2”), (4), (5
), (6), (7), (8), (9) are multiplication circuits, (1
0), (11) are adder circuits, (122n) is a source circuit,
(13) is the output source of GF (2-), (14) is GF (
22n) input sources, (15) and (16) are multiplication circuits, (
17), (18) are adder circuits, (19), (20),
(21) is a multiplication circuit, (222n) is a source circuit, (23
) is the output source of GF (22n), (24), (25),
(26) is a multiplication circuit, (27) is a base conversion circuit, (28
) is the inverse basis conversion circuit, (29) is the source circuit, (30),
(31) is an adder circuit, (322n), (33), (34
) is a multiplication circuit, and (35) is a source circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] The input is an element of the Galois field GF(2^2^n) of order 2^2^n, which is included in GF(2^2^n) and whose order is 2^n.
elements α that are not included in the subfield GF(2^n) of and GF
By the elements a_0, a_1, f_0, f_1 of (2^n), α=f_0+f_1α, and the input source is a_0+a_1
When expressed as α, addition and multiplication of GF(2^n) from the input source,
Perform inverse element (a_0+f_1a_1)/{a_0(a_
0+f_1a_1)+f_0a_1^2} and a_1
/{a_0(a_0+f_1a_1)+f_0a_1^
A finite field inverse element circuit characterized by comprising an arithmetic circuit that outputs 2}.