JPH01179642U - - Google Patents
Info
- Publication number
- JPH01179642U JPH01179642U JP1988074815U JP7481588U JPH01179642U JP H01179642 U JPH01179642 U JP H01179642U JP 1988074815 U JP1988074815 U JP 1988074815U JP 7481588 U JP7481588 U JP 7481588U JP H01179642 U JPH01179642 U JP H01179642U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- reception
- transmission
- control unit
- ptt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Electric Clocks (AREA)
- Transceivers (AREA)
Description
第1図はこの考案に係るトランシーバの実施例
を示したブロツク図である。
主な番号の説明、2:アンテナ切換器、3:受
信部、5:スケルチ回路、6:AF増幅器、8:
送受信制御部、9:PTT操作スイツチ、10:
送信部、12:論理和(OR)回路、13:タイ
マ回路、14:アラーム発生回路。
FIG. 1 is a block diagram showing an embodiment of a transceiver according to this invention. Explanation of main numbers, 2: Antenna switcher, 3: Receiver, 5: Squelch circuit, 6: AF amplifier, 8:
Transmission/reception control section, 9: PTT operation switch, 10:
Transmission section, 12: OR circuit, 13: timer circuit, 14: alarm generation circuit.
Claims (1)
を行うトランシーバにおいて、 受信部に構成されているスケルチ回路のアンス
ケルチ信号と、送受信制御部に設けられたPTT
操作スイツチにより設定されるPTT信号と、こ
のアンスケルチ信号とPTT信号との論理和(O
R)を取つて出力する論理和(OR)回路と、こ
の論理和(OR)回路の出力信号によつて計時を
開始するタイマ回路と、このタイマ回路によつて
作動するアラーム発生回路とを備えたことを特徴
とするトランシーバ。[Claim for Utility Model Registration] In a transceiver that performs transmission and reception communications under the control of a transmission/reception control unit, an unsquelch signal from a squelch circuit configured in the reception unit and a PTT provided in the transmission/reception control unit
The PTT signal set by the operation switch, the logical sum (O
R), a timer circuit that starts measuring time based on the output signal of the OR circuit, and an alarm generation circuit that is activated by the timer circuit. A transceiver characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988074815U JPH01179642U (en) | 1988-06-07 | 1988-06-07 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988074815U JPH01179642U (en) | 1988-06-07 | 1988-06-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01179642U true JPH01179642U (en) | 1989-12-22 |
Family
ID=31299905
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1988074815U Pending JPH01179642U (en) | 1988-06-07 | 1988-06-07 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01179642U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5746346B2 (en) * | 1979-08-21 | 1982-10-02 | ||
JPS5936442A (en) * | 1982-08-24 | 1984-02-28 | Matsushita Electric Ind Co Ltd | State display system of radio device |
-
1988
- 1988-06-07 JP JP1988074815U patent/JPH01179642U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5746346B2 (en) * | 1979-08-21 | 1982-10-02 | ||
JPS5936442A (en) * | 1982-08-24 | 1984-02-28 | Matsushita Electric Ind Co Ltd | State display system of radio device |
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