JPH01179433A - Active wiring element, active wiring process using the element and manufacture thereof - Google Patents

Abstract

PURPOSE:To collectively form a wiring structure very easily without increasing the space inside an integrated circuit by a method wherein a multilayer wiring structure is formed of active wiring elements in the film thickness direction. CONSTITUTION:Active elements 2a, 2b, 2c are formed of active wiring elements on a semiconductor substrate 1 to form an interlayer insulating film 3 and a wiring metallic film 4 thereon. At this time, an interwiring active film 5 and a power supply wiring layer 6 are laminated on the metallic film 4. As for the active film 5, a super lattice multilayer thin film in band gap modulated mode and the periodicity of several Angstrom in the thickness direction is applicable. The metallic film 4 and the wiring layer 6 are isolated from each other by the active film 5 having non-linear electrical properties. Through these procedures, the wiring structure can be collectively formed very easily.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an active wiring element, an active wiring method using the element, and a method of manufacturing the active wiring element, and particularly relates to an active wiring element, an active wiring method using the element, and a method for manufacturing the active wiring element. The present invention relates to an active wiring element in which an active film is arranged, an active wiring system in which the element is connected between a signal line and a return line, and a method for manufacturing such an active wiring element.

[Conventional technology]

Generally, elements that make up a semiconductor integrated circuit have at least two terminals, and these terminals are used to transmit signals (in the form of changes in voltage or current) from one element to another.
are doing.

For example, a conductive semiconductor substrate itself and a low impedance power supply line are used as one of the two signal lines, and more specifically, a single polysilicon line on the surface of the semiconductor substrate after formation. A wiring structure or wiring method is adopted in which a signal is propagated using only wiring, one metal wiring, or one low-resistance diffusion layer.
- FIG. 7 is a sectional view of an element for explaining an example of a conventional active wiring element.

As schematically shown in FIG. 7, such an active wiring element includes an active element 2a formed on a semiconductor substrate 1 and next-stage elements 2b and 2c, and interlayer insulation formed on the substrate 1 to cover these elements. The active element 2a has a film 3 and a wiring metal TpA4 deposited from above the interlayer insulating film 3.
These connections are made using the wiring metal film 4.

Next, FIG. 8 is a wiring circuit diagram for explaining an example of an active Eve wiring circuit using such a conventional active wiring element.

As shown in FIG. 8, this active-eve wiring circuit is designed to prevent signal leakage between two wiring lines consisting of a signal line 7 and a return line 8 for connecting an active element 10 and a next-stage element 14. In both stages f&, the wirings are separated by an insulating material shown as a capacitor C. Furthermore, the two wirings, the signal line 7 and the return line 8 made of a semiconductor substrate or a power supply line, are also separated by the insulating material.

Therefore, as shown in FIG. 8, elements in a conventional integrated circuit can be regarded as being coupled by a type of transmission line if treated strictly. At the clock frequency used in normal semiconductor integrated circuits, the inductance component of the wiring can be ignored, and in the transmission line consisting of the signal line 7 and the return line 8, resistance (R) due to the layer resistance of the wiring layer
Capacitance (C
) components are dominant. Incidentally, since the impedance of the semiconductor substrate and power supply line on the return line 8 side is sufficiently low, this impedance can be ignored.

In addition, in the conventional manufacturing method of active wiring elements, it is sufficient to connect elements using a single layer of wiring metal film.
This is achieved using normal lamination technology and etching technology.

[Problem that the invention seeks to solve]

Due to the progress of higher density and miniaturization of integrated circuits mentioned above, the line width of signal lines has been reduced, and due to restrictions in the manufacturing process, the thickness of the signal line layer has also become greater than a certain ratio with the line width. Since it is difficult to increase the thickness of the signal line, the cross-sectional area of the signal line continues to decrease. Therefore, the wiring resistance per unit length increases in proportion to the square of the reduction rate.

On the other hand, the wiring capacitance per unit length decreases in inverse proportion to the multiplication factor between the 0th power and the 1st power of the reduction rate due to the two-dimensional spreading effect from the end of the wiring.

Therefore, the CR time constant of wiring per unit length is 1 of the reduction rate.
It increases in proportion to the ride between the power and the square.

However, the high speed of an integrated circuit as a whole is determined by the propagation delay in the critical path, which takes the longest time for signal propagation.

The length of this critical path tends to increase as the complexity of integrated circuits increases. Therefore, the above-mentioned increase in the CR constant has the disadvantage that it impedes the high speed performance of the integrated circuit.

The objects of the present invention are to provide an active wiring element that reduces the circuit area of the conventional circuit, an active wiring method that uses this element to reduce wiring delay problems and realize high speed, and a wiring layer that is not restricted by dimensional accuracy. An object of the present invention is to provide a method of manufacturing an active wiring element that can be efficiently manufactured.

[Means for solving problems]

The active wiring element of the present invention includes a plurality of active elements formed on a semiconductor substrate, an interlayer insulating film coated on the semiconductor substrate including the elements, and an opening in the interlayer insulating film on the plurality of active elements. It consists of a wiring metal film deposited on the interlayer insulating film, and a material or structure having nonlinear electrical characteristics.

The wiring metal film and the power supply wiring include an inter-wiring active film deposited on the wiring metal film and a power wiring layer laminated on the inter-wiring active film, and electrically connect the plurality of active elements. It is constructed by separating the layers.

Further, the active wiring method using the active wiring element of the present invention includes a plurality of active elements formed on a semiconductor substrate, an interlayer insulating film coated on the semiconductor substrate including the element, and a plurality of active elements formed on the plurality of active elements. An interconnection metal film which is deposited on the interlayer insulating film through an opening in the interlayer insulating film, an interwiring active film made of a material or structure having nonlinear electrical characteristics and deposited on the interconnection metal film, and the interwiring active film. an active wiring element including a power wiring layer laminated thereon and having at least two electrically different parts separating the wiring metal film electrically connecting the plurality of active elements and the power wiring layer; The signal line and its return line are electrically connected so that one side is connected to the signal line and the other side is the return line.

Furthermore, the method of manufacturing an active wiring element of the present invention includes a step of forming a plurality of active elements on a semiconductor substrate in a method of manufacturing an active wiring element having a plurality of active elements and a plurality of wiring layers on a semiconductor substrate. , a step of covering the semiconductor substrate including the elements with an interlayer insulating film; a step of opening the interlayer insulating film on the plurality of active elements and depositing a wiring metal film over the interlayer insulating film; A step of depositing a multilayer inter-wiring active film on the interconnect metal film, which is made of a material or structure having non-linear electrical characteristics, and a step of laminating a power supply wiring layer on the inter-wiring active film, using a lithography method. The method includes a step of forming a wiring pattern on a resist film coated on the power supply wiring, and a step of collectively transferring the wiring pattern onto at least the multilayer inter-wiring multilayer film.

[Effect]

The active wiring element of the present invention includes a plurality of active elements formed on a semiconductor substrate, an interlayer insulating film coated thereon,
A wiring metal film deposited on the active element through an opening in the interlayer insulating film, an inter-wiring active film made of a material or structure having nonlinear electrical characteristics, and a power supply wiring layer laminated on the inter-wiring active film. Accordingly, the wiring metal film that electrically connects the plurality of active elements and the power supply wiring layer are separated.

Next, the active wiring system using the active wiring element of the present invention separates a signal line and a return line using a material or structure having nonlinear electrical characteristics (hereinafter referred to as a nonlinear material). The nonlinear material is generally layered and is in electrical contact with the signal line on one side and the return line on the other side. In the same way that both the signal line and the return line can be regarded as distributed constant lines, the nonlinear material can be regarded as a multi-terminal circuit in which two-terminal devices are distributed between the signal line and the return line. Therefore, when electrodes are attached to one side and the other side of this nonlinear material and its characteristics as a two-terminal element are measured, if it has the nonlinear characteristics of a two-terminal element, it can be used as an active wiring element. Can be done.

Next, in the method for manufacturing an active wiring element of the present invention, when forming a wiring structure, instead of forming a conventional single or multilayer conductive film (usually a metal film), a -layer or multilayer conductive film (usually a metal film) is used. Following the formation of the film, a single thin film of a nonlinear material or a multilayer film that exhibits nonlinear characteristics when made into multiple layers is deposited, and then another layer or multilayer conductive film is formed, and a series of these multilayer films is used. are formed all at once, just like a conventional wiring layer.

As a result, the bottom conductive film in a series of multilayer films makes electrical contact with the underlying device through the contact hole, and the top conductive film has a low impedance due to the conventional wiring process for the second layer. can be electrically connected to the power supply line. That is, by adding a series of multilayer film forming steps, the wiring structure can be easily formed all at once.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of an active wiring element according to an embodiment of the present invention.

As shown in FIG. 1, such active wiring elements include active elements (such as MOS transistors) 2a,
2b and 2c are formed, and an interlayer insulating film 3.2b and 2c is formed thereon. The structure up to the formation of the wiring metal film 4 is the same as the conventional one, and the difference lies in the structure in which the inter-wiring active film 5 and the power supply wiring layer 6 are laminated on the wiring metal film 4. As the inter-wiring active film 5 formed between the wiring metal film 4 and the power supply wiring layer 6, a superlattice multilayer thin film in a bandgap modulation mode having a periodicity of several tens of people in the thickness direction is used. By using such a laminated structure, the two conductive materials, that is, the wiring metal film 4 and the power wiring layer 6, are electrically separated in the thickness direction by the inter-wiring active WA 5 having nonlinear electrical characteristics.

Such a multilayer structure can be regarded as a distributed constant circuit and converted into an equivalent circuit.

As explained above, the active wiring element of this example has a multilayer wiring structure that can be formed in the film thickness direction, so it can be formed with a simple geometric structure without increasing the area within the integrated circuit. effective.

Next, FIG. 2 is a circuit principle diagram for explaining one embodiment of the active wiring method according to the present invention.

As shown in FIG. 2, this block circuit is a circuit schematically showing the propagation of a signal at a certain point on the wiring. Electrical signals always propagate as energy waves (=Bointing vectors), in other words, as a combination of voltage and current. Normally, signals in a semiconductor integrated circuit propagate from the transmitting device to the receiving device at approximately the propagation speed of electromagnetic waves in the medium, but due to transmission loss, the energy waves that reach the receiving device are weak. , due to the need for discrimination from noise, energy waves are accumulated over a certain period of time at the receiving end, and in voltage-mode devices such as MOS devices, the signal voltage is reduced, and in current-mode devices such as bipolar devices, the energy wave is The presence or absence of signal propagation is determined by identifying whether each signal current exceeds a certain threshold value. Therefore, in order to reduce the delay time of interconnects between elements, it is necessary to increase the intensity of energy waves rather than reducing the signal propagation speed.

That is, the principle of the wiring system of the present invention is that by connecting one or more nonlinear circuits 9 in parallel between the signal line 7 and the return line 8, the intensity of the energy wave as described above can be increased in the middle of the transmission line. It is something to be carried out.

In the semiconductor integrated circuit mentioned above, energy.

- Although the source of waves is only the transmitting device, the receiving end actually absorbs energy waves not only by the receiving device but also by the resistance of the signal line and the capacitance between the signal line and the return line. The resistance of the signal line converts part of the energy wave into heat, and the capacitance between the signal line and the return line stores part of the energy wave as electrostatic energy. Furthermore, because electrostatic energy is accumulated in the capacitance between the signal line and the return line, the signal voltage VIN is generated and increases even in the middle of the transmission line. This is detected by the nonlinear circuit 9, and a current Is is injected from both ends of the nonlinear circuit 9 in a direction to strengthen the signal current. As a result, the source of energy waves is no longer just the transmitting device, but a device connected in parallel to the part of the transmission line that has accumulated more than a certain amount of signal energy.
The entirety of an infinite number of nonlinear circuits, including three or more or distributed nonlinear circuits, also serves as a source of energy waves. Moreover, since the size of the portion increases over time, the rate of energy accumulation at the receiving end of the receiving device can snowball. Therefore, the time to store energy up to the threshold can be reduced inversely to the storage rate. That is, signal propagation delay time can be reduced.

In short, in the wiring system of the present invention, the nonlinear circuit 9
is a circuit that releases current to the outside when the potential difference between terminals increases above a certain voltage, or further increases the potential difference between terminals to intensify the energy wave.
When viewed as a terminal element, it has a kind of negative resistance characteristic when turned into a device.

Next, FIG. 3 is a concrete active wiring circuit diagram using the principle shown in FIG. 2.

As shown in FIG. 3, in this embodiment, in a logic circuit having two or more cascaded next-stage elements 14 connected to an active element 10, the active element 10 is connected to the first next-stage element 14. FIG. 2 is a circuit diagram showing a wiring system between the In addition to the intrinsically existing resistance component R1 and capacitance component C, the wiring consisting of the signal line 7 and the return line 8 of this circuit includes a two-terminal element 11 having nonlinear characteristics and the signal line 7.
A precharge circuit 12 is connected in parallel to set the voltage to a constant potential in advance. Further, the return wire 8 has sufficiently low impedance. However, precharge circuit 1
2 was introduced to clarify an additional step to realize this wiring method, and the characteristics of the active element 10,
Alternatively, depending on the driving method of this wiring system, it is not necessarily necessary or essential.

Next, a driving method in the wiring system of this embodiment will be explained.

First, the precharge circuit 12 is turned on using the precharge circuit control signal line 13, and the signal line 7 is set to a predetermined potential VDD in advance. At this time, the active element 10
output impedance must be sufficiently high.

Next, the logic of the precharge circuit control signal line 13 is inverted, the output impedance of the precharge circuit 12 is set to a high level, and the signal line 7 is made floating. The bias condition of V=Vor in FIG. 4, which will be described later, is at an unstable point, and since . However, when the logic of the precharge circuit control signal line 13 is inverted and the active element 10 is activated at the same time, when the output logic signal is at a low level, the two-terminal element 11 starts injecting current, so the wiring capacitance C discharge is accelerated. Therefore, the time required for the potential of the signal line 7 at the input end of the next stage element 14 to fall to a low logic level is shortened. That is, the potential latched at the input terminal of the next stage element 14 after a certain period of time after driving the active element 10 is determined by whether the output logic level of the active element 10 is at a low logic level or a high logic level. can be set to a low logic level or a high logic level, respectively. In short, this means that one bit of logical information is transmitted to the next stage element in a shorter time than when transmitting signals using the conventional wiring method.

FIG. 4 is a voltage-current characteristic diagram of the circuit element shown in FIG. 3.

As shown in FIG. 4, this voltage-current characteristic is obtained when an infinite number of specific member resistance devices are distributed as the nonlinear circuit 9 in FIG. 2 or the nonlinear two-terminal element 11 explained in FIG. Let me explain with an example.

First, a device having voltage-current characteristics shown in FIG. 4 is used as a negative resistance device, but such characteristics can be realized by using, for example, a resonant tunnel device. The resistance and capacitance of the transmission line, and the characteristic quantities per unit length of the nonlinear circuit 9 are expressed as R, C, respectively.
Let it be i (V). ■ is the potential difference between both ends of the nonlinear circuit 9,
i is the terminal current per unit length.

Next, signal line 7 at position X1 and time t. Let the potential difference between the return wires 8 be V(x, t), and let the current flowing in the signal line 7 from the receiving end toward the transmitting end be I(x, t). In this governing equation, the capacitance of the nonlinear circuit 9 is the wiring capacitance C
It is assumed that there is no nonlinearity in C for the sake of simplicity. It is also assumed that the transmission line is semi-infinitely long.

The initial condition is V(x, O)=Von>0 (constant) −(3)
The boundary condition is V (0, t) = 0 (4)
That is, it is assumed that the transmitting device is placed at x=O, the driving capability of the transmitting device is infinite, and a transition from the on state to the off state is assumed. Here, the current i
As for (V), the characteristics shown in Fig. 4 are further simplified as follows: 1(V)=i□X (Vl<V<V2)...
・Set as (6). When l max-0, it corresponds to conventional wiring. In this case, voltage V(x, t) and current ■(
x, t) follows the diffusion equation with D=1/(RC) as the diffusion coefficient, and the solution is V(X, t) = Vooerf(X/ (2(Dt)”2))−・(7
). Note that erf is an error function.

Incidentally, FIG. 5 is a potential distribution diagram of the circuit elements in the wiring in FIG. 3.

As shown in Figure 5, if we consider ■2 as a threshold that captures the transition from on to off, then the point X where V(x, t) = ■2
It can be said that the faster the moving speed of 2(t), the shorter the wiring delay.

Moreover, since this moving speed is , it can be seen that the longer the wiring length, the more the wiring delay increases. This was a drawback of conventional wiring systems.

When i□8>0, the moving speed of xz(t) is, so the nonlinear circuit 9 has the effect of increasing the moving speed of the threshold point x2. At this threshold point x2, i (
Since V) is discontinuous, the spatial curvature of V(x, t) increases discontinuously (in the negative direction) in order to make the moving speed of X2(t) continuous. That is, the potential difference and current in the region where V>V2 behave as if the transmission source were driving the transmission line at a position close to each other.

In the above description, an N-type negative two-terminal element was modeled as the nonlinear circuit 9, but the present invention is not limited to this device. Furthermore, although the equations that describe the system differ depending on the nonlinear circuit 9 used, the same equations apply regardless of whether the device or circuit has two terminals or multiple terminals as long as the device or circuit positively feeds energy waves as a characteristic of the transmission line. It is a device that exhibits the functions of

In short, the active wiring system of the present invention described above has the effect of shortening the wiring delay time, thereby improving the high-speed operation of the integrated circuit.

Next, FIGS. 6(a) to 6(e) are device cross-sectional views shown in order of steps for explaining the method of manufacturing an active wiring device according to the present invention. It should be noted that the method for forming the element itself in the present invention is not an essential part, so a detailed explanation will be omitted.

First, as shown in FIG. 6(a), an active element 2 and an interlayer insulating film 3 are formed on a semiconductor substrate 1 by a series of element forming methods. Next, a contact hole is formed in the interlayer insulating film 3 by a phosphorography process and an etching process. Next, a wiring metal film 4 having a high melting point is deposited by the CVD method. At this time, the wiring metal film 4 is deposited to such an extent that the height of the lowermost part of the upper surface thereof is sufficiently higher than the height of the uppermost part of the upper surface of the interlayer insulating film 3.

Next, as shown in FIG. 6(b), a flattening etch-back method is applied to the wiring metal film 4 formed on the semiconductor substrate 1 to flatten the upper surface.

Next, as shown in FIG. 6(C), the semiconductor substrate 1 is placed in an ultra-high vacuum apparatus and subjected to a light sputtering process. next,
Approximately five silicon oxide films 15 are deposited on the interconnect metal film 4 that has been planarized on the semiconductor substrate 1 by vapor phase MBE.

Next, as shown in FIG. 6(d), about 50 silicon films 16 are deposited by the same vapor phase MBE method while maintaining the vacuum state in the same ultra-high vacuum apparatus.

Next, the surface of the silicon film 16 is activated by a lamp annealing method in the apparatus to promote surface movement, thereby improving the crystal axis orientation of the silicon crystal within the silicon film 16. In this case, since the underlying wiring metal film 4 is flattened, the reflected light from the wiring metal film 4 becomes uniform, and a silicon single crystal of relatively good quality can be obtained. Next, about five silicon oxide films 17 are deposited on the silicon film 16 by vapor phase MBE again, and silicon oxide films are formed, silicon films are formed, lamps are deposited, etc. Repeat the three steps of annealing,
An inter-wiring active film 5 having a superlattice structure made of a silicon oxide film and a silicon film is formed.

In addition, the resonance increases as the number of repetition cycles increases,
The ratio between I MAX and I MIN in FIG. 2 described above increases. Therefore, the number of cycles may be determined in consideration of the membrane capacitance, membrane resistance, and resonance of the active membrane 5. Next, a first power supply wiring layer 6 is formed on the superlattice active film 5, with the first part formed by the MBE method and the remaining part by the CVD method.

Next, as shown in FIG. 6(e), a lithography process and an etching process are performed to form the first power wiring layer 6. Inter-wiring active film 5. The wiring metal film 4 is patterned all at once, and an interlayer insulating film 20 is deposited. Next, a contact hole is formed in the interlayer insulating film 20 by a lithography process and an etching process again, and a second power supply wiring layer 21 is deposited thereon. Further, after patterning the second power wiring layer 21 by performing a lithography process and an etching process, a passivation film 22 is formed to obtain an active wiring element.

As described above, in this embodiment, by combining the simultaneous formation of multilayer films with the lithography method and the etching method, active wiring elements having such a wiring structure can be efficiently formed at once. That is, since this embodiment uses a multilayer film formation method to form the wiring structure, it is not limited by the dimensional accuracy of microfabrication technology, exposure technology, etc.

Although each embodiment of the present invention has been described above,
Although the wiring metal film 4 and the power supply wiring layer 6 in the active wiring element are separated in the film thickness direction, the present invention can be similarly practiced even if they are separated in the in-plane direction.

〔Effect of the invention〕

As described above, since the active wiring element of the present invention has a multilayer wiring structure that can be formed in the film thickness direction, it has the advantage that it can be formed without increasing the area within the integrated circuit.

Further, the active wiring method of the present invention has the effect of shortening the wiring delay time, thereby improving the high-speed operation of the integrated circuit.

Furthermore, since the method for manufacturing an active wiring element of the present invention uses a multilayer film formation method in forming the wiring structure, it has the advantage that it is not restricted by dimensional precision such as microfabrication technology or exposure technology.

[Brief explanation of the drawing]

FIG. 1 is an element cross-sectional view for explaining one embodiment of the active wiring element in the present invention, FIG. 2 is a circuit principle diagram for explaining one embodiment of the active wiring method in the present invention, and FIG. A concrete active wiring circuit diagram using the principle shown in Fig. 2, Fig. 4 is a voltage-current characteristic diagram of the circuit element shown in Fig. 3, and Fig. 5 is a potential distribution of the wiring circuit element shown in Fig. 3. 6(a) to 6(e) are device cross-sectional views shown in order of steps for explaining the method of manufacturing an active wiring device according to the present invention, and FIG. 7 is for explaining an example of a conventional active wiring device. FIG. 8 is a wiring circuit diagram for explaining an example of a conventional active Eve wiring circuit. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Active element, 3... Interlayer insulating film, 4... Wiring metal film, 5... Inter-wiring active film,
6...Power wiring layer, 7...Signal line, 8...Return line,
9... Nonlinear circuit, 10... Active element, 11...
Nonlinear two-terminal element (inter-wiring active film equivalent circuit), 12...
・Precharge circuit, 13...control signal line, 14...
・Next stage element, 15.17°19...silicon oxide film,
16.18... Silicon film, 20... Interlayer insulating film,
21... Second power wiring layer, 22... Passivation film.

Claims (3)

[Claims] (1) a plurality of active elements formed on a semiconductor substrate; an interlayer insulating film coated on the semiconductor substrate including the elements;
A wiring metal film formed by opening the interlayer insulation film on the plurality of active elements and deposited on the interlayer insulation film, and a wiring metal film made of a material or structure having nonlinear electrical characteristics and deposited on the wiring metal film. It includes an inter-wiring active film and a power wiring layer laminated on the inter-wiring active film, and is characterized in that the wiring metal film that electrically connects the plurality of active elements and the power wiring layer are separated. active wiring element. (2) A plurality of active elements formed on a semiconductor substrate, an interlayer insulating film coated on the semiconductor substrate including the elements, and the interlayer insulating film on the plurality of active elements are opened, and the interlayer insulating film is opened from above the interlayer insulating film. The plurality of wires includes a deposited wiring metal film, an inter-wiring active film deposited on the wiring metal film, and a power supply wiring layer laminated on the inter-wiring active film, which is made of a material or structure having nonlinear electrical characteristics. An active wiring element having at least two electrically different parts separating the wiring metal film and the power supply wiring layer that electrically connect the active elements of the signal line and its return line is placed between the signal line and its return line. An active wiring system using an active wiring element, characterized in that the active wiring element is electrically connected to the signal line and the other side is the return line. (3) A method for manufacturing an active wiring element having a plurality of active elements and a plurality of wiring layers on a semiconductor substrate, which includes a step of forming a plurality of active elements on a semiconductor substrate, and a step of forming a plurality of active elements on the semiconductor substrate including the elements. a step of coating an interlayer insulating film; a step of opening the interlayer insulating film on the plurality of active elements and depositing a wiring metal film over the interlayer insulating film; a step of depositing a multilayer inter-wiring active film on the wiring metal film;
a step of laminating a power wiring layer on the inter-wiring active film; a step of forming a wiring pattern on a resist film coated on the power wiring by a lithography method; 1. A method for manufacturing an active wiring element, comprising the step of transferring a pattern all at once.