JPH01175013A - Power supply control system - Google Patents

Abstract

PURPOSE:To prevent the generation of an error or data destruction by allowing a disk control device to inhibit the off of a power supply until data transfer being processed at present is completed and no influence is exerted upon an access from another system even if a careless power supply off instruction is inputted. CONSTITUTION:When all master equipments have completed access to an I/O device 27, a storage device 29 allows an authorizing means 30 to send a clock. When the clock is received, a transfer means 31 sends a signal for instructing power supply off based upon a switch 25 to a control means 28 at the time of ending the access to the I/O device 27 for the master equipment. The control means 28 allows a data transfer circuit 9 to send a busy signal to the host equipment and then commands a power supply part 24 to turn off the power supply. Thereby, the generation of data destruction or an error in exclusive control information based upon careless power supply off operation of an I/O control device 26 can be prevented.

Description

[Detailed description of the invention] [! eRequired] When an instruction is input to turn off the power to the input/output control device that processes multi-access to the input/output device from multiple host devices, the data transfer process between the host device and the human output device is completed and exclusive: Th1l? ffl! Regarding the power supply control method, which prevents the power from being turned off until the information is guaranteed, even if the power is cut off inadvertently, the data transfer processing currently being processed will be completed and the data transfer from other systems will be completed. In an input/output control device that handles multiple accesses from multiple -F devices to an input/output device, the purpose is to continue power supply until it no longer affects access, and the access to the input/output device for each higher-level device is controlled. storage means for storing the state of the input/output device; permission means for permitting clock transmission when a signal indicating that all host devices have completed access to the input/output device; A transfer means for transferring a disconnection instruction signal, a control means for storing an access state of each host device in the storage means, and for causing the host device to send a busy signal based on the power cutoff instruction signal transferred by the transfer means, the transfer means When a signal instructing to turn off the power is input to the controller, the power to the human output control device is turned off when access to the input/output devices of all host devices is completed.

[Industrial application field]

The present invention relates to an input/output control device that processes multiple accesses from a plurality of host devices to the input/output device, and in particular, when an instruction to turn off the power of the input/output device is input, the communication between the host device and the input/output device is performed. The present invention relates to a power control method that does not turn off the power to an input/output control device until data transfer processing is completed and exclusive control information is guaranteed.

In a computer system, multiple channels access, for example, one disk device via multiple disk controllers to transfer data, but in this case, the disk device transfers data to the area occupied by one channel. Data transfer is performed by exclusively controlling access from the channel.

This disk device is controlled by the disk controller and connected to the channel, so if the power to one disk controller is cut off during data transfer, the exclusive control information of the disk device will be incorrect and the other disk controller will Since it has a negative impact on access from connected channels, powering off the disk control unit must wait until the data transfer process between the disk unit and the channel is completed and the exclusive control information of the disk unit is guaranteed. It is necessary to do so.

[Conventional technology]

FIG. 4 is a block diagram illustrating a conventional technique.

Channel 1 or channel 2 accesses the disk device 6 via the disk controller 4, is coupled with the disk device 6, and performs data transfer. Further, the channel 3 accesses the disk device 6 via the disk controller 5, and connects with the disk device 6 to perform data transfer.

In this case, the disk device 6 records exclusive control information in the exclusive control table 7, and returns busy when another channel accesses the area occupied by the channel performing data transfer.

The disk control device 4 analyzes the command sent by channel 1 or 2, controls the disk device 6, positions the head at the address specified by the command, and updates the exclusive control 1 information in the exclusive control table 7. and controls data transfer between channel 1 or 2 and disk device 6.

Further, the disk control device 5 controls the disk device 6 in the same manner as described above based on the command sent by the channel 3, and causes data transfer between the channel 3 and the disk device 6.

The disk-based '4B devices 4 and 5 are each equipped with a power supply section, and this power supply section has a switch for turning the power on/off. Therefore, if the operator carelessly turns off the switch, the power supply is stopped and the process being executed by the disk control device as described above is immediately stopped.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional disk control device, when the switch provided in the power supply section is turned off, the processing being executed is immediately stopped, so the data being transferred is destroyed and the data is not recorded in the exclusive control table 7 of the disk device 6. The exclusive control information that is being used becomes incorrect, which has a negative impact on accesses from other systems.

For example, if the power to the disk control device 4 is cut off while channel 1 is writing data through the disk control device 4 and occupying an area of the disk device 6, channel 3 of another system will control the disk. When accessing the area occupied by channel 1 of disk device 6 via device 5, the record being accessed by channel 1 remains in the exclusive control table 7 of disk device 6 without being erased. Therefore, there is a problem in that a busy message is returned when accessing channel 3, making it impossible to transfer data.

In view of these problems, the present invention allows even if an inadvertent power-off instruction is input to the power supply section of the disk control device, the data transfer process currently being processed by the disk control device is completed and the disk device 6 The purpose is to continue power supply until the exclusive control information in the exclusive control table 7 is updated and accesses from other systems are no longer affected.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

Via the data transfer circuit 9 of the input/output control device 26, the input/output device 27 is accessed from the higher-level device connected to the terminal, and the input/output device 27 is accessed from the higher-level device connected to the terminal B. 27 is accessed.

The control means 28 causes the storage means 29 to store the access state from the host device, and the storage means notifies the permission means 30 of this access state. When access to the input/output devices 27 of all host devices is completed, the permission means 30 sends the clock input from the terminal C to the transfer means 31.

When the switch 25 is turned on and a signal instructing to turn off the power is input, the transfer means 31 sends out this power-off instruction signal to the control means 28 in synchronization with the clock sent out by the permission means 30. The control means 28 instructs the data transfer circuit 9 to send a busy signal to the host device connected to the terminals A and B, and then sends the input/output control device 26 to the power supply section 24.
to stop the power supply.

[Operation] With the above configuration, the storage means 29 causes the permission means 30 to send out a clock when all the host devices complete access to the input/output device 27. Upon reception of this clock, the transfer means 31 sends a signal to the control means 28 instructing the switch 25 to turn off the power when access to the input/output device 27 of the host device is completed, and the control means 28 sends a signal to the control means 28, which instructs the data transfer circuit 9 In order to instruct the power supply unit 24 to turn off the power after sending a busy signal to the host device, data may be destroyed or errors may occur in exclusive control information due to careless power-off operations on the input/output control unit 26. can be prevented.

〔Example〕

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.
FIG. 3 is a time chart explaining the operation of FIG. 2.

The processor 10 of the disk control device 8 instructs the data transfer circuit 9 to
Access to the disk device 6 from channel 1 shown in the figure is processed, and access to the disk device 6 from channel 2 connected to terminal B is processed.

At this time, the processor 10 sends a bit indicating access from channel 1 to the register 11 in synchronization with the clock as shown in FIG. 3, and as shown in FIG. 3,
A bit indicating access from channel 2 is sent to register 12. When access from channel 1 is completed, register 11 is reset and channel 2
When the access from the register 12 is completed, the register 12 is reset.

Therefore, while the channel 1 is accessing the disk device 6 from the register 11, '1' is sent to the J terminal of the Frisobuf 1'J block 13, the N○゛F circuit 17, and the N○R circuit 19, and the register 12, "l" is sent to the J terminal of the flip-flop 15, the NOT circuit 18, and the NOR circuit 19 while the channel 2 is accessing the disk device 6.

Therefore, from the NOT circuit 17, as shown in FIG.
O'' is input to the terminal of flip-flop 13, NOT
Since "0" is input from the circuit 17 to the terminal of the flip-flop 15 as shown in FIG. 3, the flip-flop 13 sends "1#" to the Q terminal as shown in FIG. As shown in Figure 3 15Q,
Send l" to the Q terminal.

Also, since the NOR circuit 19 sends out "1" while both registers 11 and 12 are reset, the AND circuit 2
0, the NOR circuit 19 sends out the clock input from the open terminal C, which is sending out 11", to the latch circuit 21. Therefore, as shown in FIG. As shown in FIG. 3, the launch circuit 21 detects the turning on of the switch 25 when both the registers 11 and 12 are reset, and sends a power-off interrupt signal to the processor 10 via the OR circuit 22.

The processor 10 sends a busy signal to channels 1 and 2 via the data transfer circuit 9 in response to a processing request after the completion of the current processing, and then sends "1" to the power supply control circuit 23 to instruct it to turn off the power. . Based on this instruction, the power supply control circuit 23 controls the power supply unit 24 to stop the power supply to the disk control device 8 .

The timers 14 and 16 are activated when the flip-flop 13 or 15 is set and "1" is sent from the respective Q terminal, and the flip-flop 13 or 15 is reset and "0" is sent from the respective Q terminal. ” is sent, each is reset. Then, when a predetermined period of time has elapsed after activation, an interrupt signal for power-off is sent to the processor 10 via the OR circuit 22. This is to enable the disk control device 8 to be powered off when the access time to the disk device 6 of channel 1 or 2 exceeds a predetermined time due to a failure.

[Effects of the Invention] As explained above, the present invention prevents data destruction and exclusive control information errors caused by careless power-off operations on input/output control devices, and prevents accesses from other systems from being affected. It can be done.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a block diagram of a circuit showing an embodiment of the present invention, Fig. 3 is a time chart explaining the operation of Fig. 2, and Fig. 4 is a block diagram of the principle of the present invention.
The figure is a block diagram illustrating a conventional technique. In the figure, 1 to 3 are channels, 4, 5.8 are disk controllers,
6 is a disk device, 7 is an exclusive control table, 9 is a data transfer circuit, 10 is a processor, LL12 is a register,
13.15 is a flip-flop, 14 and 16 are timers, 17.18 is a NOT circuit, 19 is a NOR circuit,
20 is an AND circuit, 21 is a latch circuit, 22 is O
R circuit, 23 is a power supply control circuit, 24 is a power supply unit, 25 is a switch, 26 is an input/output control device, 27 is an input/output device, 28 is a control means, 2 is a storage means, 3
0 is a permission means, and 31 is a transfer means. 9/1 +? -knee hand
, to 3

Claims (1)

[Claims] In an input/output control device (26) that processes multiple accesses to the input/output device (27) from a plurality of higher-level devices, the state of access to the input/output device (27) for each higher-level device is stored. a storage means (29) that allows clock transmission when a signal is received from the storage means (29) indicating that all the higher-level devices have completed access to the input/output device (27); Means (3
0), a transfer means (31) that transfers a signal instructing power-off in accordance with the clock sent by the permission means (30), and a transfer means (31) that stores the access state of each host device in the storage means (29), and A control means (28) is provided for causing the higher-level device to send a busy signal based on a power-off instruction signal transferred by the transfer means (31), and when a signal instructing power-off is input to the transfer means (31). , when access to the input/output device (27) of all the host devices is completed, a busy signal is sent to the host device, and then the power of the input/output control device (26) is cut off. Power control method.