JPH01174149A - Monitoring system in time slot replacement device - Google Patents
Monitoring system in time slot replacement deviceInfo
- Publication number
- JPH01174149A JPH01174149A JP33281487A JP33281487A JPH01174149A JP H01174149 A JPH01174149 A JP H01174149A JP 33281487 A JP33281487 A JP 33281487A JP 33281487 A JP33281487 A JP 33281487A JP H01174149 A JPH01174149 A JP H01174149A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- modulo
- time slot
- temporary storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012544 monitoring process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims description 3
- 108010076504 Protein Sorting Signals Proteins 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000012795 verification Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
- 230000011164 ossification Effects 0.000 description 1
Landscapes
- Monitoring And Testing Of Exchanges (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は監視方式に関し、特にタイムスロット入替え装
置における監視方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a monitoring system, and particularly to a monitoring system in a time slot switching device.
従来のタイムスロット入替え装置における監視方式の構
成を第２図（−示す。この図１＝おいて入力信号１５の
あるタイムスロットに着目し。The configuration of a monitoring system in a conventional time slot switching device is shown in FIG.
これを遅延回路１６で一時記憶装置１２の出力側の位相
に合せる。一時記憶装置１２から出力された信号１６と
遅延回路１６から出力された信号を照合回路１４で照合
する。制御回路１１は監視するタイムスロットヲ順次移
し、一時記憶装置１２のすべての領域を監視している。This is matched with the phase of the output side of the temporary storage device 12 by the delay circuit 16. The signal 16 output from the temporary storage device 12 and the signal output from the delay circuit 16 are collated by a collation circuit 14 . The control circuit 11 sequentially shifts the time slots to be monitored and monitors all areas of the temporary storage device 12.
上述した従来の監視方式は１人力信号そのもので一時記
憶装置の監視を行っているため、入力信号が固定的であ
ると有効な監視にはならないという欠点がある。すなわ
ち入力された信号監視しているという問題点がある。例
えば入力信号が１１”固定であると、”１″の書込み。Since the above-mentioned conventional monitoring system monitors the temporary storage device using a single manual signal itself, it has the disadvantage that if the input signal is fixed, effective monitoring cannot be achieved. That is, there is a problem in that the input signal is monitored. For example, if the input signal is fixed at 11", write "1".
読出しの繰返しであり、一時記憶装置が障害で“１″と
なっていても発見できない。Reading is repeated, and even if the temporary storage device becomes "1" due to a failure, it cannot be discovered.
本発明は従来のもののこのような問題点を解決しようと
するもので、入力信号のパターンに依存することなく監
視対象の監視ができる監視方式を提供するものである。The present invention aims to solve these problems with the conventional methods, and provides a monitoring method that can monitor a monitoring target without depending on the pattern of the input signal.
骨化するための２を法とする和演算回路と、符号化、復
号化のための信号列を発生するパターン発生回路と、信
号の選択回路と、該選択回路を制御回路と、一時記憶装
置の入力側と出力側で位相を合せるための遅延回路と、
照合回路とを含んで構成される。A sum calculation circuit modulo 2 for ossification, a pattern generation circuit that generates a signal sequence for encoding and decoding, a signal selection circuit, a control circuit for the selection circuit, and a temporary storage device. a delay circuit to match the phase on the input side and output side of the
and a verification circuit.
次（二本発明について図面を参照して説明する。 Next (2) The present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の回路構成図である。入力さ
れた信号列１〜ｎはパターン発生回路６で発生した信号
列とｍｏｄｕｌｏ ２の和演算回路１で演算が行われる
。選択回路２は制御回路４の指示（二より監視対象とな
っているタイムスロットのみｍｏｄｕｌｏ ２の和演算
回′路１の出力を選ぶ。監視対象となっているタイムス
ロットの信号列とパターン発生回路６の信号列と、制御
回路４の制御情報は遅延回路（ＤＬ）６を通り。FIG. 1 is a circuit diagram of an embodiment of the present invention. The input signal strings 1 to n are calculated by the sum calculation circuit 1 of the signal string generated by the pattern generation circuit 6 and modulo 2. The selection circuit 2 selects the output of the modulo 2 summation circuit 1 only for the time slot to be monitored based on the instructions from the control circuit 4 (2). 6 and the control information of the control circuit 4 pass through a delay circuit (DL) 6.
一時記憶回路５の出力側の位相（二合わせられる。The phase of the output side of the temporary storage circuit 5 (the two are matched).
一時記憶回路５の出力中の監視対象となっているタイム
スロットの信号列はｍｏｄｕｌｏ ２の和演算回路７で
復号化され、照合回路９で照合される。また選択回路８
では復号化された信号を出力する。The signal string of the time slot being monitored that is being output from the temporary storage circuit 5 is decoded by the modulo 2 summation circuit 7 and collated by the collation circuit 9. Also, selection circuit 8
Then output the decoded signal.
本発明はこのよう（−ｍｏｄｕｌｏ ２の和演算回路で
和をとることにより入力信号をランダムパターンに変換
している。In this way, the present invention converts the input signal into a random pattern by calculating the sum using the (-modulo 2) sum calculation circuit.
すなわち、第３図に示す入力信号（ＤＡＴＡ）は０″で
ある確率がα、″１”である確率が（１−α）と仮定し
、ランダム系列信号（ＰＴＮ）は０″である確率が捧、
１１″である確率が捧である。ここで出力信号（ＯＵＴ
）が７０″となる確率は“入力信号＝ランダム系列信号
＝０″。That is, it is assumed that the probability that the input signal (DATA) shown in FIG. Dedication,
The probability that the output signal (OUT
) is 70'' is "input signal = random sequence signal = 0".
或は”入力信号＝ランダム系列信号＝１″となる確率で
与えられる。Alternatively, it is given by the probability that "input signal = random sequence signal = 1".
Ｆ’ｏｕｔ＝Ｏ−Ｐ（ＤＡＴＡ、ＰＴＮ）＝Ｐ（０，０
）＋Ｐ（１，１） Ａ＝α・％＋（，１−α
）・捧＝％
同様に出力が”１″となる確率は°入力信号＝１でラン
ダム系列信号＝０”、或は”入力信号＝０でランダム系
列信号＝１”で与えられる。F'out=O-P(DATA, PTN)=P(0,0
)+P(1,1) A=α・%+(,1−α
)・Dedication=% Similarly, the probability that the output will be "1" is given by "input signal = 1 and random sequence signal = 0", or "input signal = 0 and random sequence signal = 1".
Ｐ□ｕｔ＝ｊ ＝Ｐ（ＤＡＴＡ、ＰＴＮ）＝Ｐ（０，１
）＋Ｐ（１，０）
＝α・捧＋（１−α）・捧＝捧
よって出力は９０”と１′が捧の確率で出力される。す
なわち、ランダム系列信号となる。P□ut=j =P(DATA, PTN)=P(0,1
)+P(1, 0) =α·sequence+(1−α)·sequence=sequence Therefore, the output is 90″ and 1′ with a probability of slender.In other words, it becomes a random sequence signal.
以下今日
〔発明の効果〕
以上説明したように２本発明は監視対象の入力において
、入力信号列：：対し、あるランダム系列信号とｍｏｄ
ｕｌｏ ２の和演算を行う機能を追加することで監視対
象への入力信号をランダムパターンに変換し、監視を行
うことにより入力される信号のパターンに依存すること
なく、監視対象の監視ができる効果がある。Hereinafter, [Effects of the Invention] As explained above, the present invention provides a method for inputting a random sequence signal and a mod.
By adding a function to perform the sum operation of ulo 2, the input signal to the monitoring target is converted into a random pattern, and the monitoring target can be monitored without depending on the pattern of the input signal. There is.
第１図は本発明の一実施例の回路構成図、第２図は従来
のものの回路構成図、第３図は和演算回路の動作説明図
である。
１・・・ｍｏｄｕｌｏ ２の和演算回路、２・・・選択
回路。
３・・・パターン発生回路、４・・・制御回路、５・・
・一時記憶装置、６・・・遅延回路、７・・・ｍｏｄｕ
ｌｏ ２の和演算回路、８・・・選択回路、９・・・照
合回路。
１１・・・制御回路、１２・・・一時記憶装置、１３・
・・遅延回路、１４・・・照合回路。
ｍｌへ
第２図
第３図FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional circuit, and FIG. 3 is an explanatory diagram of the operation of the sum calculation circuit. 1... Modulo 2 sum operation circuit, 2... Selection circuit. 3... Pattern generation circuit, 4... Control circuit, 5...
・Temporary storage device, 6...delay circuit, 7...modu
lo 2 sum calculation circuit, 8...selection circuit, 9...verification circuit. 11... Control circuit, 12... Temporary storage device, 13.
... Delay circuit, 14... Verification circuit. Figure 2 Figure 3 to ml
Claims (1)
ランダムに読出し、またはランダムに書込みシーケンシ
ャルに読出して前記信号のタイムスロットの入替えを行
うタイムスロット入替え装置において、入力信号を符号
化するための２を法とする和演算回路と、符号化された
信号を復号化するための２を法とする和演算回路と、符
号化および復号化のための信号列を発生するパターン発
生回路と、信号を選択する選択回路と、該選択回路を制
御する制御回路と、一時記憶装置の入力側と出力側で位
相を合せるための遅延回路と、照合回路とを含むことを
特徴とする監視方式。1. Method 2 for encoding an input signal in a time slot switching device that writes an input signal into a temporary storage device sequentially and reads it out randomly, or randomly writes and reads it sequentially and switches the time slot of the signal. a summation circuit for decoding the encoded signal, a modulo-2 summation circuit for decoding the encoded signal, a pattern generation circuit for generating a signal sequence for encoding and decoding, and a signal selection circuit. A monitoring system comprising a selection circuit, a control circuit for controlling the selection circuit, a delay circuit for matching phases on the input side and output side of a temporary storage device, and a collation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33281487A JPH01174149A (en) | 1987-12-28 | 1987-12-28 | Monitoring system in time slot replacement device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33281487A JPH01174149A (en) | 1987-12-28 | 1987-12-28 | Monitoring system in time slot replacement device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01174149A true JPH01174149A (en) | 1989-07-10 |
Family
ID=18259100
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33281487A Pending JPH01174149A (en) | 1987-12-28 | 1987-12-28 | Monitoring system in time slot replacement device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01174149A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5692842A (en) * | 1995-04-28 | 1997-12-02 | Seiko Epson Corporation | Guide shaft assembly for a printer |
-
1987
- 1987-12-28 JP JP33281487A patent/JPH01174149A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5692842A (en) * | 1995-04-28 | 1997-12-02 | Seiko Epson Corporation | Guide shaft assembly for a printer |
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