JPH01173918A - C/n detector - Google Patents
C/n detectorInfo
- Publication number
- JPH01173918A JPH01173918A JP62329495A JP32949587A JPH01173918A JP H01173918 A JPH01173918 A JP H01173918A JP 62329495 A JP62329495 A JP 62329495A JP 32949587 A JP32949587 A JP 32949587A JP H01173918 A JPH01173918 A JP H01173918A
- Authority
- JP
- Japan
- Prior art keywords
- phase difference
- phase
- signal
- difference signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims abstract description 11
- 230000010355 oscillation Effects 0.000 claims abstract description 3
- 230000010363 phase shift Effects 0.000 claims abstract 2
- 230000007774 longterm Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
この発明はP S K (phase 5hift k
eying)信号におけるC/N (搬送波電力対雑音
電力比)検出装置に関するものである。[Detailed description of the invention] [Industrial application field] This invention is based on PSK (phase 5hift k
The present invention relates to a C/N (carrier power-to-noise power ratio) detection device in an eyeing) signal.
1従来の技術]
PSK通信などでは、伝送後の信号の品質を保証するた
め、信号のC/Nを常時監視していることが望ましい。1. Prior Art] In PSK communication, etc., it is desirable to constantly monitor the C/N of the signal in order to guarantee the quality of the signal after transmission.
然し、このような目的に対して好適なC/N検出装;ξ
は従来は存在しなかった。However, a C/N detection device suitable for this purpose; ξ
did not previously exist.
C/ N ’z−測定するために従来はスペクトラムア
ナライザ等の11定装置を必要としたり、複雑な回路構
成によりC/N検出装置を実現していた。Conventionally, in order to measure C/N'z-, a constant device such as a spectrum analyzer was required, or a C/N detection device was realized with a complicated circuit configuration.
[発明が解決しようとする問題点コ
簡単な回路構成でC/Nを常時監視できる装置を構成す
ることがこの発明の目的である。[Problems to be Solved by the Invention] An object of the present invention is to construct a device that can constantly monitor the C/N with a simple circuit configuration.
[問題点を解決するための手段]
この発明ではPSK信号の位相差の大きさと、その発生
頻度との関係を測定し、この関係がらC/Nを決定する
こととした。[Means for Solving the Problems] In the present invention, the relationship between the magnitude of the phase difference of the PSK signal and its frequency of occurrence is measured, and the C/N is determined based on this relationship.
[作用]
一定のC/Hに対しては、位相差の大きさと、その発生
確率との関係が定まっているので、各種のC、/ Nの
値に対応する位相差の大きさと、その発生確率との対応
をC/Nテーブルとして記憶し、3(11定結果をこの
C/Nテーブルに対照してC/Nを決定することは容易
である。[Effect] For a given C/H, the relationship between the magnitude of the phase difference and its occurrence probability is determined, so the magnitude of the phase difference and its occurrence corresponding to various C, /N values are It is easy to store the correspondence with probabilities as a C/N table and compare the 3(11 constant results) with this C/N table to determine the C/N.
[実施例]
以下、この発明の実施例を図面を用いて説明する。第1
図はこの発明の一実施例を示すブロック図で、図におい
て(1)はPSK信号、(2)はVCO(電圧制御発振
器)、(3)は位相比較回路、(4アはループフィルタ
、(5)はC/N検出回路、(6)はPSK信号の入力
端子、(7)はC/N出力端子である。[Examples] Examples of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing an embodiment of the present invention. In the figure, (1) is a PSK signal, (2) is a VCO (voltage controlled oscillator), (3) is a phase comparison circuit, (4A is a loop filter, ( 5) is a C/N detection circuit, (6) is a PSK signal input terminal, and (7) is a C/N output terminal.
第2図はC/N検出回路(5)の構成例を示すブロック
図で、り50)は領域識別器、(51)はタイマ、(5
2)、 (53)、 (54)はそれぞれ領域ごとに設
けられるカウンタ、(55)は比較器、(56)はC/
Nテーブル、(57)は位相比較器(3)の出力に接続
される端子であり、(7)は第1図の(7)と同じ端子
を示す。FIG. 2 is a block diagram showing an example of the configuration of the C/N detection circuit (5), in which 50) is an area discriminator, (51) is a timer, and (50) is a region discriminator.
2), (53), and (54) are counters provided for each area, (55) is a comparator, and (56) is a C/
In the N table, (57) is a terminal connected to the output of the phase comparator (3), and (7) indicates the same terminal as (7) in FIG.
第1図のVCO(2)、位相比較回路(3)、ループフ
ィルタ(4)は従来の位相変調信号復調回路の搬送波再
生回路の一種であって、PSK信号(1)の位相とV
CO(2)の位相との位相差である位相差信号を位相比
較回路(3)で検出し、この位相差信号の長時間平均値
に相当する直流電圧をループフィルタ(4)により抽出
し、この直流電圧によってV CO(2)の発振位相を
制御する位相ロックループを構成している。シンボルの
理論は位相比較回路(3)の出力である位相差によって
決定される。The VCO (2), phase comparison circuit (3), and loop filter (4) in FIG.
A phase difference signal that is a phase difference with the phase of CO (2) is detected by a phase comparison circuit (3), and a DC voltage corresponding to a long-term average value of this phase difference signal is extracted by a loop filter (4). This DC voltage constitutes a phase-locked loop that controls the oscillation phase of VCO (2). The symbol theory is determined by the phase difference that is the output of the phase comparison circuit (3).
この位相比較回路(3)の出力をC/N検出回路(5)
に入力してC/Nの検出を行う。The output of this phase comparison circuit (3) is sent to the C/N detection circuit (5).
to detect the C/N.
第3図は2相PSK信号の位相分布を表す図で、信号位
相はOoと180°だけであるが、VCO(2)の位相
誤差およびPSK信号(1)の位相誤差を考慮して、第
3図のAで示す範囲は雑音を含まない信号と判定し、図
中でバッチを施した範囲は雑音を含む信号であると判定
する。この範囲を例えば2領域に分け、雑音の影響の小
さい領域をB、大きい領域をCとする。位相比較回路(
3)はPsIく信号<i>の1シンボルごとに位相差信
号を出力するが、領域識別器(50)は各位相差信号に
ついて位相差の大きさによってA、B、Cの3領域に分
類し、当該位相差信号の属する領域から各位相差(エサ
ごとに一本のパルスを出力する。A、B、Cの各領域か
ら出力されたパルスは、それぞれAカウンタ(52)、
Bカウンタ(53)、 Cカウンタ(54)によって
計数され、所定時間の計数値がそれぞれ記憶される。タ
イマ(51)は各カウンタにおける計数時間(各カウン
タ共に同一時間)を定め、計数が終わると各カウンタの
計数値を記憶領域に移し、各カウンタをリセットして次
の測定を開始するなどの制御を行う。Figure 3 is a diagram showing the phase distribution of the two-phase PSK signal. The range indicated by A in Figure 3 is determined to be a signal that does not contain noise, and the range to which batching is applied in the figure is determined to be a signal that includes noise. For example, this range is divided into two regions, and the region where the influence of noise is small is designated as B, and the region where the influence of noise is large is designated as C. Phase comparison circuit (
3) outputs a phase difference signal for each symbol of the PsI signal <i>, and the region discriminator (50) classifies each phase difference signal into three regions A, B, and C depending on the magnitude of the phase difference. , one pulse is output for each phase difference (for each bait) from the area to which the phase difference signal belongs.
It is counted by a B counter (53) and a C counter (54), and the counted value for a predetermined time is stored, respectively. The timer (51) determines the counting time for each counter (the same time for each counter), and when counting is finished, controls such as moving the counted value of each counter to the storage area, resetting each counter, and starting the next measurement. I do.
比較器(55)は各カウンタの計数値を記憶している記
憶領域からそのデータを読み込み、これを整理して各領
域に対応する発生頻度を正規化し、C/Nテーブル(5
6)のデータに比較するのに適した形のデータにしてお
く。時間の経過と共に各カウンタの計数値は漸次更新さ
れ、これに伴って比較器り55)で整理されるデータは
漸次更新される。このような一連のデータ処理における
領域識別器(50)、タイマ(51)、各カウンタ(5
2)〜(54)、比較器(55)の動作は計算機(図示
せず)によりプログラム制御される。The comparator (55) reads the data from the storage area that stores the count value of each counter, organizes it, normalizes the frequency of occurrence corresponding to each area, and stores the data in the C/N table (55).
The data should be in a format suitable for comparison with the data in 6). The count value of each counter is gradually updated as time passes, and the data sorted by the comparator 55) is accordingly updated gradually. In this series of data processing, the area discriminator (50), timer (51), and each counter (5
The operations of 2) to (54) and the comparator (55) are program-controlled by a computer (not shown).
ところで、雑音は正規分布をしているので、C/Nの値
が与えられると、そのC/Nの信号を位相検波した場合
、ある大きさの位相差の信号の発生確率はその位相差の
大きさから算出することができる。従って、C/Nをパ
ラメータとして、領域A、B、Cの信号の発生確率(−
船釣に言えば位相差信号の表す位相差の大きさとその発
生確率との関係)を決定し、この決定した関係をC/N
テーブル(56)に記憶する。C/Nテーブル(56)
はたとえばROM (読み出し専用メモリ)で構成する
。By the way, noise has a normal distribution, so when a C/N value is given and a signal with that C/N is phase-detected, the probability of generating a signal with a certain amount of phase difference is It can be calculated from the size. Therefore, using C/N as a parameter, the probability of occurrence of signals in areas A, B, and C (-
In terms of boat fishing, the relationship between the size of the phase difference represented by the phase difference signal and its probability of occurrence is determined, and this determined relationship is called C/N.
It is stored in the table (56). C/N table (56)
is composed of, for example, a ROM (read-only memory).
比較器<55)は各カウンタからのデータのデータ処理
を終わると、この処理済みのデータのデータパターン、
すなわちA、B、Cカウンタの計数値をそれぞれ正規化
した数値を、C/Nテーブル(56)のデータのパター
ンと比較し、最も類似度の高いパターンのC/NをPS
K信号(1)のC/Nとして端子(7)から出力する。After completing the data processing of the data from each counter, the comparator <55) calculates the data pattern of the processed data,
That is, the numerical values obtained by normalizing the count values of the A, B, and C counters are compared with the data pattern of the C/N table (56), and the C/N of the pattern with the highest degree of similarity is calculated as PS.
It is output from the terminal (7) as the C/N of the K signal (1).
たとえば、A、B。For example, A, B.
C各カウンタの計数値を正規化した数値のデータパター
ンがax、bx、cxであるとし、C/Nテーブル(5
6)中C/ N = iのテーブルに記憶されているデ
ータパターンがai、bi、ciであるとすれば(ai
−ax)2+ (bi−bx)2+(ci−cx)2の
値を最小にするデータパターンを最も類似度の高いデー
タパターンとする。C/N table (5
6) If the data patterns stored in the table of medium C/N = i are ai, bi, ci, then (ai
The data pattern that minimizes the value of -ax)2+(bi-bx)2+(ci-cx)2 is defined as the data pattern with the highest degree of similarity.
以上の実施例では位相差信号の表す位相差の大きさをA
、B、Cの3領域に分類したが、領域数をさらに増加し
てデータパターンを比較してもよい。但し領域数だけの
カウンタを備え、かつ、領域に対応してC/Nテーブル
を用意しておく必要がある。In the above embodiment, the magnitude of the phase difference represented by the phase difference signal is A
, B, and C. However, the number of regions may be further increased and the data patterns may be compared. However, it is necessary to have counters equal to the number of regions and to prepare C/N tables corresponding to the regions.
更に、上記実施例では2相PSK信号に関して説明した
が、この発明は任意の相数のP S K信号に適用する
ことができる。Furthermore, although the above embodiments have been described with respect to two-phase PSK signals, the present invention can be applied to PSK signals with any number of phases.
[発明の効果]
以上のようにこの発明によれば、簡単な装置を付加する
ことによってPSK信号のC/Nを常時検出するC/N
検出装置を得ることができるという効果がある。[Effects of the Invention] As described above, according to the present invention, by adding a simple device, the C/N of a PSK signal can be constantly detected.
This has the effect that a detection device can be obtained.
第1図はこの発明の一実施例を示すブロック図、第2図
は第1図に示すC/N検出回路の一例を示すブロック図
、第3図は2相PSK信号の位相分布を示す図。
(1)はPSK信号、(2)はVCOlり3)は位相比
較回路、(4)はループフィルタ、(5)はC/N検出
回路、(50)は領域識別器、(52)〜(54)はそ
れぞれカウンタ、(55)は比較器、(56)はC/N
テーブル。
なお、各図中同一符号は同一部分を示すものと第1図
第2図FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the C/N detection circuit shown in FIG. 1, and FIG. 3 is a diagram showing the phase distribution of a two-phase PSK signal. . (1) is a PSK signal, (2) is a VCO1, (3) is a phase comparison circuit, (4) is a loop filter, (5) is a C/N detection circuit, (50) is a region discriminator, (52) to ( 54) is a counter, (55) is a comparator, and (56) is a C/N.
table. In addition, the same symbols in each figure indicate the same parts.
Claims (1)
ースバンド信号を入力し、入力信号のシンボル位相ごと
にVCO(電圧制御発振器)の出力位相と比較し位相差
信号を出力する位相比較回路、 この位相比較回路の出力を入力し、上記位相差信号の長
時間平均値に比例する直流電圧を出力するループフィル
タ、 このループフィルタの出力により上記VCOの発振位相
を制御するフェーズロックループ、上記位相差信号の表
す位相差の大きさに従つて位相差信号を複数の領域に分
類し、各位相差信号ごとに当該位相差信号の属する領域
から1本のパルスを出力する領域識別器、 上記複数の領域の各領域ごとに設けられ、対応する領域
から出力されるパルスを計数する各カウンタ、 この各カウンタの計数時間を制御するタイマ、C/N(
搬送波電力対雑音電力比)をパラメータとし、位相差信
号の表す位相差の大きさとその発生確率との対応を記憶
するC/Nテーブル、所定時間内に上記各カウンタが計
数した各領域のパルス数から、位相差信号の表す位相差
の大きさとその発生頻度との関係を決定し、この決定し
た関係を上記C/Nテーブルにおける位相差の大きさと
その発生確率との対応と比較し、最も良く類似するC/
NテーブルのC/Nの値を上記PSK信号のC/Nの値
として出力する比較器、を備えたC/N検出装置。[Claims] A phase comparison circuit which inputs a baseband signal of a PSK (phase shift keying) signal, compares it with the output phase of a VCO (voltage controlled oscillator) for each symbol phase of the input signal, and outputs a phase difference signal; A loop filter that inputs the output of the comparator circuit and outputs a DC voltage proportional to the long-term average value of the phase difference signal, a phase-locked loop that controls the oscillation phase of the VCO by the output of the loop filter, and the phase difference signal. A region discriminator that classifies the phase difference signal into a plurality of regions according to the magnitude of the phase difference represented by and outputs one pulse from the region to which the phase difference signal belongs for each phase difference signal; Each counter is provided for each region and counts the pulses output from the corresponding region, a timer that controls the counting time of each counter, and a C/N (
A C/N table that stores the correspondence between the magnitude of the phase difference represented by the phase difference signal and the probability of its occurrence, with the carrier wave power to noise power ratio (carrier wave power to noise power ratio) as a parameter, and the number of pulses in each region counted by each of the above counters within a predetermined time. From this, determine the relationship between the magnitude of the phase difference represented by the phase difference signal and its frequency of occurrence, compare this determined relationship with the correspondence between the magnitude of the phase difference and its probability of occurrence in the C/N table above, and find the best one. Similar C/
A C/N detection device comprising: a comparator that outputs a C/N value of the N table as a C/N value of the PSK signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62329495A JPH01173918A (en) | 1987-12-28 | 1987-12-28 | C/n detector |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62329495A JPH01173918A (en) | 1987-12-28 | 1987-12-28 | C/n detector |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01173918A true JPH01173918A (en) | 1989-07-10 |
Family
ID=18222007
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62329495A Pending JPH01173918A (en) | 1987-12-28 | 1987-12-28 | C/n detector |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01173918A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH033456A (en) * | 1989-05-31 | 1991-01-09 | Nec Corp | Circuit for detecting ratio of carrier power to noise power |
WO2000065793A1 (en) * | 1999-04-23 | 2000-11-02 | Mitsubishi Denki Kabushiki Kaisha | Line quality measuring instrument |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5084121A (en) * | 1973-11-26 | 1975-07-07 | ||
JPS5479507A (en) * | 1977-12-07 | 1979-06-25 | Fujitsu Ltd | Supervisoly device for error rate |
-
1987
- 1987-12-28 JP JP62329495A patent/JPH01173918A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5084121A (en) * | 1973-11-26 | 1975-07-07 | ||
JPS5479507A (en) * | 1977-12-07 | 1979-06-25 | Fujitsu Ltd | Supervisoly device for error rate |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH033456A (en) * | 1989-05-31 | 1991-01-09 | Nec Corp | Circuit for detecting ratio of carrier power to noise power |
WO2000065793A1 (en) * | 1999-04-23 | 2000-11-02 | Mitsubishi Denki Kabushiki Kaisha | Line quality measuring instrument |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US3956710A (en) | Phase locked loop lock detector and method | |
CN102045062B (en) | Digital phase-locked loop based on Cordic algorithm | |
US3982190A (en) | Phaselock circuitry with lock indication | |
US4651089A (en) | Frequency counting arrangement | |
CN102291134B (en) | Loop response time measuring device and method used for atomic frequency standard | |
US5159279A (en) | Apparatus and method for detecting out-of-lock condition in a phase lock loop | |
US4105946A (en) | Frequency synthesizer with phase locked loop and counter | |
CN1917372B (en) | Circuit arrangement for detection of a locking condition for a phase locked loop, and a method | |
Hess | Cycle slipping in a first-order phase-locked loop | |
CA1240367A (en) | Apparatus and method for producing a signal-to-noise ratio figure of merit for digitally encoded-data | |
CN108023589A (en) | A kind of transmitting frequency calibration method and circuit | |
Thuestad et al. | Scalar fields in black hole spacetimes | |
JPH01173918A (en) | C/n detector | |
US4949364A (en) | Count error detecting device for count type measuring instruments | |
CN202075347U (en) | Loop oscillation period measure equipment used for atom frequency mark | |
KR0137780B1 (en) | Pulse width discriminating circuit | |
CN107154800A (en) | A kind of detecting system and detection method of phaselocked loop losing lock | |
US3287646A (en) | Signal-to-noise ratio meter | |
CN104539289B (en) | A kind of appraisal procedure and device of atomic frequency standard frequency short-term stability | |
JPH0442061A (en) | Method and apparatus for detecting signal level | |
JP2531269B2 (en) | Sync detection method | |
KR940008154Y1 (en) | Frequency detecting circuit | |
Shuang et al. | Research and implementation of clock recovery method based on software PLL | |
JPH02242168A (en) | Frequency-range detecting apparatus | |
US8138801B1 (en) | Frequency crossing detection using opposing pattern detectors |