JPH01169963A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01169963A JPH01169963A JP62326921A JP32692187A JPH01169963A JP H01169963 A JPH01169963 A JP H01169963A JP 62326921 A JP62326921 A JP 62326921A JP 32692187 A JP32692187 A JP 32692187A JP H01169963 A JPH01169963 A JP H01169963A
- Authority
- JP
- Japan
- Prior art keywords
- recess
- semiconductor
- layer
- guide
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- RNNBHZYEKNHLKT-UHFFFAOYSA-N isopropylmethylpyrazolyl dimethylcarbamate Chemical compound CC(C)N1N=C(C)C=C1OC(=O)N(C)C RNNBHZYEKNHLKT-UHFFFAOYSA-N 0.000 description 1
- NVGOPFQZYCNLDU-UHFFFAOYSA-N norflurazon Chemical compound O=C1C(Cl)=C(NC)C=NN1C1=CC=CC(C(F)(F)F)=C1 NVGOPFQZYCNLDU-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Bipolar Integrated Circuits (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に高耐圧IC
(半導体集積回路)の製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, particularly for high voltage ICs.
(Semiconductor integrated circuit) manufacturing method.
さらには本発明は表面は平坦であるが部分的に1qさの
異なる半導体エピタキシャル層を半導体基板上に有する
半導体装置の製造方法釦関する。Furthermore, the present invention relates to a method for manufacturing a semiconductor device having a semiconductor epitaxial layer on a semiconductor substrate, which has a flat surface but partially differs in height by 1q.
セミウェル・プロセスを用いて高耐圧半導体素子を一部
に有するICを製造する技術については、本出願人に係
る特公昭58−43903公報等に記載されている。A technique for manufacturing an IC that partially includes a high breakdown voltage semiconductor element using a semi-well process is described in Japanese Patent Publication No. 58-43903 filed by the present applicant.
上記IC製造技術によれば、半導体基板の一主表面の一
部に異方性エツチングにより凹部を形成し、この凹部の
内面Kp型不純物を拡散した後にこの上にエピタキシャ
ル成長によるn型半導体層を全面に形成し、この口型半
導体層表面を平坦化エツチングした後に選択拡散技術で
上記凹部によって深くなったエピタキシャル層(ウェル
)表面に高耐圧素子を、凹部の形成されない浅いエピタ
キシャル層表面には高速素子を形成するものである。According to the above IC manufacturing technology, a recess is formed in a part of one main surface of a semiconductor substrate by anisotropic etching, and after diffusing Kp-type impurities inside the recess, an n-type semiconductor layer is formed on the entire surface by epitaxial growth. After flattening and etching the surface of this mouth-shaped semiconductor layer, selective diffusion technology is used to place a high-voltage element on the surface of the epitaxial layer (well) deepened by the recess, and a high-speed element on the surface of the shallow epitaxial layer where no recess is formed. It forms the
上述した半導体装置技術において、エピタキシャル半導
外層表面に選択拡散を行う場合、ウェルの位置を規定す
るために基板表面の一部にガイド用の凹部(段差)を設
けるが、エピタキシャル層表面を平坦化させるときに、
外観的にガイドの凹部(段差)が消失してしまい、その
後のホトレジストマスク位置合せが困難となる。In the semiconductor device technology described above, when selective diffusion is performed on the surface of the epitaxial semiconductor outer layer, a guide recess (step) is provided in a part of the substrate surface to define the position of the well, but the surface of the epitaxial layer is flattened. When you let
The concave portion (step) of the guide disappears in appearance, making subsequent alignment of the photoresist mask difficult.
本発明は上記した問題点を克服するためになされたもの
であり、その目的はセミウェルプロセスを用いるICの
製造において、平坦化後のマスク位置合せを容易とし、
高精度のICを提供することにある。The present invention has been made to overcome the above-mentioned problems, and its purpose is to facilitate mask alignment after planarization in IC manufacturing using a semi-well process.
Our goal is to provide high-precision ICs.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付出面からあきらかになろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the attached figures.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体基板の一主面の一部にセミウェル部の
ための凹部を形成し、この上にエピタキシャル成長によ
って半導体層を全面に形成し、この半導体層表面を平坦
化した後、上記半導体層表面に半導体素子形成のための
選択拡散を行う半導体装置の製造方法において、上記半
導体基板表面に予め上記選択拡散のためのマスク位置決
めガイド用の凹部を形成し、このガイド用凹部に重ねて
前記セミウェル部のための凹部の一部を形成するもので
ある。That is, a recess for a semi-well part is formed in a part of one main surface of a semiconductor substrate, a semiconductor layer is formed on the entire surface by epitaxial growth, and after the surface of this semiconductor layer is planarized, a recess is formed on the surface of the semiconductor layer. In a method for manufacturing a semiconductor device that performs selective diffusion for forming a semiconductor element, a recess for a mask positioning guide for the selective diffusion is formed in advance on the surface of the semiconductor substrate, and a recess for the semi-well portion is overlapped with the guide recess. It forms a part of the recess for.
上記した手段によればマスク合せガイド用凹部にセミウ
ェル用凹部な重ねることでエピタキシャル層平坦化後に
ガイド用凹部が段差として残りその後のマスク合わせが
可能となり、前記目的を達成できる。According to the above-mentioned means, by overlapping the semi-well recess with the mask alignment guide recess, the guide recess remains as a step after the epitaxial layer is flattened and subsequent mask alignment is possible, thereby achieving the above object.
〔実施例1〕
第1図乃至第6図は本発明の一実施例を示すものであっ
て、半導体基板にp −nの二重構造をつくる場合の’
ICプロセスの一部工程断面図である。[Embodiment 1] FIGS. 1 to 6 show an embodiment of the present invention, in which a p-n double structure is formed on a semiconductor substrate.
It is a partial step sectional view of the IC process.
以下工程順に説明する。The steps will be explained below in order.
(1)n型Si基板(サブストレート)1の表面に酸化
膜(5iot ) 2を生成し、これをマスクとしてS
iをエッチし目合せのための深さ15〜20μmのガイ
ド溝(凹部)3をKOHエッチにより形成する(第1図
)。このあとS+*Na膜4をデポジットし、このSi
、N4膜の一部をエッチしてpmエピタキシャル・ウェ
ルのためのパターンを形成する。(1) An oxide film (5iot) 2 is generated on the surface of an n-type Si substrate (substrate) 1, and this is used as a mask to deposit the S
A guide groove (recess) 3 with a depth of 15 to 20 μm for alignment is formed by KOH etching (FIG. 1). After this, an S+*Na film 4 is deposited, and this Si
, etching a portion of the N4 film to form a pattern for the pm epitaxial well.
(2)上記Si、N4膜4をマスクに5iO1をエッチ
し、ついで第2図に示すようKSiをたとえばKOH(
40%)を用いてエッチして深さ20μmの凹部5をつ
くる。この凹部5の一部は前記ガイド溝3と重なるよう
に形成される。(2) Using the Si, N4 film 4 as a mask, 5iO1 is etched, and then KSi is etched with, for example, KOH (
40%) to form a recess 5 with a depth of 20 μm. A portion of this recess 5 is formed so as to overlap with the guide groove 3.
(31S 1sN4.S s O!をエッチ除去し、p
型不純物ドー、y’siを成長させてエピタキシャル層
6を30〜40μmの厚さに形成する(第3図)。(31S 1sN4.S s O! is etched away, p
The epitaxial layer 6 is formed to a thickness of 30 to 40 .mu.m by growing a type impurity dope, y'si (FIG. 3).
(4)Si層6表面をエッチまたは研摩して基板1表面
の高さで平坦化する。このとき第4図に示すようにガイ
ド溝7のパターンは表面に残る。(4) The surface of the Si layer 6 is etched or polished to be flattened to the level of the surface of the substrate 1. At this time, the pattern of the guide grooves 7 remains on the surface as shown in FIG.
(5)全面にn型不純物ドープSi層(8)をエピタキ
シャル成長させ、第5図に示すようにp−n二重エピタ
キシャル構造を得る。(5) An n-type impurity-doped Si layer (8) is epitaxially grown on the entire surface to obtain a pn double epitaxial structure as shown in FIG.
(6)アイソレーションのための9層10、トランジス
タのためのたとえばベースp拡散層を形成する。このあ
と図示されないが、さらに選択拡散を行ってICを構成
する素子を完成する。(6) Form nine layers 10 for isolation, such as a base p-diffusion layer for a transistor. Thereafter, although not shown, selective diffusion is further performed to complete the elements constituting the IC.
上記プロセスにおいて、2段の凹部を形成することで、
エピタキシャル層平坦化後にその表面に段差9が深さ5
μm程度残ることにより、その後の拡散マスクの目合せ
が容易にかつ確実可能となり、さらに目合せの自動化が
可能となった。In the above process, by forming two-stage recesses,
After planarizing the epitaxial layer, there is a step 9 on the surface with a depth of 5.
By leaving about .mu.m remaining, subsequent alignment of the diffusion mask can be easily and reliably made, and further automation of alignment has become possible.
〔実施例2〕
第7図乃至第9図は本発明の他の一実施例を示すもので
あって、セミウェルプロセスを用いたパワーICの一部
工程断面図である。[Embodiment 2] FIGS. 7 to 9 show another embodiment of the present invention, and are partial process sectional views of a power IC using a semi-well process.
(1)前記実施例1の第1図、第2図で示した工程と同
様の工程でp−基板1表面に凹部5と、一部の凹部に重
ねてガイド溝3を形成する。このあと、凹部内表面、及
び基板表面にn+埋込層12のためのn イオン打込み
を行い、またアイソレーシヨンp層13のためのp+イ
オン打込みを行う(第7図)。(1) In a process similar to that shown in FIGS. 1 and 2 of Example 1, a recess 5 and a guide groove 3 are formed on the surface of the p-substrate 1, overlapping some of the recesses. Thereafter, n 2 ions are implanted into the inner surface of the recess and the substrate surface for the n + buried layer 12, and p + ions are implanted for the isolation p layer 13 (FIG. 7).
(2)全面にn型エビタΦシャル層14を30−40μ
mの厚さに成長させる(第8図)。(2) 30-40 μm of n-type Evital layer 14 on the entire surface
The film is grown to a thickness of m (Fig. 8).
(3)エピタキシャル層14の表面平坦化を行い、厚さ
10μm程度となしたエピタキシャル層に選択p型拡散
を行ってアイソレージ1ンp層15を形成する(第8図
)。このようにして、一方でリニア素子のための浅いエ
ピタキシャル層15を有する島領域、他方でパワー素子
のための深いエピタキシャル層16を有する島領域が形
成される。(3) The surface of the epitaxial layer 14 is planarized, and selective p-type diffusion is performed on the epitaxial layer, which has a thickness of about 10 μm, to form an isolation 1-p layer 15 (FIG. 8). In this way, an island region with a shallow epitaxial layer 15 for the linear element on the one hand and a deep epitaxial layer 16 for the power element on the other hand is formed.
上記プロセスにおいても、実施例1と同様に凹部と二重
に形成したガイド溝3によってエピタキシャル層平坦化
後に段差17が残り目合せか、容易に又自動化が可能と
なった。In the above process as well, the step 17 remains after the epitaxial layer is flattened due to the guide groove 3 formed doubly with the recess as in Example 1, and alignment can be easily and automatically performed.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能である。Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof.
本発明はセミウェルプロセスを用いた2重エピタキシャ
ルパワーICに適用する場合にもつとも有効である。The present invention is also effective when applied to a double epitaxial power IC using a semi-well process.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば下記のとおりである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、エピタキシャル層平坦化後の目合せが容易と
なりICの微細化、高精度化が実現できる。That is, alignment after planarizing the epitaxial layer becomes easy, and it is possible to realize miniaturization and high precision of the IC.
第1図乃至第6図は本発明の一実施例を示すもので、セ
ミウェルプロセスを有するICの工程断面図である。
第7図乃至第9図は本発明の他の一実施例を示すICの
工程断面である。
■・・・Si基板、2・・・S + Op膜、3・・・
凹部(ガイド用溝)、4・・・S Is N4膜、5・
・・セミウェル用凹部、6・・・エピタキシャル5i(
p型)、7・・・ガイド用段差、8・・・エピタキシャ
ル5i(n型)、9・・・ガイド用段差、10・・・ア
イソレーン3フ2層、11・・・ベース9層。
第5図
第 6 図
第 7 図
第8図
/4
第9図
手続補正書は式)
%式%
発明の名称
半導体装置の製造方法
″“−をする者
主との関係 特許出願人
称 (510)株式会社 日 立 製 作 所浬人
所 〒100東京都千代田区丸の内−丁目5番1号株
式会社日立製作所内
電話 東京 212−1111 (大代表)、−−゛1
、
名 (6850)弁理士 小 川 勝 男 ・ 1町
l
1令の目付 昭和63年3月29日の対象
図 面1 to 6 show one embodiment of the present invention, and are process sectional views of an IC having a semi-well process. 7 to 9 are process cross-sections of an IC showing another embodiment of the present invention. ■...Si substrate, 2...S + Op film, 3...
Recessed portion (guide groove), 4...S Is N4 film, 5.
... Semi-well recess, 6... Epitaxial 5i (
p type), 7... Guide step, 8... Epitaxial 5i (n type), 9... Guide step, 10... Isolane 3F 2 layers, 11... Base 9 layers. Fig. 5 Fig. 6 Fig. 7 Fig. 8/4 Fig. 9 Procedural amendment form (Formula) % Formula % Name of the invention Relationship with the owner of the method of manufacturing a semiconductor device - Patent applicant name (510) Hitachi, Ltd. Manufactured by Hitachi, Ltd. Address: 5-1 Marunouchi, Chiyoda-ku, Tokyo 100 Hitachi, Ltd. Telephone: Tokyo 212-1111 (main representative), --゛1
, Name (6850) Patent Attorney Katsuo Ogawa / 1 town 1 1st order subject as of March 29, 1986
drawing
Claims (1)
の凹部を形成し、この上にエピタキシャル成長によって
半導体層を全面に形成し、この半導体層表面を平坦化し
た後、上記半導体層表面に半導体素子形成のための選択
拡散を行う半導体装置の製造方法において、半導体基板
表面に予め上記選択拡散のためのマスク位置決めガイド
用の凹部を形成し、このガイド用凹部に前記セミウェル
部のための凹部の一部を重ねて形成することを特徴とす
る半導体装置の製造方法。 2、上記セミウェルは2重エピタキシャル層形成に用い
られる特許請求の範囲第1項に記載の半導体装置の製造
方法。[Claims] 1. After forming a recess for a semi-well part in a part of one main surface of a semiconductor substrate, forming a semiconductor layer on the entire surface by epitaxial growth, and planarizing the surface of this semiconductor layer. In the method for manufacturing a semiconductor device in which selective diffusion is performed for forming a semiconductor element on the surface of the semiconductor layer, a recess for a mask positioning guide for the selective diffusion is formed in advance on the surface of the semiconductor substrate, and the guide recess is filled with the 1. A method of manufacturing a semiconductor device, comprising forming recessed portions for semi-well portions in a partially overlapping manner. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semi-well is used for forming a double epitaxial layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62326921A JPH01169963A (en) | 1987-12-25 | 1987-12-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62326921A JPH01169963A (en) | 1987-12-25 | 1987-12-25 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01169963A true JPH01169963A (en) | 1989-07-05 |
Family
ID=18193245
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62326921A Pending JPH01169963A (en) | 1987-12-25 | 1987-12-25 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01169963A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5417280A (en) * | 1992-08-27 | 1995-05-23 | Mitsubishi Jukogyo Kabushiki Kaisha | Stacked heat exchanger and method of manufacturing the same |
JP2007123781A (en) * | 2005-10-31 | 2007-05-17 | Toshiba Corp | Semiconductor substrate with alignment mark and method for manufacturing alignment mark |
JP2007201499A (en) * | 2007-04-06 | 2007-08-09 | Denso Corp | Semiconductor substrate and its manufacturing method |
JP2007288213A (en) * | 2007-06-25 | 2007-11-01 | Fuji Electric Device Technology Co Ltd | Manufacturing method of semiconductor substrate |
JP2009010006A (en) * | 2007-06-26 | 2009-01-15 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
-
1987
- 1987-12-25 JP JP62326921A patent/JPH01169963A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5417280A (en) * | 1992-08-27 | 1995-05-23 | Mitsubishi Jukogyo Kabushiki Kaisha | Stacked heat exchanger and method of manufacturing the same |
JP2007123781A (en) * | 2005-10-31 | 2007-05-17 | Toshiba Corp | Semiconductor substrate with alignment mark and method for manufacturing alignment mark |
JP2007201499A (en) * | 2007-04-06 | 2007-08-09 | Denso Corp | Semiconductor substrate and its manufacturing method |
JP2007288213A (en) * | 2007-06-25 | 2007-11-01 | Fuji Electric Device Technology Co Ltd | Manufacturing method of semiconductor substrate |
JP2009010006A (en) * | 2007-06-26 | 2009-01-15 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
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