JPH01169963A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable easily the mask alignment after an epitaxial layer is flattened, by forming the epitaxial layer, after a recessed part for a semiwell is formed by stacking it on a recessed part for a mask alignment guide. CONSTITUTION:After a guide trench (recessed part) 3 is formed in a part of the surface of a semiconductor substrate 1, a part of a recessed part 5 for a semiwell part is formed by stacking it on the recessed part 3 for guide. Thereon, a semiconductor layer 6 is formed by epitaxial growth, and the surface is flattened. Then, the flattened epitaxial layer 6 is subjected to selective diffusion to form a semiconductor element. Thus, a recessed part 9 for guide is left as a step-difference after the above epitaxial layer is flattened, so that the mask alignment after flattening is facilitated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, particularly for high voltage ICs.
(Semiconductor integrated circuit) manufacturing method.

Furthermore, the present invention relates to a method for manufacturing a semiconductor device having a semiconductor epitaxial layer on a semiconductor substrate, which has a flat surface but partially differs in height by 1q.

[Conventional technology]

A technique for manufacturing an IC that partially includes a high breakdown voltage semiconductor element using a semi-well process is described in Japanese Patent Publication No. 58-43903 filed by the present applicant.

According to the above IC manufacturing technology, a recess is formed in a part of one main surface of a semiconductor substrate by anisotropic etching, and after diffusing Kp-type impurities inside the recess, an n-type semiconductor layer is formed on the entire surface by epitaxial growth. After flattening and etching the surface of this mouth-shaped semiconductor layer, selective diffusion technology is used to place a high-voltage element on the surface of the epitaxial layer (well) deepened by the recess, and a high-speed element on the surface of the shallow epitaxial layer where no recess is formed. It forms the

[Problem that the invention seeks to solve]

In the semiconductor device technology described above, when selective diffusion is performed on the surface of the epitaxial semiconductor outer layer, a guide recess (step) is provided in a part of the substrate surface to define the position of the well, but the surface of the epitaxial layer is flattened. When you let
The concave portion (step) of the guide disappears in appearance, making subsequent alignment of the photoresist mask difficult.

The present invention has been made to overcome the above-mentioned problems, and its purpose is to facilitate mask alignment after planarization in IC manufacturing using a semi-well process.
Our goal is to provide high-precision ICs.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the attached figures.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a recess for a semi-well part is formed in a part of one main surface of a semiconductor substrate, a semiconductor layer is formed on the entire surface by epitaxial growth, and after the surface of this semiconductor layer is planarized, a recess is formed on the surface of the semiconductor layer. In a method for manufacturing a semiconductor device that performs selective diffusion for forming a semiconductor element, a recess for a mask positioning guide for the selective diffusion is formed in advance on the surface of the semiconductor substrate, and a recess for the semi-well portion is overlapped with the guide recess. It forms a part of the recess for.

[Effect]

According to the above-mentioned means, by overlapping the semi-well recess with the mask alignment guide recess, the guide recess remains as a step after the epitaxial layer is flattened and subsequent mask alignment is possible, thereby achieving the above object.

[Embodiment 1] FIGS. 1 to 6 show an embodiment of the present invention, in which a p-n double structure is formed on a semiconductor substrate.
It is a partial step sectional view of the IC process.

The steps will be explained below in order.

(1) An oxide film (5iot) 2 is generated on the surface of an n-type Si substrate (substrate) 1, and this is used as a mask to deposit the S
A guide groove (recess) 3 with a depth of 15 to 20 μm for alignment is formed by KOH etching (FIG. 1). After this, an S+*Na film 4 is deposited, and this Si
, etching a portion of the N4 film to form a pattern for the pm epitaxial well.

(2) Using the Si, N4 film 4 as a mask, 5iO1 is etched, and then KSi is etched with, for example, KOH (
40%) to form a recess 5 with a depth of 20 μm. A portion of this recess 5 is formed so as to overlap with the guide groove 3.

(31S 1sN4.S s O! is etched away, p
The epitaxial layer 6 is formed to a thickness of 30 to 40 .mu.m by growing a type impurity dope, y'si (FIG. 3).

(4) The surface of the Si layer 6 is etched or polished to be flattened to the level of the surface of the substrate 1. At this time, the pattern of the guide grooves 7 remains on the surface as shown in FIG.

(5) An n-type impurity-doped Si layer (8) is epitaxially grown on the entire surface to obtain a pn double epitaxial structure as shown in FIG.

(6) Form nine layers 10 for isolation, such as a base p-diffusion layer for a transistor. Thereafter, although not shown, selective diffusion is further performed to complete the elements constituting the IC.

In the above process, by forming two-stage recesses,
After planarizing the epitaxial layer, there is a step 9 on the surface with a depth of 5.
By leaving about .mu.m remaining, subsequent alignment of the diffusion mask can be easily and reliably made, and further automation of alignment has become possible.

[Embodiment 2] FIGS. 7 to 9 show another embodiment of the present invention, and are partial process sectional views of a power IC using a semi-well process.

(1) In a process similar to that shown in FIGS. 1 and 2 of Example 1, a recess 5 and a guide groove 3 are formed on the surface of the p-substrate 1, overlapping some of the recesses. Thereafter, n 2 ions are implanted into the inner surface of the recess and the substrate surface for the n + buried layer 12, and p + ions are implanted for the isolation p layer 13 (FIG. 7).

(2) 30-40 μm of n-type Evital layer 14 on the entire surface
The film is grown to a thickness of m (Fig. 8).

(3) The surface of the epitaxial layer 14 is planarized, and selective p-type diffusion is performed on the epitaxial layer, which has a thickness of about 10 μm, to form an isolation 1-p layer 15 (FIG. 8). In this way, an island region with a shallow epitaxial layer 15 for the linear element on the one hand and a deep epitaxial layer 16 for the power element on the other hand is formed.

In the above process as well, the step 17 remains after the epitaxial layer is flattened due to the guide groove 3 formed doubly with the recess as in Example 1, and alignment can be easily and automatically performed.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof.

The present invention is also effective when applied to a double epitaxial power IC using a semi-well process.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, alignment after planarizing the epitaxial layer becomes easy, and it is possible to realize miniaturization and high precision of the IC.

[Brief explanation of the drawing]

1 to 6 show one embodiment of the present invention, and are process sectional views of an IC having a semi-well process. 7 to 9 are process cross-sections of an IC showing another embodiment of the present invention. ■...Si substrate, 2...S + Op film, 3...
Recessed portion (guide groove), 4...S Is N4 film, 5.
... Semi-well recess, 6... Epitaxial 5i (
p type), 7... Guide step, 8... Epitaxial 5i (n type), 9... Guide step, 10... Isolane 3F 2 layers, 11... Base 9 layers. Fig. 5 Fig. 6 Fig. 7 Fig. 8/4 Fig. 9 Procedural amendment form (Formula) % Formula % Name of the invention Relationship with the owner of the method of manufacturing a semiconductor device - Patent applicant name (510) Hitachi, Ltd. Manufactured by Hitachi, Ltd. Address: 5-1 Marunouchi, Chiyoda-ku, Tokyo 100 Hitachi, Ltd. Telephone: Tokyo 212-1111 (main representative), --゛1
, Name (6850) Patent Attorney Katsuo Ogawa / 1 town 1 1st order subject as of March 29, 1986
drawing

Claims (1)

[Claims] 1. After forming a recess for a semi-well part in a part of one main surface of a semiconductor substrate, forming a semiconductor layer on the entire surface by epitaxial growth, and planarizing the surface of this semiconductor layer. In the method for manufacturing a semiconductor device in which selective diffusion is performed for forming a semiconductor element on the surface of the semiconductor layer, a recess for a mask positioning guide for the selective diffusion is formed in advance on the surface of the semiconductor substrate, and the guide recess is filled with the 1. A method of manufacturing a semiconductor device, comprising forming recessed portions for semi-well portions in a partially overlapping manner. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semi-well is used for forming a double epitaxial layer.