JPH01167079U - - Google Patents

Info

Publication number
JPH01167079U
JPH01167079U JP5233489U JP5233489U JPH01167079U JP H01167079 U JPH01167079 U JP H01167079U JP 5233489 U JP5233489 U JP 5233489U JP 5233489 U JP5233489 U JP 5233489U JP H01167079 U JPH01167079 U JP H01167079U
Authority
JP
Japan
Prior art keywords
board
circuit board
wiring
pattern formed
solder bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5233489U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5233489U priority Critical patent/JPH01167079U/ja
Publication of JPH01167079U publication Critical patent/JPH01167079U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Combinations Of Printed Boards (AREA)
JP5233489U 1989-05-02 1989-05-02 Pending JPH01167079U (US20100223739A1-20100909-C00005.png)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5233489U JPH01167079U (US20100223739A1-20100909-C00005.png) 1989-05-02 1989-05-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5233489U JPH01167079U (US20100223739A1-20100909-C00005.png) 1989-05-02 1989-05-02

Publications (1)

Publication Number Publication Date
JPH01167079U true JPH01167079U (US20100223739A1-20100909-C00005.png) 1989-11-22

Family

ID=31278334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5233489U Pending JPH01167079U (US20100223739A1-20100909-C00005.png) 1989-05-02 1989-05-02

Country Status (1)

Country Link
JP (1) JPH01167079U (US20100223739A1-20100909-C00005.png)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56150897A (en) * 1980-04-23 1981-11-21 Fujitsu Ltd Method of manufacturing multilayer printed board

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56150897A (en) * 1980-04-23 1981-11-21 Fujitsu Ltd Method of manufacturing multilayer printed board

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