JPH01164126A - Address decoder - Google Patents

Abstract

PURPOSE:To settle a selecting operation at high speed by providing plural static decoding parts and a logical gate part to form one selecting signal based on the output signals of the respective static decoding parts. CONSTITUTION:A static address decoding part is divided into two parts of a first static decoding part 20a related to the address signal of a low-order half and a second static decoding part 20b related to the address signal of a high-order half, and is provided with a two-input NOR gate NOR1 to form one selecting signal S1 based on the output signals S1a, S1b of the decoding parts 20a, 20b. The number of MOS FETs Q2 connected in series to be on- operated in order to force the output signals S1a, S1b of the static decoding parts 20a, 20b to be at such a low level as an earth level is reduced to half compared with a case that the static decoding part is constituted without being divided. Thus, the selecting operation can be settled at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique for accelerating the selection output determination timing in an address decoder or a static address decoder, and is a technique that is effective when applied to, for example, a NAND type static address decoder. It is related to.

[Prior art]

Address decoders are classified into dynamic and static types, but dynamic address decoders require a preparation period for discharging internal nodes or precharging them due to their logical configuration, so output of a selection signal is required. The confirmation period will be relatively short.

On the other hand, the static address decoder does not require a preparation period for discharge or precharge, and can lengthen the period for determining the output of all selection signals.

An example of a static address decoder is the one shown in FIG.

This static type address decoder 1 decodes an internal address signal supplied from an address buffer 2 that converts external address signals A to An into complementary level internal address signals a, to an, and outputs a selection signal. It has a NAND type circuit configuration that forms S□. Internal address signal a1. The signal line that transmits a, an, an,
According to address decode logic, P channel type MOS
The gate electrodes of FETQ1 and N-channel MOSFETQ2 are commonly coupled. Each P channel type MO
SFETQI has its source electrode connected to the circuit power supply terminal Vdd.
The drain electrode is connected to the selection signal line SL1.
Commonly connected to. Each N-channel type MOSFETQ2
are connected in series between the ground terminal vSS of the circuit and the selection signal line SL1.

A state in which the internal address signals supplied to each pair of MOSFETs QI and Q2 are all set to high level, that is, according to FIG. 3, internal address signals a2. ..., al@
In a state where aJ*..., an are all set to high level, all MO5FETQ2 connected in series are turned on, thereby.

The selection signal line SL is discharged to a low level,
A selection signal S1□ driven to a selection level via a clocked inverter CINV whose input terminals are connected to both sides of this selection signal line SL is applied to the memory cell arrays 3 and 4 on both sides.
is supplied to

An example of a document describing a static address decoder is rHITACHI MICROCOMPUT published by Hitachi, Ltd. in February 1985.
ERDATA BOOK 8-BIT 5INGL
There are E-CHIPJ P279 to P2O3.

[Problem that the invention seeks to solve]

However, in a static address decoder, for example, in a NAND circuit configuration as shown in FIG. 3, series-connected MO5FETQ2 for forcing the selection signal line SL□ to a low level is required for the number of bits of the input address signal. As a result, the operation of discharging the selection signal line SL to a low level is delayed due to the influence of undesired parasitic capacitance of MOSFET Q2, and the predetermined selection signal S□ is quickly determined to the selection level. The present inventors have clarified the problem that it is not possible. This problem becomes more noticeable as the number of bits of the input address signal increases.

Regarding the static type address decoder, the problem that the selection signal line cannot be quickly determined to the selection level applies not only to the above-mentioned NAND type circuit configuration but also to other circuit types such as the NOR type.

SUMMARY OF THE INVENTION An object of the present invention is to provide an address decoder having a static circuit configuration that can quickly determine a selection operation.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, it includes a plurality of static decoding sections that separate and individually decode input address signals, and a logic gate section that forms one selection signal based on the output signal of each static decoding section. The above-mentioned static decoding section includes a bare first switching element and a second switching element that switch in a complementary manner in response to the address signal of each bit, and in each static decoding section, each first switching element is connected in series. the second switch element is connected in parallel to the series end of the first switch element and the other second power supply terminal of the circuit, respectively. .

[For production]

According to the above-mentioned means, when a selection signal is formed via the logic gate section based on the decoding result of the respective static decoding sections for the - set of input address signals, the output of each static decoding section is set to the ground level. The number of series-connected first switch elements that must be turned on to force a predetermined level is reduced compared to the case where the static decoding section is not divided, thereby achieving high-speed determination of the selection operation. It is.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of an address decoder according to the present invention, and FIG. 2 is a schematic block diagram of a memory to which the address decoder is applied.

Although the memory shown in FIG. 2 is not particularly limited, the memory shown in FIG.
only memory).

Although this memory is not particularly limited, one address decoder 10 is shared by left and right memory mats 11 and 12. The external address signals A-An are supplied to the address buffer 13 and converted into internal address signals of complementary levels, and the converted internal address signals are supplied to the address decoder 10.

The memory mats 11 and 12 have a plurality of memory cells (not shown) arranged in a matrix, and selection terminals of the memory cells arranged in the same row are connected to word lines (not shown) for each row, and the selection terminals of the memory cells arranged in the same row are connected to word lines (not shown). The data output terminals of the memory cells are coupled to bit lines for each column.

The above address decoder 10 uses external address signals A□~A
Set one predetermined selection signal to a selection level according to n,
One word line in each of the corresponding memory mats 11 and 12 is driven to the selection level.

The data of the memory cells respectively coupled to the word lines driven to the selection level are read out to the respective bit lines (not shown), and the read memory cell data is output in parallel from the data output circuits 14 and 15 in units of word lines. is output to the outside.

Next, address decoder 10 will be explained in detail.

The address decoder 10 shown in FIG. 1 typically shows a circuit configuration for forming one selection signal S□.

This address decoder 10 receives an n-bit internal address signal a□+ax supplied from the address buffer 13.
~an, an are decoded to form a selection signal, and the static address decoding section includes, but is not particularly limited to, a NAND type first static decoding section 20a for the lower half address signal, and a NAND type static decoding section 20a for the upper half address signal. Second static decoding section 20b of the mold
The output signals S and a of the first and second static decoding sections 20a and 20b forming a pair are divided into two.

It is configured by providing a two-person gate NoR1 that forms one selection signal Si based on S1b. Note that the first and second static decoding sections 20a.

In reality, the number of pairs of 20b and two-person gate N0R1 corresponds to the number of word lines (not shown) included in memory mat 11.12.

The first and second static decoding sections 2°a, 20
b includes signal lines for transmitting internal address signals att a1 to a n pan in the column direction, and these signal lines are connected to P-channel type MOSFEs according to the address decode logic.
The gate electrodes of TQI and N-channel MOSFET Q2 are commonly coupled in address bit units. For example, according to FIG. 1, in the first static decoding section 20a, internal address signals a, ..., ai are sequentially supplied to the gate electrodes of the paired MOSFETs QI and Q2, and In 20b,
Internal address signals aJ+ . . . , an are sequentially supplied to the gate electrodes of the paired MOSFETs QI and Q2 (7).

In the first static decoding section 20a, each P
The channel type MOSFET QI has its source electrode coupled to the power supply terminal Vdd of the circuit, and its drain electrode commonly connected to the output signal line 5Lia. Each N-channel type MOSFET Q2 is connected in series between the ground terminal Vss of the circuit and the output signal line 5L1a.

Similarly, in the second static decoding section 20b,
The source electrodes of the respective P-channel MOSFETs QI are coupled to the power supply terminal Vdd of the circuit, and the drain electrodes are commonly connected to the output signal line SL. Each N-channel type MOSFET Q2 is connected in series between the ground terminal Vss of the circuit and the output signal line 5L1b.

Each M included in the first static decoding section 20a
A state in which all internal address signals supplied to the pair of OSFETs QI and Q2 are set to high level, that is, according to FIG. 1, internal address signal a is set.

..., in a state where all ai are set to high level.

All the MOSFETs Q2 connected in series are turned on and all the MOSFETs QI are turned off, so that the output signal line 5Lia is discharged to the ground level and the output signal S1a is set to the low level.

That is, the first static decoder 20a uses NAND logic to output the lower internal address signals a1e at~ai, a
Decode i.

Similarly, the internal address signals supplied to each pair of MOSFETs QI and Q2 included in the second static decoding section 20b are all set to high level, that is, according to FIG. 1, the internal address signals ajy..., When all the MOSFETs an are set to high level, all the MOSFETs Q2 connected in series are turned on, and all the MOSFETs Q2 connected in series are turned on.
When OSFETQ1 is turned off, output signal line 5L1b is discharged to the ground level, and output signal Sib is determined to be low level. That is, the second static decoder 20b uses NAND logic to determine the upper internal address signal aj, aj=an.

Decode an.

First and second static decoding sections 20a.

Signals Sia and S1b output from 20b are supplied to the two-person gate NOR. When the signals S1a, S, and b supplied thereto are all set to low level, this two-person gate NOR sets the selection signal S1 for selecting a word line (not shown) to a high level as a word line selection level. Drive to. Note that the output timing of the two-person gate NOR is controlled by the clock signal φ after the output signal level is determined.

According to the above embodiment, the following effects can be obtained.

(1) First and second static decoding sections 20a, 2
The number of series-connected MOSFETs Q2 that must be turned on in order to force the 0b output signals S1a, S, and b to a low level such as the ground level is halved compared to the case where the static decoding section is not divided. , the first and second static decoders 2 according to the external address signals A~An supplied to the address buffer 13.
0a.

20b performs address decoding using NAND logic and logic, and based on the decoding results, the two-person gate N
When the OR□ outputs the selection signal S□ at the word line selection level, the time until the output signals S, a, S, b of the respective static decoding sections 20a, 20b are determined, that is, the time required for each signal line SL , a, 5Lib is discharged to below the logic threshold voltage of the two gates N0R1, which is shorter than the configuration shown in FIG. 3 in which the static address decoding section is not divided. It is possible to speed up the line selection operation.

(2) When the address decoder 10 is shared by a pair of left and right memory mats 11 and 12 as in the above embodiment, the gate for regulating the output timing of the selection signal S1 may be configured by one NOR gate N0R1. Therefore, clocked inverters C are installed on both sides as shown in Figure 3.
The number of transistors forming the gate can be reduced compared to the case where INVs are arranged. Therefore, the above effects can be achieved without increasing the chip area occupied by the address decoder.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, in the above embodiment, a configuration in which the static address decoding section is divided into two has been described, but the number of divisions can be determined as appropriate. Further, in the above embodiment, a case has been described in which the address decoder is shared by a pair of left and right memory mats, but the present invention is not limited thereto and can be applied to an address decoder for one memory mat. Further, in the above embodiment, the memory cell data is read out on a word line basis, but a bit line may be selected.

Further, the configuration of the static address decoding section is not limited to the configuration that uses NAND logic as in the above embodiment, but may be changed to a configuration that uses NOR logic.

In that case, the logic gate section that forms the selection signal based on the output signal of each static address decoding section can have a NAND logic configuration.

In the above explanation, the invention made by the present inventor was mainly applied to a ROM built in a microcomputer LSI, which is the field of application that formed the background of the invention, but the present invention is not limited to this, and It can be applied to various semiconductor integrated circuits such as RAM (random access memory, J
). The present invention can be applied to a device having at least a plurality of divided static address decoding sections.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, by comprising a plurality of static decoding sections that separate and individually decode input address signals, and a logic gate section that forms one selection signal based on the output signal of each static decoding section, When a selection signal is formed via a logic gate section based on the decoding result of each static decoding section for an input address signal, an ON operation is performed to force the output of each static decoding section to a predetermined level such as the ground level. The number of series-connected switch elements to be connected can be reduced compared to the case where the static decoding section is not divided, and this has the effect that the selection operation can be determined at high speed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of an address decoder according to the present invention, and FIG. 2 is a schematic block diagram of a memory to which the address decoder is applied. FIG. 3 is a circuit diagram showing an example of a conventional static type address decoder. 10... Address decoder, 11, 12... Memory mat, 13... Address buffer, 20a, 20b
... Static decoding section, NOR, ... 2-person gate, S1a, S1b ... Output signal, Sl...
・Selection signal, Ql...P channel type MOSFET,
Q2...N-channel MOSFET, A, ~An・
・・External address signal, ate a-an, an...
・Internal address signal.

Claims (1)

[Claims] 1. An address decoder that forms a selection signal in accordance with a multi-bit address signal, comprising a plurality of static decoding sections that separate and individually decode input address signals, and each static decoding section. 1. An address decoder comprising: a logic gate section that forms one selection signal based on an output signal. 2. Each of the static decoding units described above has a first switch that operates in a complementary manner in response to the address signal of each bit.
comprising a switch element and a second switch element, in each static decoding section, each first switch element is connected in series and coupled to the first power supply terminal, and the second switch element is connected between the series end of the first switch element and the first switch element. 2. The address decoder according to claim 1, wherein the address decoder is connected in parallel to two power supply terminals. 3. The logic gate is constituted by a NOR gate when the first switch element is an N-channel MOSFET and the second switch element is a P-channel MOSFET. Address decoder according to range 2.