JPH01162014A - Electric field effect transistor logic circuit - Google Patents

Abstract

PURPOSE:To reduce noise, to improve high speed performance and to reduce energy consumption by connecting a variable conductance coupling means, in which conductance goes to be small when an input signal to be supplied to an input terminal goes to be a high level, between the input terminal and the gate of normally-off type FET (EFET) for driver. CONSTITUTION:When an input signal Vin goes to be H, the conductance goes to be small for a normally-on type FET (DFET)14. Thus, a value DELTAV to subtract the source potential of an EFET12 from the source potential of the DFET14 is set so as to be a constant value near a sum between a threshold voltage Vtd of the DFET14 and a turn-on voltage Vf of the parasitic diode of the EFET12. Since the gate of the DFET14 and the source of the EFET12 are directly connected, a voltage between gate and source goes to be DELTAV=0 and the condition of Vtd -Vf is obtained. Accordingly, a direct current coupling is obtained to be strong against the noise and a logical amplitude is caused to be wide. Then, a noise margin is made high, the low energy consumption is obtained and logical operation can be executed at the high speed.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to an electric field transistor constructed using a Schottky junction field effect transistor formed on a compound semiconductor substrate such as GaA3 or a PNN junction field effect transistor. This invention relates to effect transistor logic circuits.

(Prior Art) In recent years, GaA3 integrated circuits having characteristics of ultra-high speed and low power consumption have attracted attention, and DCF L having low power consumption characteristics has been used as a logic circuit for such GaA3 integrated circuits.
(Direct Coupled Field
Various field-effect transistor (hereinafter referred to as FET) logic circuits called ect transistor logic have been proposed.

Conventionally, this type of FET logic circuit was developed in Japanese Patent Application Laid-Open No. 1986-
There was one described in No. 231920. below,
Its configuration will be explained using figures.

FIG. 2 is a circuit diagram showing an example of the configuration of a conventional DCFL type FET logic circuit.

This FET logic circuit is a normally-off type FET for the driver.
ET (hereinafter referred to as EFET) 1 and a normally-on type FET (hereinafter referred to as DFET) 2 for load, and these EFET1 and DFET2 are connected to the power supply potential Vdd.
and the ground GND, and the input signal @V i (input terminal 3 for 1 is connected to the gate of EFETl, and the output is output to the drain of EFETl and the gate and case of DFET2. The output terminals 4 for the signals V., . . . are commonly connected.

This FET logic circuit functions as an inverter to obtain an output signal @voc+t which is an inversion of the input signal V1n. In this type of circuit, EFET1 and DFET2 are configured with Schottky junction FETs or PN junction FETs, and parasitic diodes exist between the gate and source and between the gate and train. Therefore, EFETl
If the voltage (Vin) applied to the gate of the EFET is even slightly higher than the turn-on voltage Vf of the parasitic diode, the EFET l
A forward current of the diode flows from the gate to the source, and there is a clamping effect that the potential of the input signal Vio cannot be higher than this turn-on voltage vf. Here, the turn-on voltage Vf of the parasitic diode is approximately 0.6 to 0.8 V for a Schottky junction FET, and P
Since the N-junction FET can generate voltage at about 1V, the logic amplitude of this FET logic circuit is less than 1V, which is similar to the MO of Si integrated circuit.
It has the disadvantage that it is extremely small compared to those with three circuits, and the noise margin is small. Also, the current due to the clamping effect results in unnecessary power consumption, so
This was an obstacle to low power consumption.

As an example of a circuit that eliminates the drawbacks of the FET logic circuit, there is an FET logic circuit as shown in FIG. 3 described in the above-mentioned document.

This FET logic circuit includes antiparallel diodes 5 and 6 between the gate of EFETl and the input terminal 3 in FIG.
is connected. One diode 5 is connected to the input signal ■
When in becomes a high level (hereinafter referred to as 11H11), the diode 6 is connected with a forward polarity, and the other diode 6 is connected with a polarity opposite to that of the diode 5 in order to discharge the gate charge of the EFET1. There is.

In this FET logic circuit, when the input signal Vio supplied to the input terminal 3 is 'H', the signal Vi.

is divided and applied to diode 5 and EFETI.

Therefore, the turn-on voltage of diode 5 is changed to EFETl
If Vf is the same as that of the parasitic diode, the gate potential of EFETI will be Vi, /2, so the input signal 75 V i
No clamping effect occurs until p exceeds 2Vf (V). As a result, the H'' of the input signal @V i g can be increased, and the logic amplitude can be increased, so the noise margin can also be increased. Also, if the power supply potential Vdd is set to 2Vf (V) or less, no clamping effect will occur. Therefore, it is possible to reduce power consumption.

On the other hand, the input signal Vin changes from 11 HIT to 11 L l
When it changes to #, the gate charge of EFETl is discharged by the diode 6 at a relatively high speed.

Therefore, the circuit shown in FIG. 3 has the advantages of large logic amplitude, high noise margin, low power consumption, and high-speed logic operation.

The above document also describes a FET logic circuit as shown in FIG.

In this FET logic circuit, DFET7 is connected between EFETl and input terminal 3 in FIG.
The gate of T7 is connected to the gate of EFETI.

In this type of circuit, the DFET 7 is always on and is necessarily of a DC result type that is resistant to noise.

Also, when the input signal ■in is 11 HII, the clamp current flowing from the gate of FET1 to the source is DFET
Since the transistor gain coefficient β is limited to a constant value determined by the transistor gain coefficient β of 7, unnecessary power consumption can be reduced. Roughly,
Since "Hll" of the input signal 75 V i 1 is the turn-on voltage Vf of the parasitic diode plus the voltage drop of the DFET 7, the noise margin can be increased.

(Problems to be Solved by the Invention) However, the following problems frequently occur in the FET logic circuits shown in FIGS. 3 and 4.

In the case of the circuit shown in Fig. 3, the input signal ■i is “from HJl”
The DC discharge path of the gate charge of the EFET1 when the voltage is turned on is not limited to the diode 6 which is in the forward direction. The electric charge cannot be lowered, and only the alternating current component is discharged by the capacitive coupling of the diodes 5 and 6. For this reason, E
The impedance of the gate of the FETl is high, which makes it susceptible to noise, and when the gate potential rises due to noise, there is a problem in that since there is no direct current path, charge remains, resulting in malfunction.

In addition, in the case of the circuit shown in Fig. 4, the input signal Vio is ll HI
When I, the gate-source voltage of DFET7 is Ov
, it becomes a constant value higher than the threshold voltage, so
In order to increase the voltage drop of DFET7, its β
needs to be sufficiently smaller than β of DFET2, which is the load in the previous stage. For this reason, if the logic amplitude is increased, the charge/discharge current of the gate of EFET'l cannot be increased.
There was a problem that high-speed performance was impaired.

The present invention provides an FET logic circuit that solves the problems of the prior art, such as being susceptible to noise, impairing high-speed performance, and high power consumption.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides an EF for a driver.
In an FET logic circuit in which an ET and a load DFET are connected, a variable conductance coupling means whose conductance decreases when an input signal supplied to an input terminal becomes 'H' is connected between the input terminal and the driver EFET. It is connected between the gate and the gate.

(Function) According to the present invention, since the FET logic circuit is configured as described above, the conductance coupling means is a DFET or an E
Consisting of FETs, it suppresses clamp current, improves noise resistance through DC coupling, increases logic amplitude to improve noise margin, and improves high-speed performance by shortening the charging and discharging time for the driver EFEH gate. Move as if aiming for. Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a circuit diagram of a FET logic circuit showing a first embodiment of the present invention.

This FET logic circuit is formed on a compound semiconductor substrate such as GaA3, and has an input terminal 1 for input signal Vi0.
0, an output terminal 11 for the output signal @Vout, an EFETl 2 for the driver, a DFET 13 for the load, and a DFET I4 as a variable conductance coupling means, and the EFETl2 and DFET13 are connected in series between the ground GND and the power supply potential Vdd. further connected to its EFE
The drain of Tl2 and the gate and source of DFET13 are commonly connected to output terminal 11.

One of the source and train of DFET14 is connected to the input terminal 10, the other is connected to the gate of EFET12, and the gate of DFET14 is connected to the EFET12.
It is connected to the source of l2 and ground GND. Note that A in FIG. 1 is the gate side node of EFET l2, I
h is charging current, r is discharging current, Vl, V2 are DFET
The gate-source voltage is 14.

In this FET logic circuit, EFETl2 and DFET1
3 constitutes a DCFL inverter. DF
E, T14 has a conductance that becomes small when the input signal vio becomes "'H", and the conductance of E and T14 decreases from its gate potential.
The value ΔV obtained by subtracting the source potential of FETl2 is the DF
Threshold voltage Vtd of E7r14 and EFETl
It is set to a constant value close to the sum of the turn-on voltage Vf of the second parasitic diode (ΔV'=vtd+vf). Here, the gate of DFETI 4 and EFE
Since the source of Tl 2 is directly connected, the gate-source voltage is ΔV=O, and Vtd” V
It becomes f. The threshold voltage Vtd of the DFET 14 is, for example, about -0.6 to -0.8 V when the EFET 12 is a Schottky junction FET.

FIGS. 5(a), (b), and (C) are explanatory diagrams of the operation in FIG. 1, and FIG. 5(a) shows the EF when the input signal io is "H".
Operation characteristic diagram of gate side node A of ETl2, same figure (b)
is an operating characteristic diagram of the input terminal 10 when the input signal vio is "H9e," and (C) is a diagram showing the operating characteristics of the input terminal 10 when the input signal vio is ((LIT).
FIG.

In addition, in FIGS. 5(a) and (C), the curve Ct is the characteristic curve of DFET14, the curve Cd is the forward direction characteristic curve of the parasitic diode in EFETl 2, and FIG. 5(b)
curve (J is the load FET equivalent to the previous stage DFET13
This is the load curve of Also, point M1 in FIG. 5(a) is the operating point of node A, point M2 in FIG. 5(b) is the operating point of input terminal 10, ■ih is the potential of the operating point M2, and Vl4
is the voltage drop of DFETI 4, ViΩ in Figure 5 (C)
is the rising potential of the characteristic curve Ct.

First, the input signal Vi supplied to the input terminal 10 in FIG.
When o changes from ``BI'' to 1 (HIT), input terminal 10
The charging current Ii flows from there to the gate-side node A of the EFET l2, and the potential of that node A rises. At this time, the gate-source voltage of DFET I4 is Vl from the direction of the current.
(That is, if the potential of node A is V, its negative value -
Va), and decreases as the potential (2)8 increases.

Therefore, as shown in FIG. 5 (a>), as the potential Va rises, the charging current Ii flowing through the DFET 13 decreases along the curve Ct.On the other hand, when va≧Vf, the charging current Ii flowing through the DFET 13 decreases along the curve Ct.
The parasitic diode l2 is turned on, and a forward current shown by curve cd in FIG. 5(a) flows toward the ground potential. Therefore, the operating point M1 of the node A when the input signal vio is "'H" is the intersection of the curves Ct and cd, and va#Vf
As a result, EFETl 2 turns on, and the output signal ■
. , t becomes “L′′.

At this time, as mentioned above, the gate-source voltage of the DFET 14 is 1, and becomes -2a key -Vf. Also,
Vtd''; -Vf, the DFET 14 has a gate-source voltage -Va close to the threshold voltage of -VaKtd, and is in an extremely off state, and the conductance is small, so the clamp current is extremely low. On the other hand, the input signal @ V i n 4 (H1
As shown in FIG. 5(b), the potential Vih at 1 o'clock is EF
Since the voltage drop V''14 of the 0FET14 is added to the gate potential vf of ETl2, it can be made to a sufficiently high value even if there is a clamping effect, and the logic amplitude can be increased.

The voltage drop of DFET14, V14, is large.
ET14 conductance and DFET which is the front stage load
It is determined by the ratio to the conductance of l3, but DFET14
The gate-source voltage of DFET13 is near Vtd, whereas the gate-source voltage of DFET13 is OV(nvt
d), and a large voltage drop V14 necessarily occurs on the DFET I4 side even if the transistor gain coefficients β of both transistors are approximately the same. In this way, when the input signal vio becomes H'', D
Since the conductance of FET14 is configured to be small, β of DFET13 is
There is no need to make the EFETl particularly small, and the EFETl
2 gates can be charged.

Next, a case will be explained in which the input signal v11 changes from 'H' to 'B'. When the input signal Vin becomes 'L', a discharge current ■ β flows. Therefore, from the direction of the current, DFE
The gate-source voltage of T14 is a negative value -Viρ of V2 (that is, the potential Viρ at the time of input signal Vi1), and is about -0.1 to -0.2V from the characteristics of the DCFL in the previous stage, which is a threshold value. The voltage can be set to a value sufficiently higher than the voltage Vtd. As a result, as shown in FIG. 5(C), DFET I4 is in the on state in the range where the potential Va of node A is higher than the input signal Vio (=V i, ), and the conductance is large, causing a large discharge current ρ. Therefore, the potential V is rapidly discharged to a sufficiently low potential equal to the potential Viρm when the input signal V is in the dead mode, and the EFET
I2 is almost turned off. Therefore, the output signal V
. , t is mainly determined only by the ratio of the conductance of the load DFET 13 and the conductance of a DFET equivalent to the next-stage DFET 14, and its in Htp is sufficiently high as described above. Also, EFETl
When the gate potential of EFET 2 is in the range of O(V) to vf (V), which is effective as the input voltage of the DCFL circuit, DFET 14 enters the normal 1/ state, and the input terminal 10 and the gate of EFET 12 are DC-coupled. Therefore, its impedance is low, and it is difficult for noise to occur, and even if noise occurs, it quickly recovers to a potential equal to that of the input signal Vio. As described above, the circuit shown in FIG. 1 has DC coupling that is resistant to noise, has a large logic amplitude, has a high noise margin, and is capable of high-speed logic operation with low power consumption.

In the first embodiment, under the condition of -Vtd>Vf, the characteristic curve Ct of the DFET 14 in FIG.
Although the description has been made assuming that the characteristic curve Cd of the parasitic diode of the EFET l2 intersects with the characteristic curve Cd of the parasitic diode of the EFET l2, as long as -Vtd is sufficiently close to vf, it may be less than Vtd and Vf. In this case, the characteristic curves Ct and cd do not intersect, the operating point becomes Va=-vtd, the DFET 14 is completely turned off, the clamp current does not flow, and the "H" of the input signal @ V in is connected to the power supply potential. It is possible to increase the voltage up to Vdd.

The FET logic circuit in Figure 1 is a DCF other than an inverter.
It can also be applied to L circuits, such as NOR circuits (hereinafter referred to as NOR circuits) and NAND circuits (hereinafter referred to as NAND circuits).

FIG. 6 is a circuit diagram of a NOR circuit to which the circuit of FIG. 1 is applied, and elements that are the same as or common to those in FIG. 1 are given the same reference numerals.

This NOR circuit adds an EF for the driver to the circuit in Figure 1.
ETl 2-L D as variable conductance coupling means
FET14-1 and input terminal 10-1 are added, and a DCFL NOR circuit is configured by driver EFET12, 12-1 and load DFET13, and the gate of EFET12 and input signal Vio
DFET I4 is connected between the input terminal 10-1 for EFET l, and the gate of EFET l 2-1 and the input signal V
DFET14-1 between input terminal 10-1 for i, 2
is connected. The gate of DFET14 is EFETl
The source of DFET I4-1 and the gate of DFET I4-1 are EFET
l connected to the sources of 2-1 respectively, and its DFET
14. The threshold voltage Vtd of 14=1 is Vtd”
'f is set.

In the above configuration, the input signals ■, 1. Vin2n is passed through DFET14.14'-1 to EFET12.
12-1 and DFET 13, and then inverted and output signal V. , 1 are output from the output terminal 11.

In this NOR circuit, the circuit configuration from each input terminal 10°10-1 to the gate of the driver EFET l2,12=1 is the same as that of the inverter shown in FIG. A similar effect can be obtained. That is, when the input signal supplied to any input terminal 10.10-1 becomes "Wl", the corresponding DFET 14
The conductance of ゜14-1 becomes small, and the clamp current can be made small. Furthermore, the input signal Vi, 1. Vin2's (H$1) can be set to a sufficiently high potential, so even if the logic amplitude is increased, high speed performance will not be impaired.On the other hand, each EFET12, 12-
Since the corresponding DFET 14.14-1 is in the on state when the gate potential of 'I is in the range of 0 (V) to Vf (V), logic operation that is resistant to noise is possible.

FIG. 7 is a circuit diagram of a NAND circuit to which the circuit of FIG. 1 is applied, and elements that are the same as or common to those in FIG. 1 are given the same reference numerals.

This NAND circuit is added to the circuit shown in Figure 1 with the E
FETl2-1, DFET14-1 as a variable conductance coupling means, and input terminal 10-1 for human input signal Vi, 2 are added, and EFETl2-1 is a driver.
2.12-1 and DFET13, which is used as a load, are connected in series between the ground GND and the power supply potential Vdd, and the DCF
An L NAND circuit is configured. D, which is a variable conductance coupling means 14-1, is connected between the gate of the added driver EFET 12-1 and the input terminal 10-1.
FET14-1 is connected, and the gate of DFET14-1 is EFE'! 12 drains and EFETl 2-
1, roughly connected to the source of EFETI 2-1
The drain of the DFET 13 is commonly connected to the gate and source of the DFET 13 and the output terminal 11 for the output signal ou1.

The threshold voltage Vtd of DFE14.14-1 is
Vtd; set to 'f. In addition, B in Figure 7
is the gate side node of EFETI 2-1, C is its EF
This is the source side node of ETl 2-1.

In the above configuration, the two vio and ■io2 human signals supplied to each input terminal 10.1'O-1 are as follows:
EFETl2.12- through DFET14.14-1
1 and DFET 13 and then inverted,
Output signal V. , t are output from the output terminal 11.

In the circuit of FIG. 7, from the input terminal 10 to the EFET l2
The circuit configuration leading to the inverter shown in FIG. 1 is the same as that of the inverter shown in FIG. The gate can be charged and discharged at high speed, and since it is DC coupled, it is resistant to noise.

Next, the path on the input terminal 10-1 side will be explained.

First, the input signal Vio1 supplied to the input terminal 10 is I
If t HII, EFETl 2 is turned on, and the potential V of the node C of the source of EFETl 2-1 and the gate of DFET 14-1. is about the ground potential. Therefore, under this condition, from the input terminal 10-1 to the EFE
Regarding the route leading to TI 2-1, effects similar to those described above can be obtained. Next, when the input signal Vio1 is the same, EFETl2 is in the off state.Here,
The input signal V in2 supplied to the input terminal 10-1 is “
If it is HI+, even if the potential vb of the node B on the gate side of EFETl 2-1 rises, the potential V of the node C on the source side thereof increases. also rises, and Vo−Vb″=OV, so D
FET14-1 is always on.

On the other hand, since there is no DC path to the ground GND, the input terminal 10-1 is not clamped. Therefore, nodes B, C
The potentials Vb, Vo both rise to a value close to the power supply potential Vdd due to the characteristics of the DCFL.

When the potential of the input signal @Vin2 decreases, the potential of node B
b decreases, and the gate-source voltage Vb-Vo of EFET 12-1 becomes negative, so EFET 12-1 turns off. However, the potential V at node C. Since the DFET 14-1 always remains in the on state while remaining at a high level, the potential Vb of the node B becomes the same potential as the input signal Vi,2. The input signal Vi□2 drops so that Vi,2<V. -V
When f is reached, the parasitic diode existing between the gate and source of DFET 14-1 is turned on, and the potential ■b of node C also begins to fall. At this time V. =Vi,2+Vf, and as mentioned above, since Vb=Vi,2, EFE
The gate-source voltage of Tl 2-1 is Vb-Vo=-
Vf <O, and EFETI 2-1 remains off. Therefore, no direct current flows to the input terminal 10-1, and the output signal V. , t also remains "Hat". Roughly, when the input signal Vio2 drops to about OV,
(2) o': Vf, vb: OV and become stable. here,
Even if the input signal Vio1 becomes 11 Ht#, the EFET
The gate-source voltage Vb-Vo of l2-1 is about Ov, and the output signal V. , t remains 11 HIT.

As described above, even when the input signal Vi, 1 is "the same", there is no problem with logic operation. Also, at this time, no clamping effect occurs and DFET 14-1 remains in the on state. Therefore, the input logic level Regardless of the state of Combined and resistant to noise.

FIG. 8 is a circuit diagram of a FET logic circuit showing a second embodiment of the present invention.

This FET logic circuit constitutes an inverter using an EFET as a variable conductance coupling means, and has an input terminal ■io for an input signal Vio and an output signal V. , the output terminal 21. EFET22 for driver, DFET23 for load, EF which is variable conductance coupling means
It includes an ET 24, a DFET 25, and a diode 26 for constant voltage generation. Ground GND and power supply potential Vdd
An EFET 22 and a DFET 23 are connected in series between the two, and the series circuit constitutes a DCFL inverter circuit. An EFET 24, which is a variable conductance coupling means, is connected between the gate side node D of the EFET 22 and the input terminal 20, and the gate of the EFET 24 is connected to a constant voltage circuit including a DFET 25 and a diode 26. The gate potential of the EFET24 is set to be approximately Vf (v) higher than the driver (7)E FET22(7)'/-i, that is, the EFET24.
Potential difference ΔV between the gate of EFET 4 and the source of EFET 22
=Vt-Vf''=Vf.

Here, Vf is the turn-on voltage of the parasitic diode of EFET 22, and Vt is the threshold voltage of EFET 24.

In the above configuration, when the input signal Vin supplied to the input terminal 20 becomes 44 HO and the potential Vd of the node D on the gate side of the EFET 22 rises to about Vf which causes a clamping effect, the voltage between the gate and source of the EFET 24 increases. Since the voltage V1 becomes V1=Vf-Vd-OV, its conductance becomes extremely small, and the clamp current can be made small.

In addition, the potential vih of input signal Vio can be made high without making the transistor gain coefficient β of EFET 24 particularly small.
You can charge the gate of ET22.

On the other hand, when the input signal vio changes to the potential i, l!
V2 = Vf V Hl '; Vf (D, threshold voltage Viρ of EFET24 is O)
EFET 24 is turned on, and the gate of EFET 22 is discharged to a potential equal to Viρ. Moreover, the gate-source voltage V2 of the EFET 24 at this time is V2=Vf −V ij
<Vf, no new ramp effect by the EFET 24 occurs. As described above, the logic amplitude is large due to DC coupling, and high-speed logic operation is possible.

This second embodiment also has the following advantages.

In the configuration shown in Fig. 8, which uses EFET as the variable conductance coupling means, significant effects can be expected if it is applied to a NOR type circuit consisting mainly of the EFETs required for the driver connected in parallel. can. on the other hand,
The EF necessary for the driver as explained in the first embodiment above, which has variable conductance coupling means using DFET.
It is not easy to construct a NAND type device in which ETs are connected in series. However, there is no particular limit to the threshold voltage of a DFET, and the threshold voltage of a general EFET is set around Ov, so the conventional DC
It has the advantage that it can be implemented without changing the wafer process for FL circuits.

Furthermore, while the power consumption is reduced by the reduction in clamp current compared to that of the DCFL circuit, the power consumption valve of the constant voltage circuit for providing the gate potential of the EFET 24, which is the variable conductance coupling means, increases. However,
In the NOR type circuit, the source potentials of the EFETs that are drivers are all a common reference potential, so the constant voltage circuit also has multiple FEETs that are variable conductance coupling means.
It may be common to T, and even if β of the DFET 25 in the constant voltage circuit is made quite small, there will be no particular problem as a voltage generating means, and the speed of logic operation will not be affected. Therefore, by reducing the clamp current, the overall power consumption can be lower than that of the DCFL circuit.

(Effects of the Invention) As detailed above, according to the present invention, the input signal is
Since the variable conductance coupling means is provided, the conductance becomes small when it reaches 1 level, the logic amplitude and noise margin can be increased, and high-speed logic operation with low power consumption can be obtained.

As one of the variable conductance coupling means, for example, the threshold voltage is about the negative value of the turn-on voltage of the parasitic diode of the driver EFET.
The present invention can be implemented with a configuration in which the gate of the ET is connected to the source of a driver EFET, thereby making it possible to easily configure a NAND circuit in which driver EFETs are connected in series. The variable conductance coupling means can also be realized by a configuration in which an EFET is applied with a potential higher than the source of the driver EFET by about the turn-on voltage Vf (V) of a parasitic diode to its gate. DCF
It becomes possible to realize the circuit of the present invention without changing the conditions of the wafer process. Furthermore, any of the variable conductance coupling means described above also allows the driver E.
The gate voltage of the FET is 0 (
Since the input terminal and the driver EFET are DC-coupled at V) to Vf (V), a circuit resistant to noise can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a FET logic circuit showing a first embodiment of the present invention, FIGS. 2, 3, and 4 are circuit diagrams of conventional FET logic circuits, and FIG. 5(a). (b) and (C) are operation explanatory diagrams of Fig. 1, Fig. 6 is a circuit diagram of a NOR circuit to which Fig. 1 is applied, Fig. 7 is a circuit diagram of a NAND circuit to which Fig. 1 is applied, and Fig. 8 is a circuit diagram of a NAND circuit to which Fig. 1 is applied. The figure is a circuit diagram of a FET logic circuit showing a second embodiment of the present invention. 10.10-1.20...Input terminal, 11゜2
1...Output terminal, 12.12-1.22...
...EFET for driver, 13,23...DFET for load, 14,14-1...DFET for variable conductance coupling means, 24...For variable conductance coupling means EFET, Vi,, Viol,
Vin2-...Input signal, Vout...Output signal.

Claims (1)

[Claims] 1. In a field effect transistor logic circuit in which a normally-off type field effect transistor for a driver and a normally-on type field effect transistor for a load are connected, when an input signal supplied to an input terminal becomes a high level. A field effect transistor logic circuit, characterized in that a variable conductance coupling means having a small conductance is connected between the input terminal and the gate of the normally-off field effect transistor for driver. 2. The variable conductance coupling means is composed of a normally-on field effect transistor, the source and drain of which are connected to the input terminal and the gate of the driver normally-off field effect transistor, and the variable conductance coupling means is composed of a normally-on field effect transistor. The gate of the transistor is connected to the source of the normally-off field effect transistor for the driver, and the threshold voltage of the normally-on field effect transistor for the coupling means is present between the gate and source of the normally-off field effect transistor for the driver. The field effect transistor logic circuit according to claim 1, wherein the field effect transistor logic circuit is set to approximately a negative value of the turn-on voltage of the parasitic diode. 3. The variable conductance coupling means is composed of a normally-off type field effect transistor, the source and drain of which are connected to the input terminal and the gate of the normally-off type field effect transistor for the driver, and the normally-on type field effect transistor for the coupling means is configured. A potential higher than the source potential of the normally-off field-effect transistor for the driver by about the turn-on voltage of a parasitic diode existing between the gate and source of the normally-off-field-effect transistor for the driver is applied to the gate of the normally-off-type field-effect transistor for the driver. A field effect transistor logic circuit according to scope 1.