JPH01162011A - Flat pulse generator - Google Patents

Abstract

PURPOSE:To obtain an output pulse, whose rising and falling are rapid, to be plain in both high and low level sides by executing connection to the source of an FET and a constant current source, which are commonly connected, in a flat pulse generator FPG and removing an output from an interval between one drain of the FET and a drain resistance. CONSTITUTION:The two couples of a low power source coupled FET logic (SCFL) are parallelly connected just as being 'turned inside out'. Namely, in the respective SCFLs, slight field-through, to be generated by an input signal VIN and a reverse phase input signal VIN' are coupled at common connecting points among resistances RD1, RD2, FET1, FET3 and FET4 and between the FET4 and an FET2 in the relation of a reverse phase mutually. Thus, these field-through are canceled each other and accuracy is improved much more. Further, since the two SCFLs are coupled, an output high level VH and a low level VL can be set independently. Accordingly, since an allowing threshold level is wide, a GaAsMESFET can be used. Thus, the pulse at an extremely high speed can be generated.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a flat pulse generator (hereinafter referred to as FPG) which can be used as a high-speed pulse standard signal source and a signal source for calibration of digitizing oscilloscopes, linear LSI test systems, etc. (referred to as ).

[Prior art and its problems]

In recent years, in order to test high-speed D/A converters,
Demand for high-speed, high-precision measurement is increasing. However, there is still no measuring instrument that can satisfactorily measure high-speed settling signals of 8 bits or more at 1 nS or less in this field. In order to improve the accuracy of conventional high-speed measuring instruments under these circumstances, a signal that can be used as a standard is required.

Specifically, a signal that can become this standard is one that rises (or falls) to a certain level in an extremely short time.
, it is a signal that settles extremely quickly after reaching that level.

The rise time of conventional high-speed signal measuring instruments, such as oscilloscopes, is at most 300 pS, and for sampling types, it is several tens of pS, which is sufficiently high. However, in terms of accuracy, oscilloscopes have a resolution of only 6 to 8 bits, and the accuracy at high speeds is not normally specified.

As a high-speed pulse standard, NBS standard FPG I
It is described in EEE IM-32 pp27-32, and as a further development, the patent application filed by the applicant in 1986-20
There are No. 5627 and Japanese Patent Application No. 62-20992. on the other hand,
As a high-speed pulse circuit, for example, IEICE Technical Report 5SD81-
GaAs MES as disclosed in 83
There are logic circuits using FETs, but since these are intended for high-speed operation, no consideration is given to providing them with the above-mentioned waveform necessary for use as a standard signal.

In the conventional FPG disclosed in the above-mentioned documents, a diode clamper is used to shorten the rise time and flatten the waveform after the rise. For this reason, only one of the output levels of the FPG is flat, and therefore only this flat level can be used as a pulse standard. Furthermore, the rise time of the output pulse depends on the input signal to the diode clamper, and if the rise of this input signal becomes fast, leakage to the output side through the capacitance of the clamping diode at the steep rise portion cannot be ignored. becomes.

A method for analyzing a system using the output of this type of FPG as a calibration signal is disclosed in, for example, Japanese Patent Application No. 61-239737 and Japanese Patent Application No. 140614-1982 filed by the applicant. But a big problem arises. That is, although fast Fourier analysis is the most effective and necessary means for analyzing the frequency domain of a signal, it cannot be directly applied to a pulse signal where only one side of the level is flat due to the nature of fast Fourier transform. Therefore, in order to make it suitable for fast Fourier transform, some measures are taken, such as artificially connecting one signal with another signal whose level is flat. However, according to this method, there is a risk that errors may occur due to the joining.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art described above and to provide an FPG that can generate a signal with an extremely good waveform as a reference signal.

[Summary of the invention]

According to an embodiment of the present invention, the above-mentioned document IEICE Technical Report 5
SD81-83 rLow power/source coupled/FE
Logic circuit S CF L (Sou
An FPG configured using rcCoupled PET Logic) is provided. In this FPG, the sources of commonly connected FETs are connected to a constant current source, and an output is taken out between the drain of one FET and a drain resistor. With this configuration, it is possible to obtain an output pulse that has steep rises and falls and is flat on both high and low levels of the output pulse.

In the first embodiment, two sets of 5CFLs are connected in parallel in order to cancel the feedthrough caused by the slight capacitance between the gate and drain of the FET. Also 5CFL
By combining these, the high level and low level output voltages can be set independently.

In the second embodiment, in order to cancel the feedthrough,
A small capacitor is connected across from the input to the drain of the FET.

[Embodiments of the invention]

FIG. 1 shows a first embodiment of the FPG of the present invention.

In the same figure, FETI and FET2 and FET3 and F
Each ET4 constitutes 5 CFLs.

These two sets of 5CFLs are driven by the input signal VIN and the opposite phase input signal *VIN.
) Current flows through the path shown in (). Also, the input signal VI
When N=”L”, reverse phase input signal *VIN=”H・”, the second
Current flows through a path as shown in Figure (b). By setting the currents of the constant current sources 11 and (2) to be different, when the input signal VIN and the negative phase input signal *VIN are inverted, a rectangular wave is generated in the load RL.

By configuring 5CFL, it becomes easy to use GaAs MES FETs for FETI to FET4. In general, GaAs MES FETs have large variations, but 5CFLs have a wide range of dark values, so this is not a problem. GaAs MES FET is used in this circuit configuration.
By using , extremely high speed operation can be achieved due to high carrier mobility and no accumulation of minority carriers. Furthermore, in the 5CFL, since the FET can be operated within the drain current saturation region, the gate-drain capacitance is small, and feedthrough, where an input signal leaks to the output side, is improved compared to the conventional configuration.

In the embodiment shown in FIG. 1, two sets of 5CFLs are
are connected in parallel. In other words, in the configuration shown in Figure 1,
A small amount of feedthrough generated by the input signal VIN and the negative phase human input signal *VIN in each 5CFL is coupled at a common connection point between the resistors RDI, RD2, FETI, FET3, and FET4 and FET2 in a mutually negative phase relationship. This allows these feedthroughs to cancel each other out, further improving accuracy. Furthermore, by combining two 5CFLs, the output high level VH and low level VL can be set independently.

In the circuit shown in Figure 1, the value of the drain resistor RD2 connected to the output terminal within 5CFL is set to the load RL of this FPG.
Let it be equal to As a result, as is clear from the equivalent circuit shown in FIG. 2, the output impedance of the FPG can be matched with the load RL at both high and low output levels, so that no waveform distortion occurs due to reflection. Further, the value of the other drain resistance RDI in 5CFL is set to 1/2 of the drain resistance RD2. In this way, R
Since the combined resistance of D2 and RL and the RDIO value are equal, the load conditions of the two constant current sources 1 and I2 are kept constant as shown in FIG. As a result, constant current source ■1,
Disturbances due to the transient characteristics of I2 can be minimized.

FIG. 3 is a circuit diagram for explaining the basic operation of the second embodiment of the FPG of the present invention. In this circuit, one of the two 5CFLs in FIG. 1 is replaced with minute capacitors C1 and C2 for simplification.

This configuration is effective when the change in the gate-drain capacitance of FETI and FET2 is small. In addition, in Figure 1, the drain resistors RDI and RD2 are placed between the drain and ground, so the output of the FPG is limited to negative potential pulses when using an N-channel FET, and positive potential pulses when using a P-channel FET. However, in the circuit shown in FIG. 3, this restriction is eliminated by providing a drain power supply DD.

In addition, in this configuration, the values of the two drain resistors RDI and RD2 are made equal, and the values of the load RL2 and the pseudo load RLIO are also made equal to each other, so that the load condition of the constant current source 1 remains constant even in direct current. is preferred. Furthermore, the internal impedance of the drain power supply VDD needs to be sufficiently low.

In addition, in the above explanation, GaAsMES is used as the FET.
Although only an example using an FET has been given, it is of course possible to use other high-speed devices such as a HEMT.

Furthermore, the constant current source may be any power source that has an internal impedance high enough to obtain the required output.

In addition, if the reflection from the load can be ignored, for example, if the load is connected to the end of a sufficiently long cable and the reflection does not return within the time period of interest, then the drain of the FET can be used to directly output the current. It can also be connected to a load as a

Furthermore, in the configuration of the present invention, a GaAs MESFET or the like is used in a drain current saturation region, so that the capacitance between the gate and drain is extremely small. As a result, the FPG exhibits sufficiently better characteristics than the conventional FPG even without reducing the feedthrough by canceling out the feedthroughs having mutually opposite phases as shown in FIGS. 1 and 3. Therefore, depending on the required signal accuracy, a "raw" output without cancellation can also be used. In that case, one of the gates of the FET may be fixed at a DC level and only one side may be driven.

〔Effect of the invention〕

As described above, according to the present invention, GaAs MES FETs can be used because the allowable dark value range is wide, and therefore extremely high-speed pulses can be generated. Further, since the output impedance is constant in any state, by matching the transmission impedance to the load, it is possible to prevent the flatness of the output pulse from being adversely affected by the influence of reflected waves. Furthermore, since the influence of input pulse leakage is small, extremely flat output pulses can be generated.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the basic configuration of the first embodiment of the present invention, FIG. 2 is a diagram showing an equivalent circuit for explaining the operation of the circuit in FIG. 1, and FIG. 3 is a diagram for explaining the basic configuration of the first embodiment of the present invention. FIG. 2 is a diagram illustrating the basic operation of the second embodiment. FETI, FET2, FET3, FET4: GaAs
MES FET. RDl, RD2 Nidrain resistance, RL, RL2: Load, RLI: Pseudo load 11, I2: Constant current source, VIN: Input signal, *VIN: Negative phase input signal.

Claims (1)

[Claims] The sources of the pair of FETs are commonly connected to a current source, and the
A flat pulse generator that takes the output from the drain of a T.