JPH01160327A - Recharge control circuit for secondary cell - Google Patents

Abstract

PURPOSE:To protect recharge control characteristic of a cell from being influenced by the characteristics of components, by providing an end-of-recharge signal upon elapse of a predetermined time after a time point when voltage rise of the cell is stopped. CONSTITUTION:A current control circuit 3 receives a quick recharge signal from a recharge sequence logic 5 and starts quick recharge with recharge current being detected through a current detecting resistor 2. An indication circuit 6 lights a LED8 and indicates the state of 'under quick recharge'. A peak voltage memory counter 10 and a D/A converter 9 hold a peak level of cell voltage. A voltage drop detecting circuit 12 detects voltage drop of cell. When voltage drop of cell continues for a predetermined time, the recharge sequence logic 5 provides an end-of-recharge signal to the current control circuit 3 and brings out a trickle recharge mode. At the same time, LED8 flickers to indicate finish of recharge.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a charge control circuit for a charger that rapidly charges a secondary battery.

When a secondary battery such as a nickel-cadmium battery (hereinafter referred to as a 2-cadmium battery) is charged, it has a characteristic that shows a peak voltage vBP at point P and then drops, as shown in the charging voltage characteristics shown in Figure 3. ing. Means for controlling rapid charging by detecting this voltage drop and controlling the charging current is widely and generally used. The present invention provides an optimal configuration circuit when configuring a charger by applying this control method.

2. Description of the Related Art Next, the configuration circuit of a conventional charger will be described with reference to the drawings. FIG. 2 is a configuration circuit diagram of a conventional charger. In Figure 2, 1 is a DC power supply, 2 is a charging current detection resistor, 3 is a current control circuit, 4 is a voltage control circuit, 6 is a display circuit that displays the charging status, 7 is a resistor, and 8 is an LED.
, 12 is a voltage drop detection circuit that detects a voltage drop; 13.
14 is a resistor, 16 is a secondary battery to be charged, 16 is a diode, 17 is an amplifier for impedance conversion, 18 is a diode that constitutes a circuit that stores peak voltage, 19 is a capacitor that stores peak voltage, and 20 is a charging It is a sequence logic circuit. The operation of the circuit of the charger configured as described above will be explained.

First, when the DC power supply unit 1 is driven and the battery 16 is removed, the voltage control circuit 4 operates to control the DC power supply unit to a specified voltage. This voltage is set to a value slightly higher than the maximum value of the charging voltage characteristics of the battery 16.

At this time, the charging sequence logic circuit 20 is in a reset state. In this case, the display circuit 6 outputs "Lo", the display LEDs are turned off, the cathode side of the diode 16 remains "Lo", and the charge in the storage capacitor 19 is discharged through the diode 16.

Next, when the battery 15 is connected, the voltage control circuit 4 stops working. At the same time, the current control circuit operates and rapid charging starts at the current value determined by the current control circuit. At this time, the charging sequence logic circuit 20 is released from the reset state, starts the charging sequence, sends a quick charging signal to the current control circuit 3, sends a quick charging signal to the display circuit, and switches on the discharging diode 16. Cathode side LO”→”
At this time, the x-pressure VC of the storage capacitor 19 is almost zero V. 17 is the FET input or MO3FET.
This impedance conversion circuit uses an input calculation increaser of $1 and outputs the same voltage as the input voltage vc, which is input to the drop voltage detection circuit 12. From the time when the reset state is released, the specific voltage vBs obtained by dividing the voltage VB of the battery 16 by the resistor 13.14 passes through the diode 18 and charges the capacitor 19. Charge is performed until the capacitor voltage vc becomes approximately the battery specific voltage vBs. The battery specific voltage vBs is simultaneously input to the O input of the voltage drop detection circuit 12.

The detected voltage drop set by the voltage drop detection circuit 12 is Δv
s, during rapid charging, -Δvs<vBs-vc
), the voltage drop detection circuit 12 is at Hi” level/
'tit sequence logic, and the charging sequence logic maintains the rapid charging state and outputs a signal to each block. In the charging voltage characteristics shown in FIG. 3, the battery voltage slowly increases until it reaches the voltage ■BP at the peak point P. Therefore, as mentioned above, -Δvs<vBs-v
c is established, and the state of rapid charging is maintained. Eventually, when charging approaches completion and the battery voltage reaches its peak, the battery voltage vBP and battery specific voltage VBSP change, and the capacitor 19
If the voltage is also the peak value ■cP, it will be approximately the same voltage as VBSP. In this case, -Aζ<VBSP-■CP is established, and the voltage drop detection circuit 12 maintains "Hi" and continues rapid charging. As charging progresses further, the battery voltage begins to drop. When the voltage drop eventually reaches the set voltage drop of the voltage drop detection circuit 12, -Δvs>vBS
-vc and Nasi, voltage drop detection circuit 12 (f-i, “Hi”
"→"LO" is output to the charging sequence logic 2o. Here, the charging sequence logic outputs a charging completion signal to the charging control circuit 3 and the display circuit e. The current control circuit 3 The battery is charged with a small current that is safe even if it is permanently applied to the battery.The display circuit 6 also blinks the display LEDs to indicate the completion of charging. The component circuit of the charger shown in FIG. 2 operates.

Problems to be Solved by the Invention However, in the above configuration, since the circuit that stores the peak value of the battery voltage is composed of a capacitor, a diode, and an impedance conversion circuit, the leakage current of the capacitor and the leakage current of the semiconductor will be reduced to the battery voltage. In addition to affecting the detection voltage drop of the J-
FET process, MOS-FET or B i -C
MOS) process is required, increasing costs.

In view of the above-mentioned problems, the present invention provides a battery charger configuration circuit that can be made into a low-cost Mobasic IC, in addition to providing a battery charger configuration circuit using a low-impedance memory circuit.

Means for Solving the Problems In order to achieve this object, the secondary battery charging control circuit of the present invention includes a power supply control circuit composed of a voltage control circuit and a current control circuit, and a charging control circuit composed of a logic circuit. A sequence logic circuit, a circuit that digitally stores the battery voltage or its ratio voltage, a digital-to-analog conversion circuit that converts the digitally stored voltage into an analog voltage, and a circuit that stores the maximum value of the stored voltage and the battery voltage or its ratio voltage. A circuit that compares and detects a specified voltage drop, and a timer circuit that limits the specified time from the point when the battery voltage stops rising.

It consists of a display circuit that displays the charging status.

Operation With the above configuration, the charging control characteristics of the stain battery are not affected by the characteristics of the constituent elements, and in order to apply a low impedance battery voltage storage circuit, it is possible to use a monolithic IC using the general bibolar rough process. It becomes possible.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 1 is a configuration circuit diagram of a charger according to the present invention. In FIG. 1, 6 is a charging sequence logic, 9 is a digital-to-analog conversion circuit, 1o is a peak voltage storage counter, 11 is a counter control, and 21 is a timer.

Other details are the same as in Figure 2.

The operation of the circuit of the charger configured as described above will be explained.

First, when the DC power supply unit 1 is driven and the battery 16 is removed, the voltage control circuit 4 operates to control the DC power supply unit to a specified voltage. This voltage is set to a value slightly higher than the maximum value of the charging voltage characteristics of the battery 15.

At this time, the charging sequence logic 6 is in a reset state. In this case, the display circuit 6 outputs "Lo",
The display LED 8 is off, the peak voltage storage counter is in a clear state, and the timer 21 is also in a reset state. Therefore, the output of the digital/analog converter circuit 9'' outputs a voltage value corresponding to a voltage slightly lower than the lowest value of the reed/battery 0 charge 1 voltage characteristic in the initial state.

Next, when the battery 16 is connected, the voltage control circuit 4 stops working. At the same time, the reset of the charging sequence logic 6 is released, and a signal indicating that rapid charging is in progress is output to each block. Therefore, the current control circuit 3 receives the quick charge signal "Hi" from the charging sequence logic 6, and the current detection resistor 2
While detecting the charging current, the current control circuit 3 controls the DC power supply section with the current value determined by the current control circuit 3 to start rapid charging. Display circuit 6 is charging sequence logic 5
Upon receiving the quick charge signal "Hi", the display LED 8 is turned on to indicate that the quick charge is in progress. When quick charging starts, the clear state of the peak voltage memory counter is also released. At this point, the output voltage ■DA of the digital-analog conversion circuit 9 that converts the data of the peak voltage storage counter 10 from digital to analog is obtained by dividing the voltage VB of the battery 16 by the resistor 13.14 as shown in FIG. The resulting specific voltage is lower than Bs (vDA minus VBS).

Therefore, the counter control circuit 11 outputs a "Hi" level signal. At this time, the timer 21 is not in the reset state.
The peak voltage storage counter 10 performs an up operation. Count up of peak voltage memory counter 10
Corresponding to the operation, the voltage of the output voltage vDA of the digital-to-analog conversion circuit 9 also increases, and when the state of VDA≧vBs is reached, the counter control circuit 11 outputs “Lo” and the peak voltage storage counter 10 And the digital-to-analog conversion circuit 9 maintains its state. at the same time.

The timer 21 starts from the time when the counter control circuit 11 becomes "Lo".While charging is in progress, the battery voltage VB increases with time.
> With vDA, the counter control circuit 11 is turned off again.
Hl n is output, the timer 21 is reset, and the peak voltage storage counter 10 performs an up operation. When vBS≦vDA, the counter control circuit 11 outputs IT L O'' again, and the peak voltage storage counter 10 performs an up operation. While holding the counter 1o and the digital/analog conversion circuit 9 in this state, the timer 21 is started.Therefore, the peak voltage storage counter 10, the digital/analog conversion circuit, and the counter control circuit 11 always keep ■Bs=vDA. Work to make it happen.

The voltage drop detection circuit 12 detects that -ΔVS<VBS during rapid charging, assuming that the detected voltage drop fVs is set by this circuit.
I'm playing "Hi" tj17 to listen to VDA.

Charging progresses and eventually reaches a peak point P in the charging voltage characteristics shown in FIG. At this time, change the battery voltage to ■B
If the ratio voltage of P is VBSP and the output voltage of the digital-to-analog conversion circuit is vDAP, then VBSP=vDAP holds true. Furthermore, as charging continues, the battery voltage begins to drop. At that time, the counter control circuit remains at LO, the peak voltage storage counter 10 and the digital-to-analog conversion circuit 9 maintain the same state and output vDAP. This is the voltage that stores the peak voltage of .At the same time, the timer 21 continues to operate.

When the battery voltage continues to drop and the voltage drop detection circuit 12 reaches -ΔvS>vBS-vDAPK, the voltage drop detection circuit 12 outputs "Lo".

Upon receiving this signal, the charging sequence logic 5 outputs a charging completion signal to each block. The current control circuit 3 receives the charging completion signal "LO" from the charging sequence logic 6 and controls the DC power supply section 1 so that a safe minute current (trickle current) is generated. The charging display circuit 6 receives the charging completion signal from the charging sequence logic 6 and turns on the 1 display LED.
s flashes to indicate charging completion. The charging control circuit of the present invention operates as described above.

The basic operation of the charging control circuit of the present invention has been explained. Next, the protection function of the charging control circuit of the present invention will be explained. Now, it is assumed that in the configuration circuit of the charger shown in FIG. 1, rapid charging is performed and the charging voltage characteristic of the battery reaches a peak point P. At this time, battery voltage ■BP, battery specific voltage VB
, SP, output voltage vDA of digital-to-analog conversion circuit
P=VBSP':,,! : It has become. In the normal case, as described above, the battery voltage eventually drops, and the voltage drop detection circuit 12 detects the end of charging, and charging is completed. However, depending on charging at extremely high temperatures or the quality of the battery, the voltage drop may not reach the voltage drop Δv8''! detected by the voltage drop detection circuit 12, as shown in the charging voltage characteristics shown in FIG. In this case, the rapid charging state will persist and become very dangerous.

Therefore, the counter control circuit 11 changes from "Hi" to "L".
This problem is solved by starting the timer 21 from the point at which the counter control circuit 1
1 changes from "Hi" to "Lo", the battery voltage rises again and the battery voltage changes from "LO" to "Ht". At this time, the timer 21
will be reset. This time is very short compared to the time limit TF of the timer 21, and therefore the timer 21 never times up.

After the peak point of the battery voltage, the counter control circuit becomes “L”.
The timer 21 continues to operate in order to hold O''. After that, as shown in FIG. This signal is sent, and the component circuits of this charger complete charging.

Effects of the Invention As described above, the present invention includes a power supply control circuit composed of a voltage control circuit and a current control circuit, a charging sequence logic circuit composed of a logic circuit, a circuit for digitally storing battery voltage or its ratio voltage, and the like. The digital-to-analog conversion circuit that converts the digitally stored voltage into analog voltage, the circuit that compares the maximum value of the stored voltage with the battery voltage or its ratio voltage to detect a specified voltage drop, and the increase in battery voltage are eliminated. By composing a timer circuit that limits the specified time from the moment the battery is charged, and a display circuit that displays the charging status, the charging control characteristics of the Shimi battery are not affected by the characteristics of the component elements, ensuring good charging. A secondary battery charging control circuit having control characteristics can be constructed, and its utilization effects are significant.

[Brief Description of the Drawings] Figure 1 is a circuit diagram showing an embodiment of the present invention, Figure 2 is a circuit diagram showing a conventional example, Figure 3 is a battery charging voltage characteristic diagram, and Figure 4 is a diagram showing timer control. The characteristic diagram shown in Figure 6 is the characteristic diagram at the time of overvoltage. Name of agent: Patent attorney Toshio Nakao and 1 other person, 2 wards〉MiQ) ro: ku〉ゑ子〉(; 6to4 kuU)

Claims (3)

[Claims] (1) A power supply control circuit consisting of a voltage control circuit, a current control circuit, a charging sequence logic circuit consisting of a logic circuit, a circuit for digitally storing the battery voltage or its ratio voltage, and a circuit for digitally storing the battery voltage or its ratio voltage. A digital-to-analog conversion circuit that converts the stored voltage into an analog voltage, a circuit that compares the maximum value of the stored voltage with the battery voltage or its ratio voltage to detect a specified voltage drop, and A secondary battery charging control circuit consisting of a timer circuit that limits the specified time and a display circuit that displays the charging status. (2) A secondary battery charging control circuit according to claim 1, which has means for terminating charging when the circuit for digitally storing battery voltage or its specific voltage overflows. (3) A secondary battery charging control circuit according to claim 1 or 2, wherein the circuit is constructed of a monolithic IC.