JPH01160059A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent erroneous write, and to shorten the erasing time by providing a high-voltage setting means through which the potential of a bit line at the time of erasing is made higher than that of a word line and a bit line at the time of write. CONSTITUTION:Two charging pumps are installed, and output voltage from the charging pump 32 generating high voltage Vpp (BL, E) applied to bit lines is set at a value higher than output voltage from the charging pump 11 generating high voltage Vpp (WL, P) applied to word lines. High voltage Vpp (WL, P) generated by the charging pump 11 is transmitted over the word line selected by a high-voltage switch 14. A signal E rises on erasing, and output voltage from the charging pump 12 is transmitted over the bit lines through an I/O line 20. A signal P rises on write, and voltage applied to a Vpp terminal (an external high-voltage input terminal) T1 is transmitted over the bit lines.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to electrically erasable/programmable non-volatile semiconductor memory devices (EEPROMs), and particularly to bulk erase type EEPROMs.
This is related to EFROM.

[Conventional technology]

Figure 3 is a 1987 I.N.S.C. Technical Paper Digest, pages 76-77 (19871
SSCCDIGEST OF TECHNICAL P
APER3,9p.

76-77)" is a circuit diagram showing a simple equivalent circuit of a conventional EEFROM having a memory cell consisting of one memory transistor.

In FIG. 3, Q1 to Q4 are memory transistors, and each of the memory transistors Q1 to Q4 has a drain on the bit lines BLI, BLI, BL2, BL2, and a gate on the word lines WLI, WL2 . WLl, WL2, the sources are source lines SLI, SL2 . Connected to SLI and SL2.

Figure 4 shows memory transistors Q1 to Q4 shown in Figure 3.
FIG. As shown in the figure, a drain diffusion region 2 and a source diffusion region 3 are formed at an interval on the surface of a semiconductor substrate 1. This semiconductor substrate 1 is covered with a thin oxide film 4 of about 200 layers, and a floating gate 5 is provided on a part of this oxide film 4 so as to be located above the end of the drain diffusion region 2. The gate 5 and the oxide film 4 are covered with an oxide film 6, and the oxide film 6 is
is covered with control gate 7. Therefore, the control gate 7 has a low step structure in the portion where the floating gate 5 is not present, and the floating gate 5 is surrounded by the oxide films 4 and 6 and is in an electrically floating state. Further, a drain electrode 8, a control gate electrode 9, and a source electrode 10 are connected to the drain diffusion region 2, the control gate 7, and the source diffusion region 3, respectively.

In the above configuration, a write operation will be explained.

First, an erase cycle is performed in which "1" is written to all memory transistors. In the erase cycle, all bit lines (BLI, BL2 in FIG. 3) are set to high voltage Vpp level, and all word lines (WLl, WL2 in FIG. 3) are set to rLJ level (
OV), a high electric field is generated between the floating gate 5 and the drain diffusion region 2 of the memory transistors (Q1 to Q4 in FIG. 3) (see FIG. 4).

Therefore, the electrons accumulated in the floating gate 5 are drawn out to the drain diffusion region 2 through the thin oxide film 4 by a tunneling phenomenon. As a result, the floating gate 5 becomes deficient in electrons, and the dark value voltage of the memory transistors Q1 to Q4 as seen from the control gate 7 becomes low (becomes a negative level). This state can be logically defined as ``
1" is stored.

When the erase cycle ends, the program moves to the write cycle. Here, a write cycle when memory transistor Q3 is selected will be described. This write cycle is E
The program operation is performed in the same manner as in EPROM, and the selected bit line BL2 is set to the high voltage VPP level.
The unselected bit line BLI is set to OV, the selected word line WLI is set to the high voltage Vpp level, and the unselected word line WL is set to OV.
Set 2 to 0■. Therefore, high voltage VPP is applied to drain diffusion region 2 and control gate 7 (see FIG. 4) of selected memory transistor Q3. At this time, hot electrons are generated near the drain diffusion region 2 of the selected memory transistor Q3, and these hot electrons are accelerated by the high voltage VPP applied to the control gate 7 and the floating gate 5
injected into.

As a result, the floating gate 5 becomes in a state of accumulating electrons, so that the dark value voltage of the memory transistor as seen from the control gate 7 becomes high (becomes a positive level). The memory cells selected in this way are logically
0" is written.

Source lines SLI and SL2 are kept floating during erasing, and are kept at ground potential during writing.

[Problem that the invention seeks to solve]

Since the conventional batch erasing type EEPROM is configured as described above, a high voltage Vp is applied to the control gate even in the memory cell, for example, Ql, to which it is not desired to write.
Since p is applied and the drain is grounded, there is a drawback that electrons are injected into the floating gate 5 due to the tunneling phenomenon. For this reason, the conventional batch erasing type E
In an EFROM, it is necessary to make the injection efficiency of electrons into the floating gate by avalanche sufficiently higher than the injection efficiency by tunneling. The thickness of the thin oxide film 4 is 200 mm compared to the conventional floating gate type EEPR.
This is the reason why the tunnel oxide film of OM is made thicker than the tunnel oxide film (approximately 100 people).

However, because the injection efficiency was lowered due to the tunneling phenomenon, the time required for erasing became several tens to thousands of times longer than the writing time.

The present invention has been made in view of these points, and its purpose is to provide a nonvolatile semiconductor memory device in which the time required for erasing is as short as the time required for writing.

[Means for solving problems]

In order to achieve such an object, the nonvolatile semiconductor memory device according to the present invention makes the voltage of the high voltage pulse applied to the bit line during erasing lower than the voltage of the high voltage pulse applied to the word line during writing. A high pressure setting means is provided to increase the pressure.

[Effect]

In the nonvolatile semiconductor memory device according to the present invention, there is no erroneous writing and the erasing time is shortened.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of a nonvolatile semiconductor memory device according to the present invention. In the same figure, 11.12
13 is a Y decoder, 14 is a high voltage switch, 15 is a row decoder, 16 is a charge pump provided on the same chip.
-19 are transistors, 20 is an I10 line, and charge pumps 11 and 12, high voltage switch 14, and transistors 18 and 19 constitute high voltage setting means. In this figure, the same or equivalent parts as in FIG. 3 are given the same reference numerals.

In FIG. 1, two charge pumps are provided, and the output voltage of a charge pump 12 that generates a high voltage Vpp (BL, E) to be applied to a bit line is a high voltage Vpp (W L , P ) is set higher than the output voltage of the charge pump 11 that generates the voltage. High voltage Vpp (WL, P) generated by charge pump 11 is transmitted to a selected word line by high voltage switch 14. During erasing, signal E rises and charge pump 1
The output voltage of 2 is transmitted to the bit line via the I10 line 20. During writing, the signal P rises and transmits the voltage applied to the Vpp terminal T1 to the bit line.

2(a) and 2(b) are configuration diagrams showing an example of a memory transistor constituting a nonvolatile semiconductor memory device according to the present invention. In the structure shown in FIG. is formed thinly throughout, with a film thickness of 60 to 120 layers.In the structure shown in Figure 2(b),
The oxide film in the overlapping portion of the floating gate 5 and the drain diffusion region 2 is formed thin.

Next, the operation when memory transistor Q3 is selected will be explained using FIG. 1. Bit line BL during erasing
1. The voltage VPP of the high voltage pulse applied to BL2 (B
L, E) are set high enough to allow current to flow due to tunneling. During writing, the high voltage pulse voltage VPIJ (BL, P) applied to the bit line BL2 corresponding to the selected memory transistor Q3 and the high voltage pulse voltage VPP (B L, P ) applied to the word line WLI corresponding to the memory transistor Q3. WL, P) are set to such an extent that the tunneling phenomenon in the unselected memory transistor Q1 can be ignored. For example, 'Jpp (BL, E)
If the thickness of the oxide film under the floating gate 5 is set so that erasing can be performed in a few milliseconds for two hours at about 20 V, VPP (BL, P), VPP (WL,
If P) is set to 15 V or less, writing due to tunnel current can be almost ignored. Currently, the programming voltage of EEPROM is 10 to 12.5V, so VPP(BL,P)
, VPP (WL, P) < 15V, sufficient writing is performed.

In FIG. 1, the above VpP (BL, E), VPP (W
L, P) are configured to be generated by the charge pump 12.11, and at the time of writing, the Vpp terminal (
The high voltage applied to the external high voltage input terminal (external high voltage input terminal) Tl is applied to the bit line. Note that a single charge pump may be configured to change the high voltage generated during erasing and writing.

〔Effect of the invention〕

As explained above, in the nonvolatile semiconductor memory device according to the present invention, the potential of the bit line during erasing is changed from the potential of the bit line during erasing to the potential of the word line during writing.
By providing a high voltage setting means that raises the potential higher than the bit line potential, writing due to tunnel current in unselected memory transistors can be ignored, which has the effect of eliminating erroneous writing and shortening the erasing time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a non-volatile semiconductor memory device according to the present invention, FIG. 2 is a block diagram showing an example of a memory transistor constituting the device of FIG. 1, and FIG. FIG. 4 is a block diagram showing a memory transistor constituting the device of FIG. 3. Q1-Q4...Memory transistor, BLI, BL2
...Bit line, WLI, WL2...Word line, SL
l, SL2...source line, 1112...charge pump, 13...Y decoder, 14...high voltage switch, 15...row decoder, 16-19...transistor, 20...T10 line, T1...Vpp terminal.

Claims (3)

[Claims] (1) In a nonvolatile semiconductor memory device in which an array of memory transistors each having a floating gate and a drain connected to a bit line and a gate connected to a word line are arranged, the voltage of the high voltage pulse applied to the bit line during erasing is 1. A nonvolatile semiconductor memory device comprising a high voltage setting means for setting a voltage higher than a voltage of a high voltage pulse applied to a word line and a bit line during writing. (2) A patent characterized in that the memory transistor has an oxide film between the floating gate and the substrate with a thickness of 60 to 150 Å, a control gate extending toward the source side, and a region without the floating gate below. A nonvolatile semiconductor memory device according to claim 1. (3) The memory transistor has a region where the oxide film is thinner than other parts in the overlapping part of the floating gate and drain, and has a control gate extending to the source side and a region without the floating gate below. A nonvolatile semiconductor memory device according to claim 1, characterized in that: