JPH01158570A - Hardware modelling system and method of simulation of electronic circuit using it - Google Patents

Abstract

PURPOSE: To simulate part of the electric circuit by using an actual hardware element such as an integrated circuit, a printed circuit and a sub system of the electric circuit for simulation. CONSTITUTION: The system is provided with a hardware modelling circuit means 10 and it is interfaced with plural electric circuit simulation work stations 14 with a computer network integrated circuit means 12. The hardware modelling circuit means 10 contains plural integrated circuit elements 16 and a printed circuit or a circuit sub system 18. When a work station 14 designs a circuit, the hardware modelling elements 16, 18 are accessed and used for simulating elements. Then the work station 14 as required has an access to the actual physical hardware modelling elements 16, 18. Thus the improved hardware modelling element circuit system is obtained to use the hardware modelling elements 16, 18 in the simulation of the electric circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION The present invention simulates portions of electrical circuits by using in simulation real hardware elements such as integrated circuits, printed circuits, and subsystems of electrical circuits. METHODS AND APPARATUS.

Traditionally, software systems have been developed to model, or simulate, the performance of circuit elements. Such software models facilitate the design and engineering of electrical circuits. Although these devices have proven to be powerful tools in assisting circuit designers, they also have drawbacks, particularly notable in software models of LSI and VLSI such as microprocessors. These LSI and VLSI require time to create a software model and are expensive.

In this regard, the time required to create such a model is long, making it difficult to create models quickly as new circuits are designed.

Also, complex software models are difficult to test and have low reliability. Additionally, professional circuit designers are typically kept in the dark about modeling unless their employer provides them with sufficient information to create a software model. Employers of circuit designers often neglect to provide this information.

In an attempt specifically aimed at these issues, DaisyS
ys tems and Valid Logic Sys
tems has rPMX J and rReal C, respectively.
They have developed a device called hip J. In each of these devices, the circuit designer uses a workstation containing software models of several circuit elements.

Each workstation is also connected to its own serving hardware element modeling unit.

These hardware element modeling units contain actual integrated circuit elements for use in modeling. and when a user at a workstation is evaluating a circuit design that has elements that correspond to one or more hardware elements in this hardware element modeling unit, wear elements are accessed and used for modeling. That is, test data is provided from the workstation to the physical elements within the hardware modeling unit. After testing, the test results are returned from the hardware modeling unit to the workstation. In this way, the actual hardware elements are used in the modeling instead of the software model.

However, these existing devices are subject to several limitations. First, as mentioned above, each workstation is associated with a separate hardware modeling unit that it supports. Thus, for example, four such workstations would require four hardware modeling units. As a result, each hardware modeling device must be provided with one of these integrated circuits in order for each user to have access to one given integrated circuit for modeling. This is impractically expensive. This may also be difficult or impossible for dedicated circuits if only one or a few such circuits are present.

rPMX J and rReal Chip J also suffer from various technical deficiencies. For example, these are
It is understood that the ability to clock hardware elements at the very high speeds required to keep some elements active is lacking. Other features desirable in circuit modeling systems are also lacking.

Therefore, there is a need for improved hardware modeling circuit systems and methods that address these and other problems of prior art devices and are directed toward miniaturization.

SUMMARY OF THE INVENTION In accordance with one aspect of the present invention, a hardware modeling circuit system allows users at multiple workstations to access a single piece of hardware modeling circuitry on a partitioned basis. The hardware modeling circuit means includes means for providing test data to pins of one or more hardware modeling elements, such as integrated circuits, printed circuit boards, and circuit subsystems. In addition, the hardware modeling circuit means includes means for collecting result data generated from the hardware modeling elements during evaluation. Timing analyzer means, which may be optionally provided, time-analyze the outputs from the pins of the hardware modeling element under test, allowing the behavior of asynchronous signals of the resulting data to be observed and evaluated.

Another feature of the invention provides that the hardware modeling elements are
A clocking means is provided for generating a high frequency device clocking signal for clocking such elements at the frequency necessary to keep them in operation. Also, the frequency and other characteristics of these signals are variable. For example, the clocking frequency can be varied from 12.2 K) to 16.67 MHz in 20 ns increments depending on the clocking needs of the hardware modeling elements.

Another feature of the invention includes means for employing software-generated phase clocks as needed when the hardware modeling elements are complex.

Yet another feature of the invention is the use of three-state detection means and techniques to detect high impedance states on the output pins of hardware modeling elements.

Yet another feature of the invention is that the hardware modeling circuit means detects bus collisions between the hardware modeling circuit means and pins of the hardware modeling element and limits the current at such connections. device to prevent it from burning out or overheating.

In addition to allowing timing analysis of actual test results, the present device also allows timing evaluation from software file data that defines the minimum, maximum, and representative ranges of timing parameters of the hardware modeling device used in the modeling. .

Yet another feature of the invention is that the hardware modeling circuit means provides clocking and control signals to the integrated circuit or printed circuit board subsystem modeling elements as required, thereby controlling the operation of these hardware modeling elements. and means for synchronizing the hardware modeling circuit means.

Yet another feature of Zero Development is that it uses unique gating circuit means to access the pins of hardware modeling elements, and such gating circuit means
It is to have one or more of the above characteristics.

Another aspect of the invention automatically partitions system memory and
The purpose is to provide a means for allowing multiple users to use the system.

It is therefore an overall object of the present invention to provide an improved hardware modeling circuit system, an improved hardware modeling circuit means and an improved gating circuit means for using hardware modeling elements in the simulation of electrical circuits. is to provide.

These and other features, objects, and advantages of the invention will be apparent from the following description and drawings.

[Detailed description of preferred embodiments]

Referring to FIG. 1, the hardware modeling system of the present invention includes hardware modeling circuit means 10.
, which is connected to a plurality of electrical circuit simulation workstations 14 by means of a computer network interface means 12 on the basis of the split network principle.
is interfaced with. Hardware modeling circuit 10 is adapted to receive a plurality of integrated circuit elements, some of which are schematically illustrated at 16.

It also receives a printed circuit board or circuit subsystem, as shown schematically at 18. These integrated circuits, printed circuit boards, and circuit subsystems--both together and individually--are referred to as "hardware modeling elements" or rHMEs J. As explained below, these hardware modeling elements are accessed and used as simulation elements when designing the circuit at workstation 14.

Generally, workstation 14 is designed to perform and evaluate computer simulations of circuits being designed. Typically, the workstation includes a software model of the elements of the circuit to be analyzed. Using such software models eases circuit design and evaluation. Such workstations are currently manufactured by Mentor Graphics, Inc.
Daisy Systems and νalid Lo
Manufactured by companies such as gic systems.

As mentioned above, there are limitations to the use of software models of circuits. To overcome these limitations, the present invention provides workstation 14 with access to actual physical hardware modeling elements 16, 18 when needed. Physical hardware modeling elements are thus used in circuit simulation instead of software models of such elements.

Generally, if the workstation 14 recognizes that a circuit element used in design or evaluation corresponds to one of the hardware modeling elements 16.18 within the hardware modeling circuit 10, then the element is accessed by that workstation. As far as the user is concerned, software models and hardware modeling elements coexist and can both be used when simulating. Stimulus vectors, or input test data generated at the workstation in the same manner as such vectors, are generated for the model to be evaluated in software and sent to the hardware modeling circuit 10. Corresponding stimulation signals are applied to appropriate pins of the corresponding hardware modeling element. The resulting output signals from the hardware modeling elements 16.18 are converted into corresponding resulting test data and returned from the hardware modeling circuitry 10 via the network interface 12 to the appropriate workstation 14 upon completion of the evaluation. It will be done. Thus, network interface 12 functions as a means for receiving input test data from workstations and a means for receiving resultant test data from hardware modeling circuits.

A Domain''1 network from Apollo Computers Inc. couples a plurality of workstations to the network interface 12 and thus to the hardware modeling circuitry 10.

The network interface 12 also includes a 17a
Eight polio Model No., DSP-80 (
A) is equipped with a combinator like the one shown in FIG. The network interface 12 connects multiple workstations 1
4 allows not only the division of a single hardware modeling circuit 10, but also the division of additional hardware modeling circuits that may be coupled to its interface, as schematically illustrated by line 22. A substantial library of hardware modeling elements 16 and 18 is thus obtained, with each workstation having divided access to all hardware elements within this library. The hardware modeling circuit 10 thus eliminates the need for duplication of hardware modeling elements 16,18. However, each workstation has access to all hardware modeling elements within the system.

Hardware modeling circuit 10 includes control circuitry 24 , user memory 26 , operating memory 28 and a plurality of integrated circuit interfaces 30 , the last integrated circuit interface 30 carrying integrated circuit hardware modeling element 16 . User memory 26 can be optionally augmented with additional memory, such as an attached virtual disk file 27. In addition, a human output port 32, similar to an integrated circuit interface 30, is provided to couple hardware modeling circuit 10 to printed circuit boards and subsystems 18 when such elements are used in modeling. A timing analyzer 34 is also provided to analyze the resulting data generated from the hardware modeling elements during evaluation. Control circuit 24 and therefore hardware modeling circuit 10 are connected to network interface 12 via coupler 36 .

One suitable coupler is a multi-channel coupler such as the multi-bus circuit board Model 53c (single board computer) available from Intel Corporation. The connections of these elements of hardware modeling circuit 10 and their general functions will be described next.

Control circuit 24 is a microprocessor-based circuit that performs a variety of functions, as will be discussed in more detail below with reference to FIG. This control circuit generates the various clocking signals necessary for circuit simulation, establishes appropriate data flow paths through the various blocks of the hardware modeling circuit 10, and applies stimulus data to the various hardware modeling elements. starts and stops the operating system, determines whether a timing analysis should be performed by the timing memory circuit 34, monitors commands from a software server running on the network interface computer 12, and reads the operating system from the user memory 26. Set up and initialize direct memory access (DMA) transfers of data to memory 28. Thus, the control circuit 24 is controlled by the hardware modeling circuit 10.
arrange the movement of data between the various elements of the

More specifically, the elements of the hardware modeling circuit are interconnected as follows. A 16-pin bidirectional data bus (SYS-DAT) 38 interconnects control circuit 24, integrated circuit interface 30, input/output ports 32, and timing analyzer 34. A 24-bit address bus (SYS-ADD) 40 and a system control bus (SYS-CTRL) 42 also interconnect these same elements. Additionally, a stream clock bus 44 interconnects each of these elements except for user memory 26. A streaming address bus 48 couples control circuitry 24 to operating memory 28. A 256-bit vector data (VEL-DAT) bus 50 connects user memory 26 to operating memory 28, integrated circuit interface 30, and input/output ports 32.

Finally, the 64-bit unidirectional timing (TIM) bus 5
2 includes an integrated circuit interface 30 and an input/output board.
32 to a timing analyzer 34.

Generally, data (ie, stimulus data from the user's workstation 14 to be applied to a particular hardware modeling element 16, 18) and addresses and other information are loaded into the user memory 26. Server software within network interface 12 participates in user memory 2G receiving data from the user. This software also handles virtual user memory disk files 27, as discussed below. User memory 26 is typically 1 to 8 megabytes of dynamic MO3RA
It is M.

This memory is relatively slow and is not used to add stimulus vector data to the hardware modeling element 16.18. Instead, this memory temporarily stores one or more user's data before passing the user's data to operating memory 28 . Operating memory 28 and user memory 26 operate independently to load simulation experiment data from one or more users into user memory 26 and to load data vectors for one user's evaluation into operating memory 28. Add to hardware modeling element 16.18 selected from .

Upon completion of a user's evaluation or experiment, information participating in the next user's evaluation is transferred from the user memory 26 to the operating memory 28 under the direction of the control circuit 24. The operating memory 28 stores simulation vectors for evaluation by -users just before transferring these vectors to the desired hardware modeling element 16.18 for a simulation evaluation cycle.

The operating memory 28 is a high-speed static 1? A
Equipped with M memory. During the evaluation cycle, vector data stored in operating memory 28 is clocked into the selected hardware modeling element 16.18 by stream clock 44. As explained below, this clocking speed is varied to satisfy the requirements of the particular hardware modeling element used in the evaluation. Additionally, in the illustrated embodiment of the invention, 16.6
Clocking speeds of up to 7 Mllz are provided, allowing high-speed hardware modeling elements to be clocked fast enough in operation. Operating memory 28 typically consists of two parallel circuit boards (16 to 128K each).
with a total storage capacity of 32 to 256, or two sets of such circuit boards with a total storage capacity of 32 to 256. In the former case, operating memory 28 has 32
vectors (256 bits each), 16 vectors for each pin on a 128 pin device, or 8 vectors on a 256 pin device. When two sets of operating memory boards are used, the storage capacity is doubled. Thus, operating memory 2
8 is any one hardware modeling element 16.
18, it can be expanded to accommodate a larger number of stimulation vectors.

To save storage space, if the number of pins of a hardware modeling element exceeds 128, the data is loaded into sequential word block locations in the operating memory 28 and the hardware modeling element under test 16.18 Add to. The resulting data from the hardware modeling elements are then multiplexed and aligned in time.

Data from operating memory 28 is clocked into the appropriate hardware modeling elements 16.18 in response to signals on stream clock bus 44. That is, in response to a clock signal, data from operating memory 28 is transferred to vector data (VEC-DAT) path 5.
0 to a suitable integrated circuit interface 300A resistor. Address information is provided along streaming address bus 48 to data stored within operating memory 28 .

For each pin of the hardware modeling element,
DAT bus 50 carries two bits of information. One is a control bit that indicates whether the hardware modeling system should drive the pin or receive data from it. The other bit is a data bit. As a result, VEC-DAT bus 50 carries twice the number of bits as there are pins of the hardware modeling element. VEC-THAT
Since the hash is only 256 bits wide, it typically only supports 128 pin devices.

Two pieces support a 256-pin device. Two sequential transfers to IClF 30 or input port 32 are made on the VEC-DAT bus, as described below. For this purpose ICI
-CLKI and ICI-CLK2 buses are used. I
CI-CLKI converts the first 256 bits to VEC-DAT
clocked across the bus, while ICI-CLI2 clocks the second 256 bits. Once all data has been transferred, the master clock MAS-CLK then passes all of this data through and mounts the control bits of the pins of the hardware modeling element 16.18 to the ICIF or I/O ports.

In response to a read signal on the system control (SYS-CTRL) bus 42, the resulting data is transferred from the IC interface port sample register to the system data (SYS-DAT) bus 38 when timing analysis is not used or when timing analysis is used. If so, it is transferred from the timing analyzer 34. System data bus 38 passes the resulting information to the user's workstation 14.

If timing analysis is used, the system control bus 42
The above control signal enables the timing analysis portion of the hardware modeling circuit IO, as described below. Generally, during timing analysis, the desired pins of the hardware modeling element 16.18 are set at a periodic rate, e.g.
Sample at a sampling rate of 100 Mllz. The sampled data from these pins is
Allow users to observe timing behavior, such as asynchronous behavior, of hardware modeling elements. This provides a more accurate representation of the timing characteristics of the modeling element.

Each hardware modeling element has its own timing characteristics and does not model the range of minimum to maximum timing characteristics that can be applied to other elements of the same type. When such information is needed instead of or in addition to using timing analysis, the timing information is generated in software in the same manner as currently used in existing software model systems. That is, timing data relating to a particular hardware modeling element 16,18 can be stored in a software file that is accessible by the workstation 14. For example, this timing data includes minimum, typical and maximum response times for hardware modeling elements 16.18.
Provided against. Timing information can be calculated from this data.

1.2.3 and 6, the control circuit 24 will now be described in detail. The control circuit generally includes a clock circuit section 56 to generate a clocking signal on the stream clock bus 44, as described in more detail in the clock circuit description below. These signals are shown in FIG. 2 and discussed below. In particular, clock circuit 56 includes a clock parameter register 58 , a high frequency clock generator 60 , a reference clock generator 62 , a device clock generator 64 , a streaming control clock sequencer 66 , and a streaming clock time alignment circuit 68 . When performing an evaluation, a user at workstation 14 can select the desired clocking waveform type, clocking frequency, and duty cycle. This information is provided to a clock parameter register 58, which controls the reference clock generator 62 and device clock generator 64 to determine the corresponding hardware modeling elements 16.
18 to generate a device clocking signal.

In the illustrated embodiment, waveform generators 62 and 64 produce all clock signals for hardware modeling elements 16.18. Typically, these waveforms include no return to zero signal, return to zero signal, and return to one clocking signal. The clocking frequency can also be varied by the user, in the preferred embodiment from 12.2 KHz (81,94 μs) to 16.67 μs in 20 μs increments.
It can be controlled up to Mllz (60 ps). When generating the necessary clocking signals, a high frequency clock generator 6
0 produces a clocking signal at the highest signal frequency rate, which in turn controls and synchronizes the reference clock generator 62 and device clock generator 64. A streaming control clock sequencer 66 and a streaming clock time alignment circuit 68 align the clocking signals at the appropriate times to produce the clocking signals needed by the hardware modeling circuit 10.

In addition to the clock circuit 56, the control circuit 24 includes an Intel 80186 that executes software programs stored in local memory and program memory 72.
A microprocessor 70, such as a microprocessor, is included. This programming of the microphone 9 processor 70 will be apparent from the following description and the flowchart of FIG. The control circuit 24 also controls the user and operating memory 2.
6.28 and the network interface 12 is provided. Address bus 4 streaming address information
A streaming address circuit 76 is provided for passing to operating memory 28 on 8. Microprocessor 70, local and program memory 72, access and DMA controller 74, and streaming address circuitry 76 are interconnected by system bus 77, and system data, system address, and system control output signals are provided on buses 38, 40, and 42. give.

The simulation software running on the workstation 14 is the hardware modeling element 16.18
When it needs to be evaluated, it passes the request to the server software running on the network interface 12. If this is the first request for simulation, the server examines its map in user memory 26 and allocates four storage areas. (1) Task Control Block, (2) Vector Data Block, (3) Linked List, and (4) Results Area. The purpose of these four storage areas will be discussed individually below.

The task control block embodies the setup and run-time configuration information for the simulation experiment. The task control block stores the following information. Address (I) of hardware modeling element 16.18 to be evaluated
C interface port number and socket number of the interface port where the hardware modeling element is installed); clocking information (clock period, data/clock setup time, clock duty cycle); flags that determine whether timing analysis should be used or not an address pointer to where the result of the evaluation should be placed; a transaction code to be returned in the result queue when the task is completed; a list of input and output pins for clocks, open-collector, three-state, and hardware modeling elements; unknown number and location; address pointer to a linked list of vector data.

Vector data blocks store stimulus data for hardware modeling elements 16.18.

This block expands with each new evaluation cycle.

The newest vector is concatenated to the end of any existing vector.

A linked list contains information that connects discontinuous blocks of vector data. If the simulation is performed many times, the size of the vector data will increase. The server software may need to split such data blocks into two or more discrete pieces so that they can fit into the available storage space. If a large block can be divided into several small blocks, the hardware modeling system 1 can be used for multiple simultaneous simulations.
0 operation becomes easier. The linked list provides a mechanism for this server software and control circuitry to bridge discontinuous blocks. Each element in the linked list contains three pieces of information that add up to one data block. (1)
the size of the block (in byte coefficients); (2) an address pointer to the location of the block in user memory 26; (3) an address pointer to the next element in the linked list. Linked list blocks can potentially suffer from the same problems as vector data blocks.

That is, if it becomes too large, it must be split into two or more pieces to fit into the available storage space.

An address pointer pointing to the next linked list element provides a means of connecting the linked list elements.

Finally, the results area stores the results data generated by the evaluation cycle. The control circuit 24 places the data into the result area and the server software reproduces it.

Generally, simulation software running on the workstation 14 is the hardware modeling element 1.
When a 6.18 evaluation is required, it passes the request to the server software running on network interface 12. The server constructs a task control block, passes it to user memory 26, and places an address pointer to the task control block in a command queue in user memory 26.

Control circuit 24 continuously scans the command queue.

When it sees any non-zero value, it considers that value to be a valid address pointer to a task control block. Control circuit 24 decodes the information in the control block and sets up clock circuit 56, streaming address circuit 76, and IC interface 30 or input/output port 32 appropriately.

Control circuit 24 reads the linked list and uses address pointers and block size information to locate and DMA transfer each vector data block from user memory 26 to operating memory 28 one at a time. The control circuit performs a transfer operation using an access/DMA control circuit 74. The first block of any given evaluation starting from address zero in operating memory 2
Load into 8.

Any additional blocks for the same evaluation are sequentially appended to the end of previously transferred blocks, thereby combining them into one continuous block. Any "unknown" within the vector data is treated as a logical 1 or 0, as selected by the user.

Once all the vectors are in the correct order in operating memory 28 and the total number of vectors has been determined,
Control circuit 24 sets the "go" bit in the control register and automatically starts the clock circuit (this "
The use of the "go" bit is shown in the stream-go line of FIGS. 18 and 19). The clock circuit generates a control clock that moves data from operating memory 28 through IC interface board 30 or input/output port 32 to hardware modeling element 16.18. This becomes clear from the explanation of the control clock described later and the time diagram of FIG. 3. When the evaluation starts, the control circuit 24 sends an "end" signal from the vector counter 75.
Wait for the flag to become true. If the "end" flag is true, the entire vector stream of evaluations is transferred from operating memory 28 to the appropriate hardware modeling element 16.
Added to 18. Vector counter 75 counts the number of stimulus vectors waiting to be clocked into the hardware modeling element. When the vector counter reaches zero, the "end" flag becomes true (Figures 18 and 19 illustrate the use of the signal from vector counter 75).

Since each simulation evaluation contains only one new vector, the last one in the total vector stream relates to the only response from the hardware modeling element of interest 16.18, and the last one to which this response was added It is a response to a vector.

Without timing analysis, this response may be recorded in the form of a single response vector. Instead, this response is recorded as many sequential high speed samples made by timing analysis circuit 34.

If timing analysis is not used, the evaluation results will be
It is retrieved from a sample register in a gate array, described below, located on interface port 30 or input/output port 32. If timing analysis is used, the results of the evaluation are retrieved from the memory of timing analysis circuit 34 and moved to the result area in user memory 26 identified by the result address pointer in the task control block.

Control circuit 24 zeroes the entry in the command queue and writes the transition number obtained from the task control block to the result queue. This signifies to the hardware modeling control circuit 24 that the task is complete.

While any task is waiting for completion by control circuit 24, the server software continuously scans the result queue. When it sees any non-zero value, it sees that value as a valid transition number.

Since the server software originally assigns transition numbers to evaluation tasks, this requires the user memory 26 to obtain the results.
A number can be used to determine the correct address within the . The server software receives results from user memory 26 via multipath adapter 36 and passes them to simulation software running on workstation 14.

This completes one evaluation cycle of hardware modeling element 16.18.

, F1% memory management The memory manager is part of the server software running on the network interface computer 12. This controls the allocation of storage space within user memory 26. At the bottom of the user RAM are fixed-length blocks of memory used to pass messages between the server and the hardware modeling system firmware.

This area is not under the control of the memory manager. All of the remaining user RAM is used for vector data, task control blocks, linked lists, and results areas. A memory manager controls this area of memory.

The memory manager makes no distinction between memory allocations for any particular function. A "free list" is a linked data structure. Each element of this list represents a block of memory (256 bytes).

All allocations start with a "free list" and deallocations end with a "free list". Maintaining virtual disk files 27 has a similar structure.

This file is optional and stores vector data that overflows the user RAM, as described below.

Each record for each hardware modeling element 16.18 contains two indicators. The first indicator indicates that the data for the hardware modeling element is currently all in user RAM.
Indicates whether it is in-memory. A second indicator indicates whether evaluation of that hardware modeling element is currently in progress (in-queue). In-memory indicators are maintained by the memory manager. The in-queue indicator is maintained by the server and used to determine whether the hardware modeling element's data can be safely swapped between user RAM 26 and virtual disk file 27.

Heavy use of user memory 26 or only limited use of user memory 26 results in starvation of space within the user RAM. This means that the entire space is occupied by the data of the hardware modeling elements, and the system overhead is limited to the user memory 26 in the hardware modeling system.
Occurs whenever the current amount of is exceeded. When this happens,
All of the vector data associated with one hardware modeling element 16.18 is swapped into the virtual disk file 27. That is, all vector data applied to the hardware modeling element is transferred to the network interface computer 12 and then written to and stored in a file on disk memory. Once the data has been migrated, all user RAM that was allocated to store that data is returned to the "free list" awaiting reallocation.

The selection of which hardware modeling element to swap data is made by first checking the hardware modeling element 16, 18 whose vector data has already been swapped.

If none is found, select the earliest used hardware modeling element. If the hardware modeling element is being evaluated, or if the evaluation is bending (as a function of the commands in the command queue (in-queue)), it does not swap. If no equivalent hardware modeling element data is found to be swapped, the user can do something like suspending the current command in progress until a swappable set of data is found, or returning the results at the end of the evaluation. Hold until memory is freed for some other reason.

The disk file 27 used to store vector data of hardware modeling elements is a partial file that stores 2 bytes. These segments are handled in much the same way as user RAM blocks are managed. If the swapped vector of hardware modeling elements is copied back into the hardware modeling system 10, the disk image is retained until the channel associated with it is closed. By eliminating these vectors on disk, if another swap is needed, we only need to move the vector that occurred after the last swap. Hardware Modeling Elements 16.1 (as indicated by the "in-memory" flag)
If the data associated with 8 is not in the user RAM, it must be reloaded and rebuilt. The first step is to copy all vector data from disk file 27 to a buffer within the server.

Second, the server is told to reset its hardware modeling elements. Third, the buffer is passed to the server and the server is instructed to reconstruct the data block of the hardware modeling element. Finally, perform the evaluation sequence.

1 and 2, the clock circuit 56 moves the stimulation of the hardware modeling elements of the control circuit 24 from the operating memory 28 to the IC interface 30 or input/output port 32. , is the part that captures any resulting response. This clock circuit is connected to the IC interface 30. Input/output port 32, operating memory 2 days and timing analyzer/memory 34
is connected to the stream clock bus 44.

In addition, clock circuit 56 provides a clocking signal to the high frequency device to clock the hardware modeling device at the frequency necessary to keep the hardware modeling device operational. The clock circuit 56 also clocks 12.2KIIz (81,940μs) in 20ns increments.
) to 16.67 Ml1z (60 ns). Other suitable clocking speeds are also provided if desired.

Clocking signals are provided directly to integrated circuit modeling element 16 via appropriate IC pins. However, some printed circuit boards or circuit subsystems 18 have their own on-board oscillator circuits to generate system clockers. These devices are synchronized with the hardware modeling circuit system by disabling this on-board clock and using instead the software-generated clock provided by the present invention.

The clock circuit 56 has a clock parameter register 58
, high frequency clock generator 60, reference clock generator 62
, a device clock generator 64 , a streaming control clock sequencer 66 , and a streaming clock time alignment circuit 68 . IC interface 30, input/output port 32, operating memory 28 and timing analyzer/memory 34 (if used)
On the other hand, the clock circuit 56 generates eight clocks. These clocks are as follows.

1. EV-CLK provides a means to provide programmable hardware modeling element clocks. This clock provides the signal that actually pins the clock pin of the hardware modeling element being modeled.

2. M^5-CLK provides a means for temporally aligning stimuli from operating memory.

This clock is used to provide stimulation from the operating memory to the hardware modeling element 16.18.

3. ICI-CLKI provides a means to temporally align stimuli from operating memory. This clock was previously described for VEC-DAT bus 50.

4,1CI-CLK2 provides a means for temporally aligning stimuli from operating memory. This clock was also described above with respect to the VEC-DAT bus 50.

5.5 MM-CLK provides a means to capture stimulus and response information of hardware modeling elements. This clock provides signals after all stimuli have been applied to the hardware modeling elements and controls writing the responses of the associated hardware modeling elements.

6.0M-CLK provides a means to move stimuli from operating memory. One stimulus vector for each OM-
CLK pulses to the hardware modeling element.

? , CLK25. PHO is a timing analyzer and memory circuit that provides a means to analyze the timing of hardware modeling element components. This clock evaluates the propagation delays between the pins of the hardware modeling element with better granularity than other signals used by the timing analyzer and memory circuit 34.

8. CLK25+11 is also a timing analyzer/memory circuit that provides a means to analyze the timing of hardware modeling element components. This clock is the upper CL
Used with K24PIIO.

A high frequency clock generator 60 provides a signal at the fundamental operating frequency to the hardware modeling circuit system 10. A MHz crystal oscillator clock is used, which provides a 10 ns timing state for the hardware modeling circuit system.

In addition, the high frequency clock generator 60 has two 25MHz
Timing memory clock (CLK25PIIO and C
LK25pHl). These are shifted in phase by 90 degrees with respect to the timing analyzer/memory 34.

Clock generator 60 also provides a microprocessor clock on line 71 to control circuit microprocessor 70.

Clock parameter register 58 sets the fundamental frequency of the device,
Provides a means to program duty cycle and time alignment parameters. There are four clock parameter registers:

1. REF-CLK frequency register.

2. DEV-CLK set-up delay register.

3. DEV-CLK hold delay register.

4. Time alignment register.

REF-CIJ Blue Registration The REF-CL frequency register provides a programmable means for providing the hardware modeling elements 16.18 with the variable frequency necessary to keep these elements operational.

Loading of this register is performed by the microprocessor 7.
This is achieved by 0. The microprocessor 70 supplies the addresses of its registers and data computed and gathered from the task control blocks in the user memory 26. In the above embodiment, the allowable frequency register values are from 1 to 4095. Value O is not allowed.

Each increment in the value of the frequency register increases the REF-CLK period by 20 ns. For example, a 1 written to this register will cause the reference clock generator 62 to clock in at 60 ns.
gives the device clocking period of A value of 4095 results in a device clocking period of 81.94 μs.

DEV-CLK center door correct DEV-C
The IJ set-up delay register provides a means for providing the hardware modeling elements 16, 18 with the variable device set-up time necessary to keep these elements properly stimulated.

DEV-CLK set-up delay register is DEV:C
It only affects LK generation.

During the setup time, the operating memory 28 is kept at a temporally constant stimulus application point, MAS-CLK.
This is provided by varying the rising edge of DEV-CLK.

Each increment in the value of the set-up register is
Allow a 10 ns delay period to elapse from the S-CLK rising edge before the positive edge of the DEV-CLK signal occurs. This programmable delay is illustrated by several possible positions of the DEV-CLK pulse relative to the MAS-CLK pulse, as shown in FIG.

The value of the contents of this register must be less than the value of the hold delay register. In this particular illustrated example, allowable values are from 1 to 4095. value 0
is not allowed.

DEV-CLK hold ゛ Correct register DEV-CLK
The hold delay register provides the hardware modeling elements 16.18 with a programmable means of providing variable device hold times necessary to keep these elements properly stimulated. The DEV-CLK hold delay register only affects DEV-CLK generation.

The hold time is determined by keeping the operating memory 28 at a temporally constant stimulus application point, MAS-CLK, while DE
This is given by varying the V-CLK rising edge.

This is also shown in FIG.

Each increment of data in the hold register is DE
Allow a 10 ns delay period to elapse before V-CLK decays. The value of the contents of this register must be greater than the value of the Setup Delay register. This is because DEV-CLK cannot assert itself until the setup delay time has elapsed. In this example, allowable values are from 1 to 4095.

A value of 0 is not allowed.

The wait time alignment registers provide a programmable means to vary the set time during which the device captures a response and compensate for standard component tolerances to increase resolution and accuracy during timing analysis.

This time alignment register holds three fields of 3 bits, each containing a delay of 4 of the 8 streaming clocks.
OM-CLK, SAM-CLK and two timing memory clocks CLK25PHO and CL
Provides a means to add to K25Pl+1. The three fields of programmable delay are as follows:

1. OM-CLK delay 2. Timing memory clocker delay 3. SAM-CLK delay For OM-CIJ delay, 3 bit fields provide 2 ns increments for values from 0 to 7. This is MAS-CLK, ICI-CLKI and ICI-
CL to 0 for 2) 1 - Gives CLX a maximum delay of 14ns.

For timing memory clock delays, a 3-bit field provides 2 ns increments for values from 0 to 7. This also gives a maximum delay of 14 ns to the timing memory clock for MAS-CLK, ICI-CLKI and ICI-CLK2.

For SAM-CLK delay, the 3-bit field is 0.
gives an increment of 50 ns for a value of 7.

This includes 185-CLK, ICI-CLKI and IC
Give SAM-CLK to I-CLK2 a maximum delay of 350ns.

A reference clock generator 62 provides a means for generating a fundamental operating frequency clock signal for the hardware modeling element 16.18. A pulse train is generated that defines the operating frequency for the elements in the device 64.

The input to the reference clock generator is taken from the clock parameter register 58 (ie, the frequency register at REF-CL).

Reference clock generator 62 is a 12-bit counter;
This decrements each 10 ns period until it reaches zero. When it reaches zero, this counter is reloaded and repeats the count. Reloading the counter thus provides a programmable means of providing variable frequencies.

Device Clock A device clock generator 64 provides a means for generating setup and hold time signals for hardware modeling elements. That is, it provides a variable duty cycle output (from the DEV-CLK Setup Delay Register and the DEV-CLK Hold Delay Register).

The device clock generator 64 includes a pair of clocks that each decrement by 10 ns after the start of each reference clock period.
Equipped with a 2-bit counter. Setup delay is the first
In addition, the rising edge of DEV-CLK after the reference clock is delayed. This is followed by a hold delay counter and DE
Delay the falling edge of V-CLK.

Both the set-up counter and the hold delay counter expire within the reference clock generator period. This provides a means to change the position of the DEV-CLK signal clock edge relative to the stimulus delivered to the device (see Figure 3).

Streaming 1' Clock Sequencer Streaming Control Clock sequencer 66 provides means for moving hardware modeling element stimuli from operating memory 28 to IC interface circuitry 30 and input/output ports 32. In addition, this sequencer 66 performs timing analysis and provides a means to start and stop the streaming clock.

The streaming control clock sequencer 66 generates the following streaming clock.

1, 0M-CLK.

2, 1CI-CLKI, 3. ICI-CLK2. 4, M^5-CLK.

5, 5MM-CLK.

The specific sequence of streaming clocks is influenced by the hardware modeling element IC interface port type. This sequence is adjusted to provide the necessary time demultiplexing of the stimuli being backed into operating memory. This unbacking and alignment is performed on OM-CLK, ICl-Cl, 1.
This is achieved with ICI-CLK2 and MAS-CLX.

The IC interface port 30 for hardware modeling elements having 64 pins and 128 pins is
Those stimuli on the EC-DAT bus can be received at any one instant. , since the bus is 256 bits wide. FIG. 18 shows an exemplary 64/
4 vector transfers of 128 pins are shown.

The REF-CLK signal of FIG. 18 is an internal clock circuit signal generated by reference clock generator 62 and drives streaming clock sequencer circuit 66. Stream-Go was referred to when discussing the control circuit previously described, and is the assertion of the ``go'' bit that starts clock circuit 56. The vector counter signal indicates the number of vectors that still need to be transferred from operating memory 28. is the signal from counter 75. Vector counter 75 is decremented on each OM-CLK pulse. When the vector counter signal reaches zero,
The "complete" flag described above in connection with the control circuit is set, and the simulation ends.

The operation of interface board 30 for hardware modeling elements with more than 128 pins is as follows:
It's a bit more complicated. For 256 pin devices, 512
2 on the VEC-DAT bus to provide a bit stimulus.
Rotate. Therefore, the two transfers require OM-C to both
Performed on VEC-DAT using IJ.

ICI-CLKI captures the first vector and ICI-
CLK2 captures the second vector and MAS-CLK simultaneously provides stimulation to the hardware modeling element. See FIG. 19 for the transfer of four vectors (double vectors) in 256 pin format.

A streaming control clock sequencer 66 also provides a means for pipelining the stimuli. Pipe is 60ns
required to provide a very short stimulation period. When moving stimuli from operating memory 28 to the hardware modeling element, there are a minimum of three pipe stages.

These are:

1. Bus of vector addresses to operating memory 2. RAM access of stimulus vectors 3. Bus of vector stimulus data to IC interface circuits All three stages are fully matched and provide a minimum vector cycle time (60 ns). .

In addition to providing stimulus motion control, a streaming control clock sequencer 66 also provides M-CLK to the stimulus response acquisition controller S. This timing pulse is generated after all stimuli have been applied to the device.

The R11l2 wholesale clock sequencer 66 is also a timing analyzer and memo IJ34 to enable analysis of the timing behavior of hardware modeling elements.
Gives start and stop information to. This start and stop information is provided via an enable timing analysis line (not shown) that connects the sequencer 66 and the timing analysis/memory 34.

Streaming clock l. The one-day streaming clock time alignment circuit 68 provides a means to compensate for standard component tolerances and increase resolution and accuracy during timing analysis to provide variable set times for device response acquisition.

Time alignment is performed by four of the eight stream clocks mentioned above, namely OM-CLK, SAM-CLK, CL.
Given to K25PIIO and CIJ25PH.

In the case of element tolerance, the operating memory clock (OM-CLK) is aligned by adding a delay to the stimulus acquisition at the gate array (described below). Differences in propagation time within an element from the operating memory board 28 to the gate array output register can be compensated for from system to system. Compensation ensures confidence and system performance.

For device set times, align the sample clock (SAM-CLK) by adding a delay to the last stimulus applied to the device. This allows the time required for the device to drive or release its output to be variable. This process prevents capacitive effects of hardware modeling elements from corrupting the read logic state.

For timing analysis resolution and accuracy, the timing memory clock (CIJ25PHO and CLK25PH
1) is simultaneously delayed for 185-CLK, ICI-CLKI and ICI-CLK2. This allows the calculation or measurement of the wavefront propagation delay between the pins of the hardware modeling element device with better granularity than is available at the operating frequency of the control circuit 24.

Additionally, this provides a means to determine the delay added by the hardware modeling elements.

Access 1' Access and direct memory access (DMA) control circuit 74
provides control circuit 24 with a means for passing messages and data between workstation 14 and user memory 26. Additionally, this provides a means to directly transfer hardware modeling element stimuli between user memory 26 and operating memory 28.

Access and DM control circuit 74 is responsive to requests from multipath adapter 36 to complete transfers to or from user memory 26 and responsive to requests from microprocessor 70 to transfer data from user memory 26 to operating memory 28. Stimulate DMA to.

Control circuit 74 operates in one of three modes according to the current state of evaluation. The series of evaluation states is as follows.

■, System mode □Hardware modeling circuit 1
0 is idle or processing evaluation data.

2.0M8 - Hardware modeling circuit 10 transfers stimulus data from user memory to operating memory.

3. Stream Mode □ The hardware modeling circuit 10 is applying a stimulus or capturing evaluation results.

Upon completion of stream mode, microprocessor 70
returns the hardware modeling circuit 10 to system mode.

All three modes permit access to user memory 26 from workstation 14.

However, in the read mode, transfers from user memory 26 to operating memory 28 are temporarily suspended until the workstation access is complete. Additionally, any workstation access to user memory 26 halts microprocessor activity until such access is completed.

-Loin -face integrated circuit interface board 30 and input/output ports 32 are designed to serve as an interface to hardware modeling elements. For this reason, integrated circuit 30 and input/output port 32 omit some functions. These convert input test data into hardware stimulus signals, apply these stimulus signals to the hardware modeling element 16.18, take output signals from the hardware modeling element 16.18, and apply these output signals to the resulting test. Convert to data. For simplicity,
Only the interface board 30 will be described. The operation of input/output ports 32 is similar.

Each integrated circuit interface 30 has the necessary interface electronics to properly drive stimulation signals into the hardware modeling element 16 and detect the resulting state information generated.

The illustrated hardware modeling apparatus requires a minimum of one integrated circuit interface port 30 (IC4F), and the hardware modeling circuit 10 has a maximum capacity of eight ICIF boards. ICIF details below
Board 30 will now be described.

The following definitions are useful in understanding the discussion that follows.

- IIME - Hardware modeling elements as described above.

・Word □ Refers to 16-bit data. It is used to describe data transfers between operating memory 28, user memory 26, and control circuitry 24.

・Bit-slice □ - Refers to a subset of data controllers that process one bit of data at a time.

- Block □ - Refers to a subset of data controllers that process 4 words, or 64 bits, of data at a time.

・Vector □ Points to 256-bit data. Used to describe the amount of simulation data transferred from operating memory 28 to ICIF 30.

・Half hector □ 128 bits of data.

- 5YS-DAT - 16-bit bidirectional data bus (38 in Figure 1).

- 5YS-ADD-24 bit address bus (40 in Figure 1). Used to refer to different access functions on the ICIP control board. The address comes from microprocessor 70 on control circuit 24 or DMA hardware 74.

・READ-system control system 42 (SYS, CT
RL) to control 4BICIP access, ICIF
A signal that transfers data from the output register to the 5YS-DAT bus 38 or, if timing analysis is used, to the 71M bus 52 (FIG. 1).

・WRITE□Sent on the system control bus 42 and sent to the IC
A signal that controls IF access to transfer data from the 5YS-DAT bus 38 to the input serge resistor of the ICIP gate array.

・VEC-DAT□Operating memory 28 to l
25 used to stream data vectors to ClF30
6-bit unidirectional data bus 50 (FIG. 1).

This bus originates on operating memory 28 and is
Provides 56 bits of data to each of the 8 ICIP board slots.

-DEV-CLK, MAS-CLK, ICI-CL
The stream clocks Kl, ICI-CLK2 and SAM-CLK (described above) enter IClF30 and constitute the control signals used to provide the correct timing and control functions to the driving elements of the gate array and hardware modeling elements of the ICIF. It is.

TM-DATA or TIM bus - 64-bit unidirectional data bus 52° used to send hardware modeling element response data to timing analyzer/memory 34 Pt1LL - old OW (or Pt1LL, BP
ULL) □ A 1-bit control signal used to enable performing a high impedance test on the output pin of the hardware modeling element device under test.

- System reset control for all R3T□ ICIF boards. This places the activated section ICIF board in a known initial state.

Note that buffered signals are denoted by the prefix letter rB. Therefore, BPULL is PULL
This is the same logic signal as L, but it is arranged in a buffer stage. Another bus symbol to note is that those with an asterisk after the bus name indicate a logic 1 state to a logic 0 state.
This shows a signal that is activated by changing its state. Therefore, RST'' is an inverted version of the R5T signal.

lClF30 is calculated from F8000 to F8F['FF (1
It responds to addresses on the 5YS-ADD bus 40 in the range up to (hex).

Each ICIF determines which slot it occupies on the back of the hardware modeling circuit, and the user
Slots - Saves you from programming usage information.

ICIF has two operating modes: system mode and streaming mode.

1. System Mode □ This mode allows pre-programming the ICl14 with specific pinouts and allows testing the operating mode of the hardware modeling elements. This mode actually has several sub-modes that allow the ICIF to be programmed to handle the hardware modeling element in question correctly. These submodes are:

a. Mode register setup mode - This submode is CLKEN, PP0L, NPOL and B
Allows PM to be latched into ICIF's mode register. These signals serve the following functions: CLKEN is
This is a mask clock enable signal. This signal enables or disables sending all stream clock signals to the ICIP board 30 (CLKEN, FIGS. 7 and 9). PP0L and its inverted NPOL determine whether the pulse sent in pulse mode is positive or negative (Figures 7 and 9 (7) PPOL and NPOL, ) BPM should operate in pulse mode to lCrF30. (BP in Figures 7 and 9)
M).

b. Setup mode for clocked pin functions □
This submode writes data on the 5YS-DAT bus 38 to the ICIF's internal clocking registers to program which pins on the hardware modeling element 16 are to be clocked.

C0 read mode □ This submode is when lClF30 is 5.
Allows data to be retrieved from the ICIF output registers via the YS-DAT bus 38.

d. Timing Analysis Mode □ This submode allows the timing analyzer and memory 34 to access output data from the pins of the hardware modeling element 16 under test.

2. Streaming mode □ In this mode, the control circuit 24 and operating memory 28
Allows you to control the flow of data vectors to. Vectors and half-vectors are transferred across the VEC-DAT bus 50.

In System mode, the I (JF30 is solely dedicated to the task of handling Place Dream mode setup and Vost-Stream mode data recovery.
All functions performed by board 30 are controlled by control circuit 24, so ICIP is essentially a slave. The manner in which ICIF is controlled is 5YS-ADD
Commands given to ICIF via bus 40 and 5Y
It depends on the write and read signals on the S-CTRL bus 42. Testing of the ICIF addressing scheme is orderly.

××××××××××××××× F 8 (Slot-Idle) Most significant bit x'xxx xxxx (Mode) (Block/Word) A total of 24 addresses are given, which are shown with an x mark. In this configuration, the first eight lines are used as board select addresses. In this example this is the number F8 (hexadecimal). The next four lines are used as slot-idle addresses. These are different ICs housed within the same system.
Differentiate between IF boards. Each board has an independent slot-idle address. The next four lines are not used. The next four lines are used to indicate mode-register setup. Finally, the last four lines are the gate array blocks (Figure 4), as described below.
is used to select and keep the word working.

The illustrated ICIF 30 uses two data formats, a 64 pin format and a 128/256 pin format as described below.

64-pin format This format allows one 128-bit half-vector to be driven into both halves of the high, low, or VE (knee) DAT bus 50. This format allows for simulation evaluation on hardware modeling elements up to 64 pins. The low and high half-vectors can be transferred from operating memory 28 in sequential memory cycles. In this format, the 64 bits above the 128-bit half-vector are data information, and the other 64 bits are data information, as described below. It is used for three-state control on gate arrays.

- 128/256 Pin Format In this format, a 256-bit data vector is driven onto the VEC-DAT bus 50. This is 128
Allows simulation evaluation of hardware modeling elements up to the pin. By using sequential vector positions, 256-pin hardware modeling elements can be evaluated. Control circuit 24 controls these modes.

lClF30 generally operates as follows.

A single ICIP board 30 is designed to accommodate one of almost any type of 256 pin hardware modeling element. The bus configuration is shown in Figure 4.
The general layout of the cIF board 30 will be clarified.

Note that one gate array 110 includes four gate array blocks 120, 122, 124 and 126. These blocks are groups of gate array devices designed to process vector data for the associated ICIF. Each block receives 128 data and drive control lines, with 12
It has 8 data input/output terminals, 64 data output terminals and several control lines.

Each of the four blocks 120-126 has independent control lines and can evaluate four different hardware modeling elements at different times. However, each hardware modeling element shall have 64 pins or less.

Hardware modeling elements with more than 64 pins require cascading additional blocks, with each added clock adding 64 pins of additional capacity. In this way, the four gate array blocks 120 to 1
26 allows each ICIF board 30 to handle hardware modeling elements with up to 256 pins.

More specifically, each gate array block 120~
126 includes four gate array circuit assemblies 290 (FIG. 5), three such gate array circuit assemblies connected to the 16 pins of the hardware modeling element via respective lines 128-134 (FIG. 4). can be accessed, stimulated and monitored. Each gate array circuit assembly 290 also includes a single 16-pin access circuit 292 subassembly. One such circuit 292 is shown in FIGS. 11 and 12 and will be discussed later in connection with FIGS. 11-17.

Gate array blocks 120-126 are connected to lines 136-
It is connected to the VEC-DAT bus 50 by lines 142 (FIG. 4) and to the stream clock bus 44 by lines 144-150 to receive clocking signals from the control circuit 24. Additionally, lines 152-158 couple these gate array blocks to address decode circuitry 160 of TCrF 30. Address decode circuit 160 signals along these latter lines to the appropriate gate array assembly 290 to access the hardware modeling element requiring modeling. Output lines 190-196 are connected to gate array blocks 120-126.
Output signals from the hardware modeling elements within are routed to an output bus 198, then to a timing bus 52 and, if timing analysis is employed, to a timing analyzer/memory 34.

If timing analysis is not used, the output data is instead routed along output bus 200 through an enabled transceiver circuit 202 to 5YS-DAT bus 38;
It is then returned to the user's workstation 14. Transceiver circuit 202 is enabled by a signal sent on line 206 from address decode circuit 160.

The logic of address decode circuit 160 is not roundabout and will not be described in detail. However, in general, the address decoding circuit 160 is a slot idle, board
A set of comparators are provided to compare idle, block-idle, word-idle and select functions. Logic gates are used to select different functions for setup, streaming and readout modes on gate array 110. Also, a decoder is used to select blocks and words. A flip-flop is used to latch mode register data for the gate array control functions. The address decode circuit 160 also
Provides a means to decide whether to use timing analysis.

The job of the address decoding circuit 160 is to set up the ICIF board 30 to match the pin definitions of the hardware modeling element under test, read the output pins during timing analysis, detect high impedance as described later, and The hardware modeling device 1 provides control signals for retrieving the resulting output data from the modeling elements and detects potentially disturbing faults such as when bus contention occurs on the data line.
It is to give a signal indicating that 0 has. lCl
The manner in which F30 performs these tasks is used in each ICIF block and is directly linked to the operation of the gate array device described below.

Figure 11 shows the rc interface (ICIF) 30
FIG. 2 is a block diagram of a single gate array circuit 292 of FIG.

One gate array circuit 292 is preferably connected to each input and output conductor/pin of the hardware modeling element under evaluation. Gate array circuit 292 can choose to apply drive signals to the input conductors of the hardware modeling element or to receive signals from the output conductors. Each gate array circuit 292 can provide a clock or data signal to the input conductor of the hardware modeling element, change the load impedance seen by the output conductor of the hardware modeling element, and detect bus contention. Bus contention occurs whenever both the gate array circuit and the hardware modeling element apply drive signals that impinge on the same conductor. Gate array circuit 292 can also apply signals from the output terminals of corresponding hardware modeling elements to timing analyzer and memory circuit 34 (FIG. 1). A timing analyzer/memory samples the signal for each Ions and accurately displays its timing characteristics.

Referring to FIGS. 11 and 12, gate array circuit 292 applies drive signals to or receives output signals from hardware modeling elements on IC(N) terminal 302. Referring to FIGS. The drive signal is a digital signal that varies between a "strong logic 0 state" and a "strong logic 1 state." Gate array circuit 292 operates only when the output of this gate array circuit is in a high interface state.
Receive output signals from hardware modeling elements.

Vector data bus 50 provides signals to switch the operating mode of the gate array circuit.

The first important function of gate array circuit 292 is to provide drive signals to the hardware modeling elements.

The control circuit 24 connects this circuit 29 to the gate array circuit 292.
Whenever 2 commands a clock signal to be provided to a pin of a connected hardware modeling element,
This control circuit 24 provides a signal to lo(N) terminal 304. This signal enables clock and data drive subcircuit 306 to provide the desired accurate lock signal to IC(N).
is applied to terminal 302.

The clock signal can be in the nature of a pulsed or single-edge signal. Control circuit 24 applies a pulse mode signal to input terminal 30B of subcircuit 306 to produce the desired type of clock signal. The pulse mode signal also directs the direction of transitions between logic states of the pulsed clock signal so that they correctly drive both negative and positive edge triggered input terminals of the hardware modeling element. . The pulse mode signal 308 in FIG. 11 is the BPM signal in FIG.

PP0L and NPOL signals.

Control circuit 24 applies vector data to D(N) input terminal 310 and applies a vector output enable control signal to C(N) input terminal 310.
N) applied to input terminal 312; In clock mode, C
The (N) signal does not affect the operation of drive subcircuit 306.

Control circuit 24 applies a plurality of clock signals in the correct time sequence to input terminal 314 of drive subcircuit 306, causes clock pulses to appear at output terminal 316 of drive subcircuit 306, and adjusts these clock pulses at desired times. to the relevant pins of the hardware modeling element 16.

Whenever control circuit 24 instructs gate array circuit 292 to provide a data signal to a hardware modeling element, control circuit 24 outputs a signal of 10(N).
This signal enables the drive subcircuit 306 to provide a drive signal of the desired nature to the IC(N) terminal 30.
Give to 2. A serial flow of vector data applied to D(N) input terminal 310 is applied to drive subcircuit 3 in response to the timing of a clock signal applied to input terminal 314.
06 at output terminal 316.

The clock signals applied to the input terminal 314 in FIG. 11 are as follows: BMcLK, BVCLK, BDCLK in FIG.
B, with signals marked BDCLK and BSCLK. These signals are connected to MAS-CLK by the circuit shown in Figure 9.
, ICI-CLKI, ICI-CLK2. D.E.V.
-CLK and SAM-CLK.

When in clock mode or data mode, tristate driver 318 connects drive subcircuit 3 at its input terminal 320.
06 and its output terminal 32.
2 to appear at the IC(N) terminal 302.

A second important function of gate array circuit 292 is to receive signals from hardware modeling element 16 that are then routed to the workstation software for analysis. To accomplish this task, gate array circuit 292 is operable to provide a selectable load impedance 324 to IC(N) terminal 302. This feature is desirable if the output conductor of the hardware modeling element connected to IC(N) terminal 302 is, for example, an open collector or open emitter output terminal. Load impedance 324 is physically equal to IC(N
) terminal 302 and the ZS (N) terminal 326, and electrically connected to the gate array circuit 292 as follows.

A three-state detection and resistive load subcircuit 328 receives the pull-up signal at its input terminal 330 and
32 receives the test load signal (TSLD in FIG. 12).
A and TSLDB). These input terminals 330 and 33
2 drives the ZS (N) terminal 326 to one of three states. In particular, input terminals 330 and 332
The signal provided to the subcircuit 328 causes the tri-state driver 335 to output a "logic 0 state" or "
Logic 1 state” is driven to the ZS (N) terminal 326. The state of the three-state driver 335 is determined by its input terminal 333.
according to the logic state of the signal applied to it. Under these conditions, a signal applied to the C(N) input terminal 312 of the drive control circuit 306 disables the tristate driver 318 and presents a high impedance state to its output terminal 322. Therefore, logic 0 and logic 1 states provide logic voltage levels with a user-selected series impedance.

In the illustrated embodiment, the series impedance is 2.7
This is a typical case. Such resistors are preferably packaged in a single in-line package of ten or more resistors to save space. In addition, signals applied to input terminals 330 and 332 of subcircuit 328 can selectively disable tristate driver 335 and provide a high impedance state to ZS (N) terminal 326.

The capabilities described above allow gate array circuit 292 to operate to test whether a high impedance condition exists at IC(N) terminal 302. To perform this test, output terminal 322 of tri-state driver 318 is disabled to a high impedance state, and logic O and logic I states are sequentially applied to ZS (N) terminal 326. When IC(N) terminal 302 is high impedance, the logic state applied to ZS (N) terminal 326 appears at IC(N) terminal 302. Gate array circuit 2
92 indicates that the signal appearing at the IC(N) terminal 302 is 10(N
) is configured to appear on terminal 304.

The signals appearing at the 10(N) terminal 304 are examined by software and the logic O and logic I states, respectively, are ZS
When applied to the IC(N) terminal 326, it is determined whether a logic 0 state and a logic 1 state appear at the IC(N) terminal 302. A high impedance condition is known to exist at IC(N) terminal 302 if the driven and measured logic states match.

To protect the hardware from damage, gate array circuit 292 connects output terminal 322 of driver 318 to
is operable to determine whether a signal appearing at the IC(N) terminal 302 simultaneously appears at the IC(N) terminal 302 along with a signal applied by the hardware modeling element. Bus contention subcircuit 348 accomplishes this task by comparing the signal appearing at output terminal 316 of subcircuit 306 with the signal appearing at output terminal 322 of tristate driver 318 to determine whether they correspond. Bus contention subcircuit 348 issues an error signal at its output terminal 346 whenever a mismatch exists between the two signals. This is passed through tri-state driver subcircuit 350 to input terminal 352 of drive subcircuit 306, thereby disabling tri-state driver 318 into a high impedance state. Commanding tri-state driver 318 to a high impedance state prevents circuit failure, either in the hardware modeling elements or in the ICIP circuit. The error signal is also ■0 (N) terminal 30
4 and is sent to the user for display. The user reconfigures the control signals to the gate array to correct the problem.

The signal appearing at IC(N) terminal 302 also passes through bus connection circuit 348 and tri-state driver 350 to timing analyzer and memory circuit 34. The timing analyzer/memory circuit 34 is capable of handling IC (N
) A waveform analysis is performed on the signal appearing at the terminal 302. These signals are carried on line 356 to the gate array circuit (first
1) and is passed to the timing analyzer/memory circuit 34. The timing analyzer and memory circuit is 102
A 4-bit RAM memory is provided for each pin of the hardware modeling element being sampled. This RAM
The memory is written at a clock rate of 100M11z, which defines the logic state of the IC(N) terminal in the memory at each 10ns interval.

A 10 μs window of information about the signal appearing at IC(N) terminal 302 is thus stored. The information stored in the timing analyzer/memory circuit 34 can be read and displayed by the user. The user at this time is IC
(N) Determine the exact time sequence of signals applied to or received from terminal 302;

ICIF Gate Array φ The internal layout of a single ICIP gate array assembly 290 (FIG. 5) has 11 control input terminals, 32 data input terminals, 16 data output terminals, and 32 I
This shows that there are 10 data pins. ICIF
The functions of the control and data signals of gate array assembly 290 are as follows.

1,0(N) - Data input line used to control the driving strength of the IC(N) line.

2,0(N) - Data input line used to transfer data to the input terminal of the IC under evaluation.

3. RST” - System reset control input terminal places all resettable registers in a known state (7th
(also shown in the figure).

4. AO and AI - Address control input lines (also shown in Figure 8) used to set up the functionality of the gate array before performing simulations. Two bits from these lines can indicate one of four functions: loading the mode register, loading the clock enable register, and loading two different 3-state control registers. . The registers within ICIF gate array 110 are found as single bit storage blocks within the single gate array device of FIG. For example, the two three-state control registers are blocks U400 and U2O5 driven by lines TSLDA and TSLDII, respectively.

5. Read (active high)/write (active low) control input line used to select between setting up (write function) and reading out output values stored from an RW-IC simulation run. This validates the data on the gate array during testing of the system (also shown in Figure 8).

6. CS'' - Chip select control input function (also shown in Figure 8) that determines whether the gate array is enabled.

? , ToEN (or BTOEN) - Optionally a timing analyzer 34 is used to monitor the IC during stimulation.
The output of the timing analyzer (also shown in Figures 6.7 and 12) determines whether to probe or not.

8. FULL (or BFULL) - Control input terminal used to indicate the state of the ZS(N) pin during high impedance detection (also shown in Figures 7, 11 and 12).
.

9. DEV-CLK - Device clock control input used to clock the IC under test.

10. MAS-CLK-ICIF Mask clock control input terminal used to move simulation vectors between registers within the gate array structure.

11,1 CI-CLKI and ICI-CLK2 (abbreviation ICI-CIJ) - Vector clock control input terminals used to input control vectors and data vectors into ICIF gate array registers.

12. SAM-CLK--Sample clock control input terminal used to sample the resulting output of the IC under test by clocking data into a register.

13. ZS(N) - Data output terminal used to sense the tri-state output conductor on the IC under test. As mentioned above, a register is placed between each ZS (N) and IC (N).

14. IC(N) - Data input/output terminal used to connect the IC under test. The gate array is IC(N
) can be treated as an input terminal, output terminal, or clock terminal.

15. lo(N) - give data at setup,
Data input/output terminal used to provide a means to read sampled output data after running a simulation.

16° Eyror” - Control output line used to indicate bus contention error when in streaming mode.

Testing an IC with known terminal characteristics and timing specifications is done as follows. The first step is
The task is to define the function of each pin on the IC, set up the gate array, and treat it according to that definition. Figures 13-15 illustrate typical timing patterns for setup before testing, streaming during testing, and reading result data after testing. In all three cases, these timing diagrams show only one terminal of the gate array providing a signal to drive an IC input conductor or receiving a signal from an IC output conductor.

FIG. 13 shows the case where the gate array clocks the device pins in a positive pulsed mode. 1st
FIG. 4 shows the case where the gate array operates the device pins as data input terminals when no timing analysis is performed and no high impedance tests are performed. FIG. 15 illustrates the case where a gate array receives output signals from device pins using timing analysis and three-state testing.

The procedure for the other gate array terminals follows the same steps as for setup and readout, but the data and control signals are different.

FIG. 6 is a simple flow diagram that defines the logic paths taken by control circuit 24 when setting up a gate array block prior to simulation.

The steps in this flowchart are as follows.

Step l Start BRST (shown in FIGS. 5 and 7) is enabled and all internal registers of element gate array circuit 292 are cleared.

Step 2 Send clock to this block? - Status determination is performed at the clock level, and simply indicates whether or not the gate array circuit block receives arbitrary data in streaming mode. If the clock is not enabled by the CLKEN signal (described above for system mode operation of ICIF and shown in FIGS. 7 and 9), no data will be transferred to that block of gate array circuitry.

Step 3 Should I use a timing analyzer? - State determination is performed at the block level, and states whether or not to enable the driver associated with the block and connected to the timing analyzer/memory 34. Timing analysis for that block is enabled by the TOHN signal (shown in Figures 5.7 and 12).

Step 4 Select an IC word for testing. −
One word consists of a 16-bit slice of the gate array (corresponding to one gate array circuit assembly 290). -Sometimes one word set up. However, each bit within the word is predetermined and set up separately.

The following steps are performed separately for each gate array circuit 292.

Step 5 Does the 1C pin require a clock? - At any given time, an IC pin is either a data input terminal, a clock input terminal or a data output terminal.

If the pin is a clock pin, the gate array circuit 292 is set up and performs its function by the signal on the CFLD line (see Figure 8.12).

a. If the pin is a lock pin, then This is a pulse against IC device lock. (active edge removal reset) or non-active - Must be used in pulse mode do not have.

b. When using pulse mode, an additional selection must be made to determine whether to reset the clock line after a negative or positive edge of the device clock. Signals on the NPOL and PP0L lines (see Figures 7 and 12) indicate which is selected.

Step 6: Set error test? - This is useful if the user wants to prevent the hardware modeling device 10 and the IC under test from colliding due to accidental application of two or more drive signals to the bus during operation. 348). The bus contention enable signal is sent on line EJTTEN (see Figure 7.12).

Step 7a 7b Is it a 3-state test pin? - This is the I under test
Determine whether the output terminal of C should be treated as 3-state or whether it should be pulled up or pulled down.

a. If the pin is not tested with high impedance, treat it in a special way (e.g. oven collector output terminal) and may require a pull-up or pull-down resistor.

b. does not require special treatment; Do not test pins for high impedance. If the test driver is enable.

This is done as follows. TSLDA and TSLDB
A signal (Figure 8.12) loads two resistors indicating how the pin under test should be treated. These two resistors can be (1) always pulled up; (2) always pulled down; (3) three-state testable (i.e. can be dynamically pulled high and low with the BFULL signal); or (4)
Give four combinations corresponding to the floats.

These four options are illustrated by blocks 7a and 7b in FIG.

Step 8 Are all words completed? - Setup is complete if all words are set up.

ICIF Bi-dose on the door array.
'1 signal The "bit slice" gate array circuit of FIG.
One bit of CIF gate array 110 is shown.

(Input decoding and control logic has been omitted for clarity.) The complete ICIP interface 110 consists of two
Consists of 56 bit slices (1 per subassembly 290)
6 bit slice, ) 4 per lock 120-126
Subassembly 290, complete ICIP interface 11
4 blocks per 0). The control signals for ICIF bit slice gate array 292 are defined and explained below.

1. 8FULL - ZS during high impedance test
(N) Control line used to pull the output terminal high or low (shown in Figure 5.7).

2. TSLDA and TSLDB-ZS(N) are pulled up.

Three-state loads A and B (also shown in Figure 8) are used to determine whether to operate as a pull-down, high-Z test line, or nothing and to control the operation of ZS(N).
.

3. BRST - Buffered Reset Line (5th
As shown in the figure. In addition, a non-buffered configuration is shown in FIG. 7).

4. NPOL and PP0L - Negative or positive polarity is ignored unless pulse mode is used (also shown in Figure 7).

5,8PM - Buffered pulse mode sets pulse mode or non-pulse mode (also shown in Figure 7)
.

6. CFLD - Clock function load used to determine whether the bit slice is a clock pin or a data pin (also shown in Figure 8).

7. BVCLK - Buffered vector clock (also shown in Figure 9; unbuffered form is ICI-CLKI)
and ICI-CLK2).

8. BMCLK - Buffered Master Clock (
Also shown in FIG. The unbuffered form is MAS-CLK
).

9. BDCLK - Buffered device clock (also shown in Figure 9; unbuffered form is DEV-CL
K).

10. FERR-Force error forces bus contention error. It is used for medical purposes only (FERR is also shown in Figure 7).

11. EJTTEN - Enable bus contention error detection (also shown in Figure 7).

12. BEOEN - Buffered Error Output Enable (also shown in Figure 8).

13, 8TOEN - Buffered Timing Analyzer Option Enable (also shown in Figure 8).

14, 8 SOEN - Buffered Sample Output Enable (also shown in Figure 7).

15. BSCLK - Buffered Sample Clock (also shown in Figure 9).

16. BDCLKB - Buffered Device Clock Enable (also shown in Figure 9).

17,8IO(N) - (lower right corner) Connect with the circuit shown in FIG.

The following describes the individual bit slices 2 of the gate array.
This is an example of a mode in which the clock driver 92 is set up and works as a clock driver. The operation of this circuit will be explained in detail with reference to FIGS. 12 and 13.

This example assumes that the gate array has been sent all necessary lock signals determined during the setup procedure. In addition, the optional timing analyzer/memory circuit 34 is not used and is not included in the IC under test.
Assume that we want a clock that operates in positive polarity pulse mode.

Finally, assume that the IC pin is a clock pin and that flip-flop 0402 (FIG. 12) is loaded with a logic one. The time diagram of FIG. 13 shows the setup of the input signal to the clock pin at the bit slice level.

A. Enable the BRST signal, which clears all internal registers. When this happens, the IC(N) and ZS(N) terminals 302 and 306 are now in a high impedance state.

8. The bit slice is set up and clocked by loading the value 1 into the D input terminal of flip-flop 0402. This is B50EN = BTOE
This is done by setting N = O, thereby disabling output driver 1435. Data line T
o (N) Set 304 to logic 1 state and CFLD
Run for one cycle and load the value 10(N) = t into U2O5.

C1 Since the IC to be evaluated is an edge triggered device, it sets the BPM signal to a logic low state, which sets up NOR gates U409 and U410 to accept the polarity determination.

D, positive or negative polarity (NPOL and PP0L) signals are mutually exclusive when enabled, enabling NAND gate 0411 or NAND gate U412 to be active.

As shown, BPM, PP0L, logic O, NPO
L/Logic 1. These logic states enable U412. Loading a logic I state into flip-flop U402 presets flip-flop U405, which continuously enables IC(N) output tri-state driver U421. Therefore, IC(N) terminal 30
If the conductor of the hardware modeling element connected to 2 is to be treated as a clock pin, U2O5 must be loaded with a logic 1. If a logic 0 is loaded into the D input terminal of U4O2, IC(N) remains high impedance until a new instruction (C(N)·1) is loaded into input C(N) 312.

E, TSLD^ and TSLDB signals are loaded,
Therefore, flip-flops U400 and U2O5 are loaded with a logic zero state. In this case, ZS (N) terminal 3
26 remains in a high impedance state. This is because the clock pin should not be tested in a high impedance state.

F. Although not shown on the waveform diagram at this point, when using the error/bus contention circuit, it must be enabled. This example assumes that this is not used. Therefore, it will not be included in the explanation.

A description of bus contention error correction will be given later.

G. Bit slice gate array circuit 292 prepares to act as a clock driver when in streaming mode. The timing waveforms shown in FIG. 13 are indicated in the following order in the streaming mode.

1, C(N) and D(N) become valid, and in this example, the D(N) terminal 310 goes to a logic one state.

2.8 Use VCLK to transfer data to flip-flop U4
Latch into 03 and U2O5.

3. BMCIJ becomes active and data D(N)310
is moved to flip-flop υ406. If this is an input pin rather than a clock pin, then the data D (N
) is directly transferred to 1(N) 302. If it is a clock pin, the data will not reach IC(N). This delay allows leeway to set up data before the clock is enabled on the IC under test.

4. After the appropriate setup time for the data has elapsed, output BD(:LK) to activate the IC(N) terminal 302 corresponding to the clock pin. At this point, the pulse mode NOR data 1-IJ409 and Put U410 into operation. Call PP0L.0 and enable the center input terminal of NAND gate 0412. BRST
Immediately after , flip-flop U415 is reset and a logic 0 is output to the lower input terminal of NAND gate
put

As soon as BDCLK transitions to a logic one, data on the D input terminal of υ415 (which =1 in this example) is clocked into its Q output terminal. At the same time, BDCLKB changes to logic zero. This is because BOCLKB is the logical complement of BDCLK. At this point, the three input terminals to u412 are respectively 0 and 1.1 from the top. When BDCLK returns to logic 0, BDCLKB changes to logic 1, thereby setting all three input terminals of the NAND gate to 1. Flip-flop U415 is immediately reset;
This forces the Q output terminal to a logic zero. Logic 0 output is NAN
Propagates to the lower input terminal of the D gate and removes the reset from the flip-flop □. Thus, U415 is BDCLK
A selectable polarity clock follower circuit provides a simple asynchronous means of pulsing the output terminal of U415 by using only one rising edge, the rising edge of BDCLK. This process (steps 1-4)
The simulation in streaming mode is repeated as many times as necessary.

++, After each vector is transferred to the IC hardware modeling element under evaluation, the streaming control logic
Wait an appropriate amount of time before latching the resulting output into sample flip-flop υ430.

2. During read mode, B50EN is enabled and provides a valid output on line 10(N). Thus,
The sample taken in step H is read out. If the optional timing analyzer and memory 34 is used, BTOEN is enabled during the entire experiment. However, the exception is when reading, in which case it is disabled.

The timing waveforms for the other two cases, that is, the data input and output timing waveforms, are shown in the time diagrams of Figures 14 and 15, but the setup, streaming, and readout explanations are as follows for the clock input. This is very similar to what was discussed in .

The above discussion summarizes the setup of gate arrays for IC device evaluation.

This is possible by allowing the internal structure of the gate array to operate as an input driver, clock driver or output driver. The gate array bit slicing circuit diagram previously shown provides an explanation of this basic setup, streaming and follow-up mode. Sample timing diagrams and flowcharts are provided for three pin types to clarify the procedure.

The basic functions of a gate array in a gate array have already been discussed. However, two other corrections of the gate array bit slices have special importance.

The first special feature is high impedance (3-state) detection. A hardware modeling circuit can be used to determine whether the output pin of the IC under evaluation is in a high impedance (Hi-Z) state.

Referring to FIG. 12, the principle of high impedance test operation is that as long as the data driver U421 is in the old-Z mode and the device under test is capable of three-state outputs, the output terminals of the device under test are As long as it is in a high impedance state, test driver U416 can force node 302 into a logic 1 state or a logic 0 state.

The simulation is run twice, with the test driver driving a logic 0 and a logic 1 in sequence. Compare those results and check that the test driver has the IC(N) line 30
2, it is known that the pin was in the old -Z state.

A second gate array special function is used to correct bus contention during simulation. Referring to FIG. 16, potential bus contention occurs if IC(N) 302 is used as either a clock pin or a data input terminal for the IC under evaluation. If for some reason IC(N) is driven by both data driver 0421 and the IC itself, bus contention will occur and ICI
It may destroy the P-gate array or the circuit of the IC under evaluation. This bus competition problem is solved as follows.

Whenever the system is started, the IIR3T signal is enabled and clears flip-flop U428 of bus contention subcircuit 348. Assuming IC(N) 302 is intended as a data driver or clock driver pin, the signal appearing at the output of inverter U438 is a logic zero. This means that both input terminals of NAND game 0420 are in a logic 1 state, thereby enabling output driver U421.

The output of υ421 is applied to the input terminal of U423.
0423 is a Schmitt trigger buffer, IC(N
) Remove any noise present on line 302. U4
Assuming that the data on the input and output sides of 21 are the same, the output of exclusive NOR game 1-11424 will always be a logic one. εERR (forced error test)
The signal is in a logic zero state. Therefore, the signal appearing at the input of U421 passes through exclusive OR (OR) 0422 unchanged.

When bus contention occurs on IC(N) (for example, IC(N)
) is driven with logic 1 and the IC under evaluation is driven with logic 0, or vice versa), XNOR
Gate U424 provides a logic zero at its output terminal.

After propagating through NOR gate U426, BSCLK
As soon as the logic 1 is given, the flip-flop U428
0420, the inverted output of υ42B immediately sets the flip 7t] 7'U428 and disables the NAND gate 0420, thereby causing the 042
1 into 3-state mode. Therefore, further bus disruption is prevented.

The error line indicates that bus contention has been detected.

The circuit shown in FIG. 16 can be disabled by changing the EJTTEN signal to a logic one state. In that case, the gate array can operate without error detection.

Analyzing a single bit slice of a gate array, a complete one can be created by simply connecting the bit slice with appropriate front-end decoding and multiplexing.
It can be seen that a 6-bit gate array assembly 290 is produced. Figures 7-10 show the remaining circuitry, which includes the interface logic necessary to create a complete gate array and the logic circuitry common to each of the 16-bit slices (lines Nc31, NC23, MRLD). , XE
(N) and XO(N) serve to interconnect the circuits of Figures 7-10).

While the principles of the invention have been illustrated with reference to the preferred embodiments, it will be apparent to those skilled in the art that modifications may be made in arrangement and detail without departing from such principles. We claim as the invention all such modifications as come within the scope and true spirit of the appended claims.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the entire hardware modeling circuit and system according to the present invention, FIG. 2 is a block diagram of a control circuit used in the hardware modeling circuit of the system of FIG. 1, and FIG. FIG. 4 is a time diagram of a two-vector data stream processed by the system of FIG. 1; FIG. 4 is a simplified block diagram of a plurality of gate arrays used in the integrated circuit interface of the hardware modeling circuit of FIG. 1; Figure 6 shows a block diagram of a single integrated circuit interface gate array assembly; Figure 6 shows a microprocessor in the control circuit of Figure 2 for the purpose of initializing the integrated circuit interface and processing data for simulation evaluation; 7 is a schematic diagram of an electrical circuit of a part of the integrated circuit interface of FIG. 1; FIG. 8 is a schematic diagram of an electrical circuit of another part of the integrated circuit interface of FIG. 1; 9 is a schematic diagram of an electrical circuit of yet another portion of the integrated circuit interface of FIG. 1; FIG. 10 is a schematic diagram of an electrical circuit of another portion of the integrated circuit interface of FIG. 1; FIG. , a block diagram of a single gate array circuit used to transfer signals to and from a single pin of a hardware modeling element. The schematic diagram of the circuit, FIG. 13, is a time diagram of the signals applied to the hardware modeling element when coupling the clock pin of the hardware modeling element to the gate array circuit of FIG. (can be treated as a clock pin depending on the mode). Figure 14 is a time diagram of signals applied to the gate array circuit when data is flowing from the operating memory of the hardware modeling circuit of Figure 1 to the gate array circuit of Figure 12 during evaluation, and Figure 15 is a time diagram of signals applied to the gate array circuit of Figure 12. , FIG. 16 is a time diagram of the signals applied to the gate array circuit when reading the resulting data from the pins accessed by the gate array circuit of FIG. 12, and FIG. 16 is the bus connection of the gate array circuit of FIG. 12. 17A to 17E are flowcharts for explaining the operation of the network interface of the system of FIG. 1; FIG. 18 is a schematic diagram of the electrical circuitry of the system of FIG. Time diagram when transferring 4 vectors to hardware modeling element. FIG. 19 is a time diagram when transferring two double vectors to a 256-pin hardware modeling element by the system of FIG. 1 during evaluation. 10...Hardware modeling circuit 12...Network interface 14...Simulation workstation 16...Integrated circuit element 18...Printed circuit board or circuit subsystem 20,
71.128.130.132.134.136.13
8.140°142, 144,146.148.150
．． 152.154.156.158°190, 192.
194. 196.206.356...Line 24
... Control circuit 26 ... User memory 27 ... Virtual disk file 28 ... Operating memory 30 ... Integrated circuit interface (ICIP) 32
... Input port 34 ... Timing analyzer/timing memory circuit 36 ... Multipath adapter 38° System data (SYS-KAT) bus 40
...System address (SYS-ADD) bus 42.
...System control (SYS-CTRL) bus 44...
Stream clock bus 48...Streaming address bus 50...VEC-DAT bus 52...Timing (TIM) bus 56...Clock circuit 58...Clock parameter register 60...High frequency clock generation device 62... reference clock generator 64... device clock generator 66... streaming control clock sequencer 68
...Streaming clock time alignment circuit 70...
Microprocessor 72...Program memory 74...Access and direct memory access (DAM) circuit 75...Vector counter 76...I-reaming address circuit 77...System bus 110...Gate array 120 , 122.124.126...Gate array block 160...Address decoding circuit 198, 200...Output bus 202...Transceiver circuit 290...Gate array circuit assembly 292...Gate array circuit 302 ...IC(N) terminal 304...10(N) terminal 306...Clock and data drive subcircuit 308, 3
14.320.330.332.333.532...
Input terminal 310...D(N) input terminal 312...C(N) input terminal 316, 322.346...Output terminal 318, 335
...3-state driver 324...Load impedance 326...ZS(N) circuit 328...3-state detection and resistive load subcircuit 331...
...Enable Output Line 348...Bus Competition Subcircuit 350...Three-state Driver Subcircuit Claim Applicant: Menthol Graphics Corporation FORN:=OTo +5 匡

Claims (1)

[Claims] 1. In a simulation system comprising a plurality of workstations for independently and simultaneously simulating the response of an electronic circuit to applied test data, the circuit elements in the electronic circuit are Determines the response of multi-pin circuit elements by evaluating the behavior of real circuit elements in a hardware modeling system based on the corresponding workstation's perception of the actual circuit elements as being simulated. A simulating hardware modeling system comprising: input means for receiving input test data from a workstation; and stimulus signal generation means coupled to the input means for converting the input test data into an evaluation stimulus corresponding to the input test data. and application means coupled to the stimulus signal generating means for applying an evaluation stimulus to the actual circuit element, the output signal being generated by the actual circuit element in response to the applied evaluation stimulus, result test data recovery means coupled to the circuit element for receiving the output signal from the actual circuit element and converting the output signal into resultant test data; and coupled to the recovery means for receiving the resultant test data. hardware modeling circuitry comprising: output means; network interface means for coupling a plurality of workstations to the hardware modeling circuitry such that the hardware modeling circuitry can be accessed simultaneously by each workstation; The network interface means couples the workstation to the input means and receives input test data from the workstation based on the recognition that a multi-pin circuit element is being stimulated at the workstation that corresponds to an actual circuit element within the hardware modeling system. The network interface means also comprises means for coupling the output means to the workstation and, following completion of the simulation, for transmitting the resulting test data from the output means to the workstation, so that the network interface means a network interface means comprising: means for interfacing a workstation to the hardware modeling circuitry to permit partitioning of the hardware modeling circuitry among the workstations for simultaneous circuit simulation by the stations; system. 2. comprising a plurality of hardware modeling circuit means;
said network interface means comprising means for interfacing a workstation to a plurality of such hardware modeling circuitry means to permit partitioning of said plurality of hardware modeling circuitry means among said plurality of workstations; A hardware modeling system according to claim 1. 3. The hardware modeling circuit means comprises a plurality of integrated circuit interface means and input/output port means for coupling to the actual circuit elements, the integrated circuit interface means and the input/output port means being coupled to the input means. a stimulus signal generating means for receiving input test data and generating an evaluation stimulus corresponding to the input test data; an applying means coupled to the stimulus signal generating means for applying an evaluation stimulus to the actual circuit element; 2. The hardware modeling system of claim 1, further comprising recovery means coupled to receive an output signal generated by the actual circuit element in response to an evaluation stimulus from the actual circuit element. 4. a first semiconductor memory circuit operable at a first speed to store input test data for use in multiple simulations; a second semiconductor memory circuit capable of operating at a first speed for storing input test data for use in a single simulation; a second semiconductor memory circuit capable of operating at speeds of; means for transferring input test data from the first semiconductor memory circuit to the second semiconductor memory circuit for use in a single simulation; and means for transferring input test data from the second semiconductor memory circuit to the second semiconductor memory circuit; 2. The hardware modeling system according to claim 1, further comprising: means for transferring input test data of the signal generating means. 5. A number of different multi-pin hardware modeling elements used to simulate the performance of the electronic circuit corresponding to input test data, converting this input test data into evaluation stimuli, and converting this evaluation stimulus into hardware modeling elements. means for applying the output signal to the selected output pin of the hardware modeling element; and means for retrieving the output signal from the selected output pin of the hardware modeling element and converting the output signal to resultant test data; timing analyzer circuit means for periodically sampling and overtime providing a timing indication of the resulting data on the output pin; and means for selectively coupling the timing analyzer circuit means to the output pin for providing a timing indication. Hardware modeling system. 6. user memory means for storing input test data for one or more simulations; operating memory means for storing input test data for only one simulation; simulating input test data from the operating memory means; means for converting input test data from the operating memory means for the previous simulation into test data; 6. The hardware modeling system of claim 5, further comprising: means for transferring input test data for simulation. 7. The evaluation stimulus and clocking signal corresponding to the data signal cause an output signal from the output pin of the hardware modeling element to cause the simulation to occur.
In addition to the pins of a number of different multi-pin hardware modeling elements used in circuit simulation: having multiple circuit pin connections, each such pin connection connecting to a single associated pin of the hardware modeling element. gating circuit means for the connection; means for selecting any pin connection as an input data pin connection; and means for forwarding a test stimulus to the input data pin connection and thereby applying the test to the associated pin of the hardware modeling element. means for transferring a stimulus; means for selecting an arbitrary pin connection as a clock pin connection; means for transferring a clocking signal to a clock pin connection and thereby to an associated pin of a hardware modeling element; A hardware modeling apparatus comprising: means for selecting any pin connection as a data connection; and means for receiving output data from an output data connection, thereby receiving output data from an associated pin of a hardware modeling element. 8. Gating circuit means comprising any pin connection and means for selectively applying a signal varying between logic 0, logic 1, or high impedance to the associated pin. The described hardware modeling device. 9. Hardware modeling apparatus according to claim 7, characterized in that it comprises gating circuit means with arbitrary pin connections and means for selectively applying pull-up or pull-down loads to the associated pins. . 10. The method according to claim 1, further comprising means for selectively applying a clock signal to any pin of the actual circuit element, and also comprising means for adjusting the phase, duty cycle and frequency of the applied clock signal. A hardware modeling system according to scope 7. 11. A plurality of evaluation stimuli corresponding to data signals and clocking signals corresponding to elements in the circuit being simulated so as to produce output signals from output pins of the hardware modeling element for use in circuit simulation. A hardware modeling system for applying pins of a hardware modeling element to a pin of the hardware modeling element, the system comprising: a plurality of circuit pin connections, each such pin connection for connection to a single associated pin of the hardware modeling element; means for selecting an arbitrary pin connection as an input data pin connection; and means for transferring a test stimulus to the input data pin connection, thereby applying a test stimulus to the associated pin of the hardware modeling element. means for transferring; means for selecting an arbitrary pin connection as a clock pin connection; means for transferring a clocking signal to the clock pin connection and thereby to the associated pin of the hardware modeling element; as an output data connection; means for selecting any pin connection; and means for receiving output data from an output data connection, thereby receiving output data from an associated pin of the hardware modeling element, further comprising: means for selecting any such pin connection; If the same pin connection is driven to one state by a signal from a hardware modeling element while being driven to one state by a signal from a A hardware modeling system including bus contention detection means for disabling at least one of the applied drive signals. 12. The hardware modeling system of claim 11 including timing analyzer means selectively coupled to the output pin connections for timing analysis of output signals received from associated pins. 13. clocking means for applying a clocking signal to the clocking pin connections, such clocking means comprising means for varying the frequency, duty cycle and phase of the clocking signal applied to each such clocking pin connection; The hardware modeling system according to claim 11. 14. Simulating the response of at least one multi-pin circuit element in an electronic circuit being simulated at the workstation by evaluating the behavior of the actual multi-pin circuit element in response to test data from the workstation. for: memory means for receiving and storing input test data from the workstation; circuit interface means for coupling to the actual circuit elements, the circuit interface means for receiving input test data from the memory means; a stimulus signal generating means for generating an evaluation stimulus corresponding to the input test data; an application means for applying the evaluation stimulus to the actual circuit element; a result test data collection means coupled to the actual circuit element for receiving the output signal from the actual circuit element and converting the received output signal into result test data. circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means and comprising means coupled to the result test data retrieval means for receiving and storing the result test data; control the application of an evaluation stimulus to the circuit elements of the circuit element, control the reception of the output signal by the result test data collection means and the conversion of the output signal into result test data, and further control the transfer of the result test data to the memory means. control circuit means coupled to the memory means and the circuit interface means for controlling return of resultant test data from the memory means to the workstation, the memory means comprising: first memory means for receiving and storing input test data from the workstation for a plurality of circuit simulations; and second memory means for receiving input test data from the first memory means for a single simulation. control circuit means for controlling the transfer of input test data from the second memory means to the circuit interface means for simulation, and after transfer from the second memory means to the circuit interface means; A hardware modeling system comprising means for controlling the transfer of input test data from a first memory means to a second memory means for one simulation. 15. Hardware modeling according to claim 14, characterized in that the control circuit means comprises means for controlling the transfer of resultant test data from the resultant test data collection means to the first memory means. system. 16. The hardware modeling system of claim 14, wherein the first and second memory means include semiconductor memory means. 17. The hardware modeling system according to claim 16, wherein the second semiconductor memory circuit can be accessed faster than the first semiconductor memory circuit. 18. The hardware modeling system of claim 14, wherein the first memory means operates at a first speed and the second memory means operates at a second speed greater than the first speed. 19. The control circuit means includes device clock means for generating a device clock signal for clocking the actual circuit elements, the control circuit means also detecting the rising and falling edges of the device clock signal with respect to the evaluation stimulus and therefore with respect to the input test data. 15. The hardware modeling system of claim 14, including means for selectively positioning. 20. The hardware modeling system of claim 14, wherein said second memory means has a total pattern depth available for each circuit element during simulations using the circuit elements. 21. Simulating the response of at least one multi-pin circuit element in an electronic circuit being simulated at the workstation by evaluating the behavior of the actual multi-pin circuit element in response to test data from the workstation. for: memory means for receiving and storing input test data from the workstation; circuit interface means for coupling to the actual circuit elements, the circuit interface means for receiving input test data from the memory means; a stimulus signal generating means for generating an evaluation stimulus corresponding to the input test data; an application means for applying the evaluation stimulus to the actual circuit element; a result test data collection means coupled to the actual circuit element for receiving the output signal from the actual circuit element and converting the received output signal into result test data. circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means and comprising means coupled to the result test data retrieval means for receiving and storing the result test data; control the application of an evaluation stimulus to the circuit elements of the circuit element, control the reception of the output signal by the result test data collection means and the conversion of the output signal into result test data, and further control the transfer of the result test data to the memory means. control circuit means coupled to the memory means and the circuit interface means for controlling return of resultant test data from the memory means to the workstation, the memory means comprising: first memory means for receiving and storing input test data from the workstation for a plurality of circuit simulations; and second memory means for receiving input test data from the first memory means for a single simulation. control circuit means for controlling the transfer of input test data from the second memory means to the circuit interface means for simulation, and after transfer from the second memory means to the circuit interface means; means for controlling the transfer of input test data from the first memory means to the second memory means for one simulation, the memory means further comprising third auxiliary disk memory means serving as a virtual memory means. A hardware modeling system comprising: a hardware modeling apparatus comprising means for swapping input test data from the first memory means to the third memory means and from the third memory means to the first memory means. 22. Timing analyzer and memory circuit means is selectively coupled to the result test data retrieval means for receiving the result test data, and the control circuit means always provides a timing analyzer and memory circuit means to provide a representation of such result test data. 22. The hardware modeling system of claim 21, further comprising means for periodically transferring the resulting test data to the analyzer/memory circuit means. 23. The control circuit means comprises means for applying a timing analysis clocking signal to the timing analyzer and memory circuit means so as to transfer resultant test data in response to the timing analysis clocking signal. A hardware modeling system according to scope 22. 24, comprising high impedance testing means for determining whether a pin of one of the actual circuit elements is in a high impedance state, the high impedance testing means applying a logic high signal and a logic low signal to the pin; 22. The hardware modeling system of claim 21, further comprising means for evaluating whether the pin is pulled to a logic high state and a logic low state in response to a signal applied to the pin. 25. The hardware modeling system of claim 21, wherein the first memory means operates at a first speed and the second memory means operates at a second speed greater than the first speed. 26. Simulating the response of at least one multi-pin circuit element in an electronic circuit being simulated at the workstation by evaluating the behavior of the actual multi-pin circuit element in response to test data from the workstation. for: memory means for receiving and storing input test data from the workstation; circuit interface means for coupling to the actual circuit elements, the circuit interface means for receiving input test data from the memory means; a stimulus signal generating means for generating an evaluation stimulus corresponding to the input test data; an application means for applying the evaluation stimulus to the actual circuit element; a result test data collection means coupled to the actual circuit element for receiving the output signal from the actual circuit element and converting the received output signal into result test data. circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means and comprising means coupled to the result test data retrieval means for receiving and storing the result test data; control the application of an evaluation stimulus to the circuit elements of the circuit element, control the reception of the output signal by the result test data collection means and the conversion of the output signal into result test data, and further control the transfer of the result test data to the memory means. a hardware modeling system comprising: control circuit means coupled to the memory means and the circuit interface means for controlling return of resultant test data from the memory means to the workstation; , a first clock means for clocking a first set of input test data from the memory means to the circuit interface means, and a second clock means for clocking a second set of input test data from the memory means to the circuit interface means. and means for clocking the stimulus signal generating means after the transfer of the first and second sets of input test data, thereby controlling generation of an evaluation stimulus corresponding to both the first and second sets of input test data. A hardware modeling system comprising a master clock means for generating a master clock signal for clocking the actual circuit elements, and a device clock means for generating a device clock signal for clocking the actual circuit elements. 27. The hardware modeling system of claim 26, wherein the control circuit means includes means for selectively positioning rising edges and falling edges of the device clock signal relative to the master clock signal. 28. Simulating the response of at least one multi-pin circuit element in an electronic circuit being simulated at the workstation by evaluating the behavior of the actual multi-pin circuit element in response to test data from the workstation. for: memory means for receiving and storing input test data from the workstation; circuit interface means for coupling to the actual circuit elements, the circuit interface means for receiving and storing input test data from the memory means; a stimulus signal generating means for generating an evaluation stimulus corresponding to the input test data; an application means for applying the evaluation stimulus to the actual circuit element; a result test data collection means coupled to the actual circuit element for receiving the output signal from the actual circuit element and converting the received output signal into result test data. circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means and comprising means coupled to the result test data retrieval means for receiving and storing the result test data; control the application of an evaluation stimulus to the circuit elements of the circuit element, control the reception of the output signal by the result test data collection means and the conversion of the output signal into result test data, and further control the transfer of the result test data to the memory means. control circuit means coupled to the memory means and the circuit interface means for controlling return of resultant test data from the memory means to the workstation; Bus contention occurs based on the application of a drive signal by the application means to such pin of the real circuit element simultaneously with the occurrence of an output drive signal at one pin of the real circuit element in response to an evaluation stimulus, and the bus contention A hardware modeling system comprising a bus competition means for detecting. 29. The bus contention means converts the drive signal applied to such pin by the application means into a high impedance signal upon detection of bus contention at such pin, thereby reducing the risk of damage resulting from bus contention. 29. The hardware modeling system according to claim 28, further comprising means for reducing the nuisance. 30. An actual multi-pin hardware circuit element is used for simulation: storing test data for multiple simulations in a first memory; transferring test data for a single simulation from the first memory to a second memory; transferring data; applying test data for a single simulation from a second memory to one actual hardware circuit element to provide resultant test data from the circuit element; and one actual hardware circuit element; transferring test data for a single simulation sequentially from a first memory to a second memory after adding test data for a previous single simulation to a hardware modeling element of the electronic circuit; Simulation method. 31. When test data is applied to a real circuit element during simulation, sampling the output signal from the output pin of this real circuit element, thereby representing the output signal at the sampled output pin during simulation. 31. The electronic circuit simulation method according to claim 30, further comprising: 32, transferring the test data from the first memory to the second memory at a first rate; and transferring the test data from the second memory to the actual hardware circuitry at a second rate higher than the first rate; 31. The electronic circuit simulation method according to claim 30, further comprising the step of applying a voltage. 33. In a simulation system with multiple workstations for simulating the response of an electronic circuit to applied test data, circuit elements in the electronic circuit correspond to actual circuit elements in the hardware modeling system. A hardware modeling system for simulating the response of at least one multi-pin circuit element by evaluating the behavior of the actual circuit element based on the workstation's perception that it is being simulated at the workstation. comprising: input means for receiving input test data from a workstation; stimulus signal generation means coupled to the input means for converting the input test data into an evaluation stimulus corresponding to the input test data; and the stimulus signal generation means. application means for applying an evaluation stimulus to the actual circuit element, the output signal being generated by the actual circuit element in response to the applied evaluation stimulus; Hardware comprising a result test data recovery means for receiving the output signal from the actual circuit element and converting the output signal into resultant test data, and an output means coupled to the recovery means for receiving the resultant test data. hardware modeling circuitry; network interface means for coupling a plurality of workstations to the hardware modeling circuitry such that the hardware modeling circuitry is accessible by each workstation, the network interface means having an input means for coupling the workstation to the means for transferring input test data from the workstation to the input means based on the recognition that a multi-pin circuit element is being stimulated at the workstation corresponding to an actual circuit element within the hardware modeling system; , the network interface means also comprising means for coupling the output means to the workstation and transferring the resulting test data from the output means to the workstation following completion of the simulation, so that hardware modeling between the workstations is possible. network interface means including means for interfacing a workstation to the hardware modeling circuit means to permit partitioning of the circuit means; further comprising: one or more simulation inputs; user memory means for storing test data; operating memory means for storing input test data for only one simulation; means for applying input test data from said operating memory means to said means for converting test data during a simulation; means for transferring input test data for a single simulation from the user memory means to the operating memory means subsequent to application of input test data for a previous simulation to the means for converting the test data from the operating memory means; Equipped with a hardware modeling system. 34, the means for transferring input test data from the user memory means to the operating memory means includes means for transferring such input test data at a first rate; and the means for applying input test data from the operating means includes means for transferring such input test data at a first rate; Claim 33 further comprising means for applying input test data at a second rate greater than the first rate.
Hardware modeling system described in section. 35, a third auxiliary disk memory means operating as a virtual memory means, wherein the hardware modeling circuit means transfers data from the first memory means to the third memory means such that the first memory means is filled with input test data; to and third
34. The hardware modeling system of claim 33, further comprising means for swapping input test data from the first memory means to the first memory means. 36. The hardware modeling system of claim 34, wherein the operating memory means has a total pattern depth available for each circuit element during simulations using the circuit elements. 37. a plurality of workstations capable of individually performing circuit evaluation of a variety of circuits, the evaluation of which includes at least a portion of a software simulation of the circuit under evaluation at each workstation; hardware modeling circuit means including at least one actual circuit element, the hardware modeling circuit means including means for allowing divided access to the actual circuit element by a plurality of workstations;
Furthermore, if such elements appear in a circuit being evaluated by multiple workstations, the hardware modeling circuit means includes means for simultaneously performing circuit evaluation by multiple workstations using actual circuit elements for evaluation. A hardware modeling system comprising; 38. The hardware modeling system of claim 37, wherein the hardware modeling circuit means comprises a plurality of actual circuit elements.