JPH01158568A - Multiplying circuit - Google Patents

Abstract

PURPOSE:To compose the title device of small hardware quantity and to make the manufacturing price inexpensive when the device is made into an integrated circuit by equipping the device with a specific first circuit and a specific second circuit. CONSTITUTION:A multiplicand holding/base-fold calculating circuit 10 holds the respective coefficient values of multiplicands in a period in which a resetting signal is supplied, successively calculates values obtained by base-multiplying the respective coefficient values synchronously with a clock signal, and supplies the calculated values to a multiplier inputting and multiplying circuit 11 in parallel. The multiplier inputting and multiplying circuit 11 calculates the product of a multiplier and the coefficient value for the respective coefficient values to be supplied in parallel and temporarily holds the calculated result. Next, the circuit 11 calculates the product of the coefficient value of a next multiplicand and the coefficient value of a next multiplier, calculates the sum of the calculated result and the last calculated result which is previously held, and holds the summed result. The circuit 11 obtains a final multiplied result after repeating the calculation of this kind for the necessary number of times. Thus, since one part of hardware is used repeatedly, the hardware quantity can be reduced widely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) This invention relates to a finite field multiplication circuit, and particularly to a multiplication circuit used in a sign operation processing circuit.

(Prior Art) When multiplying multiple-order irreducible polynomials using hardware, conventionally, as shown in the block diagram of FIG. 6, a multiplicand and a multiplier are supplied to a polynomial product coefficient calculation circuit 50. A multiplication result is obtained by calculating a polynomial product coefficient and further supplying this polynomial product coefficient to a polynomial division circuit 51.

However, in the case of multiplication using such hardware, all bits of the multiplicand and multiplier are supplied at the same time, so as the number of bits of the multiplicand and multiplier increases, the amount of hardware increases to the square of the number of bits. The problem is that it increases in proportion to. For this reason, the conventional circuit has the disadvantage that the chip area becomes large when integrated into a circuit, and the cost becomes high.

(Problems to be Solved by the Invention) As described above, conventional multiplication circuits require a large amount of hardware, and when integrated into a circuit, the chip area becomes large and the manufacturing cost of the chip increases. be.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to reduce the manufacturing cost of chips when integrated circuits are constructed with a small amount of hardware. The purpose of this invention is to provide a multiplication circuit that can do the following.

[Structure of the Invention] (Means for Solving the Problems) The multiplication circuit of the present invention includes a first circuit that holds each coefficient value of a multiplicand A and generates a value obtained by sequentially multiplying the coefficient values by a base, and a multiplier are sequentially supplied, and this coefficient value and the first
It calculates and holds the product of the value generated by the first circuit, and also calculates the product of this coefficient value and the value generated by the first circuit when a different coefficient value of the multiplier B is supplied. , a second circuit that calculates the sum of this calculation result and a pre-held calculation result, and after the final coefficient value of the multiplier B is supplied to the second circuit, the second circuit The present invention is characterized in that the sum value calculated in is output as the multiplication result.

(Operation) Each coefficient value of the multiplicand is supplied at once at the beginning, and values obtained by multiplying each coefficient value by the base are sequentially generated. For each coefficient value of the base multiplied multiplicand, the product with some coefficient values of the multiplier is calculated,
By sequentially accumulating these products, a multiplication result is finally obtained.

According to such a multiplication circuit, some of the hardware is used repeatedly, so the amount of hardware is significantly reduced compared to the conventional case where all bits of the multiplicand and multiplier are supplied at the same time. can be reduced to

(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a multiplication circuit according to the present invention. The multiplicand holding/base multiplication circuit 10 holds each coefficient value of a multiplicand consisting of a plurality of bits while a reset signal is supplied. Thereafter, base multiplied values of each of these coefficient values are sequentially calculated in synchronization with a clock signal (not shown).

Each coefficient value of the multiplicand calculated each time by the multiplicand holding/base multiplication circuit IO is supplied in parallel to the multiplier input multiplication circuit 11. Coefficient values of a multiplier consisting of a plurality of bits are input to this multiplier input multiplication circuit 11 one part at a time, for example, one bit at a time. Then, the multiplier input multiplication circuit 11 calculates the product of each coefficient value of the multiplicand supplied in parallel from the multiplicand holding/base multiplication circuit IO with the coefficient value of the multiplier, and temporarily holds the calculation result. . Next, multiplier input multiplication circuit 1
1 calculates the product of the coefficient value of the next multiplicand supplied from the multiplicand holding/base multiplier calculation circuit IO and the coefficient value next to the multiplier. Then, the sum of the calculation result and the previous product calculation result held in advance is calculated and held as a new result. By repeating such calculations as many times as necessary, the multiplier input multiplication circuit 11 obtains the final multiplication result.

FIG. 2 is a circuit diagram specifically showing the embodiment circuit of FIG. 1 above. Note that the multiplier circuit in FIG.
) is multiplied by the multiplicand and the multiplier by supplying the coefficient of the multiplier one bit at a time. In this case, x8+x4+x3+x2+IIM of CF(28)
Based on the solution α of O (1, α, α2.α3.α4.α5.α
6. α7) as the basis coefficient field GF (2)-(0,1
Take 1. Note that the above equation may be any 8th degree irreducible polynomial on GF (2), and here, for example, the multiplicand A is a. +a1α+a2 a2+-・
+a7 a7, multiplier B b□ +bl aIb2α2+
. . +b7α7, and the case where both are multiplied will be explained as an example.

The multiplicand holding/base multiplication circuit IO is composed of eight selection/holding circuits 120-127 and three 2-bit exclusive OR circuits 132, 133, and 134.

The eight selection/holding circuits 12 each select a coefficient aO+ aI + a2 + . . . for each bit of the multiplicand A.
This is to hold the coefficient of each of a7 or its base multiplied value. In these eight selection/holding circuits 12, carry-out from the previous stage is basically sequentially supplied as carry-in to the latter stage, and carry-out from the selection/holding circuit 127 at the final stage is supplied to the selection/holding circuit 12. Supplied as a carry-in. A selection/holding circuit 12 that holds the coefficient a of the term α. The carry-out is supplied to the subsequent stage selection/holding circuit 122 via the exclusive OR circuit 132, and the other input of the exclusive OR circuit 132 is supplied to the final stage selection/holding circuit 1.
A carryout of 27 is provided. Coefficient a of α2 term
The carry-out of the selection/holding circuit 122 holding 2 is supplied to the subsequent selection/holding circuit 123 via the exclusive OR circuit 133, and the other input of the exclusive OR circuit 133 is the final stage selection/holding circuit 1.
A carryout of 27 is provided. Further, the carry-out of the selection/holding circuit 123 holding the coefficient a3 of the α3 term is supplied to the subsequent selection/holding circuit 124 via the exclusive OR circuit 134, so that the exclusive logic The other input of the summation circuit 134 is supplied with the carryout of the selection/holding circuit 127 at the final stage. Further, a reset signal is supplied to each selection/holding circuit 12 as a selection control signal.

In the multiplicand holding/base multiplication circuit 1O having such a configuration, during the reset period when the reset signal is at the "1" level, the coefficients ao+al+a2 . ...a
7 are selected by each selection/holding circuit 12, and then held in synchronization with a clock signal. After the reset signal becomes "0 level" and the reset period ends, the coefficient values held in each selection/holding circuit 12 are sequentially transferred to the subsequent stage in synchronization with the clock signal. The processing is repeated for one clock period, and each coefficient value is sequentially multiplied by α.

The multiplier input multiplication circuit 11 consists of a part that calculates a 1-bit product and a part that calculates a 1-bit sum.
Sum calculation circuit 14. 147, and eight holding circuits 15o to 157, each holding a 1-bit value. The eight product/sum calculating circuits 14o to 147 have coefficients bo, bl, b2 . ...
b7 are sequentially supplied one bit at a time, and the coefficient of each bit of this multiplier B and the multiplier A held in each selection/holding circuit 12 in the wave multiplier holding/base multiplier calculation circuit IO, The product of each coefficient value or its multiple is calculated. The calculation results of the eight product/sum calculation circuits 14 are supplied in parallel to eight holding circuits 15, where they are temporarily held. Further, the calculation results held in each of the eight holding circuits 15 are returned to the product/sum calculation circuit 14,
After the product of the coefficient of the next bit of the multiplier B and each coefficient value of the base multiplied multiplier A held in each selection/hold circuit I2 in the multiplicand preservation/base multiplication calculation circuit IO is calculated, It is added to the calculation result, and is again supplied in parallel to eight holding circuits 15 and held.

In the multiplier input multiplier circuit 11 having such a configuration, the reset signal is set to "8 hold circuits 15 during the reset period of 1 level".
The retained contents of are cleared. Then, the coefficient of each bit of the multiplier B is calculated. +') I+ b2+...b7 Each time each is supplied, the product/sum calculation circuit 14 calculates b1XAXa'
(i=o, 1, 2.-7) is calculated, followed by an accumulation with the previous result, and 8 of the clock signal.
After a clock period has elapsed, the contents held in the eight holding circuits 15 are multiplied and output.

As described above, according to the circuit of the above embodiment, it is possible to perform multiplication between 8th order irreducible polynomials. Moreover, since the same hardware is used repeatedly, the amount of hardware is approximately proportional to the number of bits in the multiplicand and multiplier, and multiplication is performed by inputting the multiplicand and multiplier at the same time as in the past. The amount of hardware can be significantly reduced compared to the previous case. As a result, when this multiplication circuit is integrated into an integrated circuit, it is possible to reduce the size of the chip, thereby reducing the manufacturing cost of the chip.

FIG. 3 is a circuit diagram showing an example of a detailed configuration of the selection/holding circuit 12 in the circuit shown in FIG. 2. In FIG. This selection/holding circuit is composed of a selector 21 and a latch circuit 22. A reset signal is supplied to the selector 21 as a selection control signal, and during the reset period when this signal is at the "1" level, the coefficient value data of the corresponding term of the multiplicand is selected, and the reset signal is Carry-in from the previous stage is selected during the period when is set to the "0" level. The data selected by the selector 21 is supplied to the latch circuit 22. This latch circuit 22 includes a clocked inverter 23 that inverts the selection data from the selector 21 at the timing of the clock signal f, an inverter 24 that inverts the output thereof, and an inverter 24 that is connected in antiparallel to the inverter 24 and is connected to the clock signal φ. Inverter 2 at the timing
A clocked inverter that inverts the output data of 4 and 25
It is composed of. Then, the output data of the latch circuit 22 is supplied to the subsequent selection/holding circuit 12 as a carry-out, and is also supplied to the product/sum calculation circuit 14.

FIG. 4 is a circuit diagram showing an example of a detailed configuration of the product/sum calculating circuit 14 in the circuit shown in FIG. 2. In FIG. This product/sum calculation circuit includes an AND gate circuit 26 that calculates the product, and the product calculated by the AND gate circuit 26 and the holding circuit 1.
5 and a 2-bit exclusive OR circuit (EX-OR) 27 which performs addition with the accumulated value held at 5.

FIG. 5 is a circuit diagram showing an example of a detailed configuration of the holding circuit 15 in the circuit shown in FIG. 2. In FIG. This holding circuit includes a latch circuit 28 configured similarly to the latch circuit 22 in FIG. 3, and a latch circuit in which a clocked inverter 29 is provided in place of the inverter 24 in the latch circuit 22 in FIG. 30, N-channel MOS for clearing) It is composed of a transistor 31 and an inverter 32. Here, one latch circuit 28 takes in data from the product/sum calculation circuit 14 at the timing of the clock signal φ, and holds it at the timing of the clock signal f. The other latch circuit 30 closes the latch circuit 28 at the timing of the clock signal
The data is taken in and held at the timing of the clock signal φ. In addition, an N-channel MOS transistor 31
When a reset signal is supplied to the gate of the transistor 31, the transistor 31 is turned on, and the output data of the latch circuit 30, which is supplied as an accumulated value to the product/sum calculating circuit I4, is forcibly cleared to the 0'' level. Further, during the reset period, the output of the inverter 32 is set to "O" level, and the output of the clocked inverter 29 in the latch circuit 30 is set to a high impedance state.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, in the above embodiment, an example was described in which the present invention is implemented in a circuit that performs multiplication of GF(28), but it goes without saying that this invention can also be implemented in other multiplications.

[Effects of the Invention] As explained above, according to the present invention, it is possible to provide a multiplication circuit that can be constructed with a small amount of hardware, thereby reducing the manufacturing cost of chips when integrated circuits are formed. be able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the multiplication circuit according to the present invention, FIG. 2 is a circuit diagram specifically showing the above embodiment circuit, and FIGS.
FIG. 6 is a block diagram of a conventional multiplication circuit. 10... Multiplicand holding/base multiplication calculation circuit, 11... Multiplier input multiplication circuit, 12... Selection/holding circuit, 13...
・2-bit exclusive OR circuit, 14... Product/sum calculation circuit, 15... Holding circuit, 21... Selector, 22.
...Latch circuit, 2B...AND gate circuit, 27.
...2-bit exclusive OR circuit, 28.30...Latch circuit, 31...N channel MOS transistor, 3
2...Inverter. Applicant's agent Patent attorney Takehiko Suzue No. 10 2] Part 3 Fourth country Figure 5

Claims (1)

[Claims] The multiplicand A (A=a_
0+a_1α+a_2α^2+...+a_mα^m)
and multiplier B (B=b_0+b_1α+b_2α^2+...
・+b_mα^m) A first circuit that holds each coefficient value of the multiplicand A and generates a value that is sequentially multiplied by the base, and a first circuit that performs multiplication between Numerical values are sequentially supplied and the product of this coefficient value and the value generated by the first circuit is calculated and held, and when different coefficient values of the multiplier B are supplied, this coefficient value and the value generated by the first circuit are calculated and held. and a second circuit that calculates the product with the value generated by the circuit, and calculates the sum of this calculation result and the calculation result held in advance, and the second circuit calculates the final value of the multiplier B. A multiplication circuit characterized in that the multiplication circuit is configured to output a sum value calculated by the second circuit as a multiplication result after the coefficient values are supplied.