JPH01157856A - Full-color video signal processor - Google Patents

Abstract

PURPOSE:To enable the high speed operation of full-color video signals by providing an operation means comprising a plurality of processors for dividing operational processing into a plurality of processings and for respectively performing the divided operational processings. CONSTITUTION:A parameter setting section 100 imparts several moduli necessary for the operational processing of full-color video signals to first, second and third processors 101, 102, 103 in advance. The first part of the whole operational processing to be performed is performed by the first processor 101 in accordance with the moduli imparted in advance by the parameter setting section 100, and the first processor receives R.G.B data 106 from an external device. The R.G.B data 106 are sent to a first FIFO 104, while referring to the status 107 of the first FIFO 104. The received R.G.B data 106 are then operation processed by means of the second and third processors 102, 103 in that order and are supplied as C.M.YBx data 112. Thus, the processing time for each divided operational processing is shortened, and the whole operational processing is in turn quickened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a full-color image signal processing device configured to perform arithmetic processing on full-color image signals at high speed in order to reproduce high-quality images with a full-color printer.

[Conventional technology]

As described in the Journal of the Institute of Image Electronics Engineers, Vol. 10, No. 5, pages 5911 to 406, the conventional image signal processing device for a full-color printer generates an output signal corresponding to a received full-color image signal, that is, 7/I/ The full-color image signal guided to the color printer is obtained in advance for all possible combinations according to the desired arithmetic processing, and stored in a table memory, and during actual recording, the received full-color image signal is It was constructed using a so-called look-up table memory method in which the table memory recorder is referred to as an image signal care address and the signal obtained thereby is guided to a full-color printer.

That is, at the address end of table memory.

Received full color image @ signal (e.g. R-G-B signal)
As a result, arithmetic-processed image signals (for example, C/M, Y-BK image signals) are obtained at the data output end of the table memory, and these are led to a full-color printer.

Since this look-up table memory method only accesses the memory during recording, it has the characteristic of being able to process full-color image signals at extremely high speed.

[Problem that the invention seeks to solve]

The conventional technique 8 described above has a problem in that the capacity of the lookup table memory becomes enormous.

In other words, the minimum number of gradations required to reproduce a beautiful image such as a photograph using a full-color printer is 64 to 256 gradations. Considering a look-up table memory that inputs R/G-B signals and obtains a C-M-Y-BK image signal, in the case of 64 gradations, the data width is 6 bits for each color, and in the case of 256 gradations, the data width is 6 bits for each color. Each color requires a data width of 8 bits. Therefore, in the case of 64 gradations, 2 × 6 × 4
In the case of 256 gradations, a memory device with an enormous capacity of 512 mechanical pits in 2 x 8 x 4 is required. There was a problem that it took a lot of time.

The purpose of the present invention is to perform full-color image processing that allows high-speed calculation of full-color image signals without using a huge capacity table memory as described above (and without employing a look-up table memory method). The equipment is to provide.

[Means for solving problems]

The above purpose is to divide the desired arithmetic processing into multiple parts, allocate a processor to each part, and execute the processor Z according to the processing procedure.
Arranged in series, Z first-in first-out memory c between each processor
This is achieved by configuring the connection using FXPO (hereinafter simply referred to as FXPO).

That is, a desired arithmetic process is divided into a plurality of parts, a processor is assigned to each part, and they are arranged in series according to the procedure of the arithmetic process, and each processor is connected by a FIFO. For example, if it is divided into 75 desired arithmetic operations,
Each processor has one processor allocation, that is, six processors. Each processor is arranged in series according to the procedure of arithmetic processing. Next, the first FIFO connecting the first processor and the second processor
Then, a second 0FIFOχ is arranged to connect the second processor and the third processor.

In this way, the first processor, the first FIFO
, the second processor, the second FIFO, and the third processor are arranged in series in this order. Furthermore, a procedure is provided to set the calculation coefficients necessary for calculation processing, and by this means, the calculation coefficients are provided to each processor.

First, the first processor receives image data from the outside and processes this image data according to the arithmetic processing assigned to it. Next, it is checked whether the image data after the first PIFOK processing can be written, and if possible, the first processor writes the image data Y after the processing.
Write I FOiC. If it's not possible, wait until it becomes possible. The second processor checks whether image data can be read from the first FIFO, and if so.

Read image data from the first FIFO.

If it's not possible, wait until it becomes possible. The image data thus read out is processed according to the arithmetic processing assigned to the second processor. Then the second FIFO
Check to see if the processed image data can be written to the second processor, and if possible, write it to the second PIF"(lc). If it is not possible, wait until it becomes possible. The third processor
Check whether image data can be read from the second numbered PIF (J), and if possible, read the image data χ from the second PIF'0. If not, wait until it becomes possible.

The image data thus read out is processed according to the arithmetic processing assigned to the fifth processor. next,
The image data after this processing is output in response to an external synchronization signal.

[Effect]

As described above, since the desired arithmetic processing is divided into a plurality of parts, the amount of processing for each part is reduced by the amount of division. Therefore, it is possible to increase the processing speed of each processor in charge of the divided arithmetic processing, so that the arithmetic processing speed of the full-color image processing apparatus can be increased to 2Y.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention,
100 is a parameter setting section, 101 is a first processor,
102 is a $2 processor, 105 is a fifth processor, 1
04 is the first FIFO 1105 is the second F'IFO.

In this embodiment, the full-color image signal is divided into tS arithmetic operations, and five processors share the processing.

In the figure, the parameter setting unit 100 includes a first processor 101. The second processor 102 and the third processor 103 are provided with various coefficients necessary for arithmetic processing of the full-color image signal in advance. Each processor executes the following processing based on the various coefficients given by the parameter setting section 100K. First, the first processor 101 receives R-G-B data 1 from an external device (not shown).
06 received.

This R-G-B data 106 is subjected to a first part of all arithmetic processing by the first processor 101 according to various coefficients given in advance by the parameter setting section 100, and the status 107' of the first PIFO 104 is
It is sent to the first F'IF0104 while referring to lJI'. Next, the second processor 102 processes the first PIFO 10
Receive the data while referring to the status 108 of 4, and l! 1 processor 101 is applied to the received data, and the second P I F
0105 OXf -1:X, 109 Send data to 2nd PIPO1os with V reference M L.

Next, the third processor 103 processes the second P I F O1
05 status 110% - While referring to the data
The image is output to a recording device such as a full-color printer (not shown) according to the image. The R-G-B data 106 received in this manner is transmitted to the first processor 101. The second processor 102 and the third processor 103 sequentially perform arithmetic processing on the C-
It is output as M-YBx data 112. Furthermore, in this embodiment, since the arithmetic processing is divided into three parts, the time required for each arithmetic processing after division is short (this makes the apparent arithmetic processing faster).

Furthermore, processors that process 16-bit wide data are currently mainstream, and can maintain sufficient accuracy to handle 256 gradations, that is, 8-bit 7A/color image quality. Therefore, according to this embodiment, the object of the present invention, which is to process full-color image signals at high speed and with high accuracy, can be achieved.

FIG. 2 is a block diagram showing specific details of the arithmetic processing explained in FIG.
203 is a black signal extraction unit, 204 is an under color removal unit, and 205 is a gradation correction unit.

In the same figure, there are images of Oi'cmill F-206B, 206.
G and 206B are input to the gradation conversion unit 201, where correction of distortion of one gradation characteristic, gamma correction, etc. are performed. The image data 207C, 207M, and 207Y after correction are processed by the color correction unit 202.
The image data is input to the printer, and a process is performed to correct the turbidity Y of the three color inks of cyan (C), magenta (M), and yellow (Y) used for recording by a full-color printer.

Furthermore, image data 208C after processing in the color correction unit 202
.

208M and 208Y are input to the black signal extraction section 203.

This black signal extraction unit 203 extracts image data 208C, 20
8M.

This is for extracting the black component from 208Y.

The black data 209 output from the black signal extraction section 203 is input to the undercolor removal section (UcR) 2oa. IjCR2
o4 is for subtracting the black data 209K) from the black signal components of the image data 208C, 208M, and 208Y. The image data 209C, 209M, 209Y and the black data 209 subtracted by 001%2oa are as follows:
The tone correction unit 205 receives K input and performs tone correction on the image printed by the full-color printer. This makes it possible to emphasize the tone of any part of the highlight, halftone, or shadow of the recorded image. Gradation correction section 2
Image data 2100.210M, 2 obtained as a result of 05
Full color printers etc. are led to 10Y and 210.

FIG. 3 is a flowchart showing the operation procedure of each processor in FIG. (O) shows the operation procedure of the fifth processor 105. Furthermore, the gradation correction section 201 and color correction section 202 of the arithmetic processing in FIG. 5 processor 103 to share the task.

@3 In Figure (6), the first processor 101 receives R-G-B data from the outside (506), then performs gradation correction (501), and further performs color correction (502).

Next, it is checked whether there is a free area in the first FIFO, that is, whether it is possible to write image data to the first FIFO (307), and if writing is not possible (316).
) Wait until it becomes possible, and if it is writable (317)
Write image data to the first F'IP'0 (18) and receive the next FL-GB data <506).

From now on, process in the same way (υ without changing).

Next, in FIG. 5(N), the second processor 102 determines whether there is image data to be read out in the first FIFO.
That is, say whether it is possible to read the image data from the first fl' IFO (509), if it is not possible to read it (318), wait until it becomes possible, and if it is possible to read it (519). Image data is read (310). The read image data is subjected to black signal extraction (503) and UCFL (504) processing.

Next, check whether there is a free area in the 21st “IFO”:
That is, it is checked whether it is possible to write to the second FIFO (511), if it is not possible to write (320), wait until it becomes possible, and if it is possible to write to the second FIFO (321).
Write the image data to the FIFO (512), check whether the next image data can be read from the first PIF'o (509), and repeat the process in the same way.

In addition, in FIG. 5(0), the sixth fluo setter 106
Is there image data to be read from the second PIFCJIC, that is, the 21st? Check if it is possible to read image data from IFO (313), and if it is not possible (522) wait until it becomes possible and if it is possible to read out 1 meter (323) read the image data from the 211th line 0. (314). This read image data is subjected to gradation correction (505). Next, the image data, that is, C-M-Y-1x Chitan When outputting to a full-color printer (515), the next image data is
' Check if it is possible to read from IFO (515
), the same process is repeated thereafter.

In this way, since the processing is shared among the three processors, the processing speed of each processor can be increased.

As described above, according to this embodiment, the processing is divided among six processors, so that the processing speed of each 7r2 setter can be increased.

〔Effect of the invention〕

As explained above, according to the present invention, since the arithmetic processing of desired image data is divided and the processor χ is assigned to each divided arithmetic processing, it is possible to increase the arithmetic processing speed of each processor. This makes it possible to increase the processing speed of full-color image signals and provide a high-quality full-color image@signal processing device.

[Brief explanation of the drawing]

The first row is a block diagram showing an embodiment of the present invention, the second row is a block diagram showing the specific configuration of arithmetic processing, and the sixth row is a flow diagram explaining the operation of each 7ct setter of the first row. be. 101...First processor. 102... Second processor, 103... Third processor, 201... Gradation correction section, 202... Color 1 stop section, 206... Black signal extraction section, 84...... U) L. 205...Tone correction section. Proxy 9P Burial Officer Katsuo Ogawa

Claims (1)

[Scope of Claims] 1. A receiving means for receiving a full-color image signal, a calculating means for processing the full-color image signal received by the receiving means in order to reproduce a high-quality image by a full-color printer, and this calculating means. a full-color image signal processing device comprising: means for guiding a full-color image signal subjected to arithmetic processing to the full-color printer; A full-color image signal processing device comprising: a full-color image signal processing device configured to enable high-speed calculation of image signals. 2. The full-color image signal processing device according to claim 1, characterized in that the plurality of processors are constituted by a plurality of buffer memories connected in series according to the order of arithmetic processing. Processing equipment. 3. A full-color image signal processing device according to claim 1, further comprising a calculation coefficient setting means for externally setting calculation coefficients necessary for the calculation processing.