JPH01155708A - High speed sequential filter circuit - Google Patents

Abstract

PURPOSE:To execute the two-dimensional sequential filter processing at a high speed by entering each picture element sequentially by a window register section 12 according to the picture raster scanning, reconstituting picture elements in a 3X3 window and giving the result sequentially to a bit deciding section. CONSTITUTION:The most significant bit - the least significant bit of an input data are fed to window generating circuits 512-515 while being retarded sequentially by the unit time. The bit deciding section 52 comprises stages 521-524 of the stage number corresponding to the bit length of the input data and each stage consists of determining circuits of the same structure and a number (9 circuits) equal to number of picture elements in the window. The determining circuit 53 consists of determining circuits 531-534 of the stage number corresponding to the data bit length of the input data. An output register 54 receives the result of decision by a bit corresponding to each picture element outputted from the decision circuits 531-534 and applies delay synthesis and then the result of a prescribed sequential filter processing is obtained sequentially simultaneously for 4 bits each.

Description

[Detailed Description of the Invention] [Summary] Regarding a two-dimensional sequential filter circuit, the purpose of the present invention is to enable high-speed execution of two-dimensional sequential filter processing, and a window register section (41) into which image data is input; , the most significant bit, second bit, . . . , least significant bit of the pixel within the window are input from the register section, and the stages (421, 422) equal to the number of bits of the pixel are input.
, . . .) and the judgment results of each judgment circuit of each stage of the bit judgment section are inputted and compared with the set number (A.

A bit determination unit (43) that outputs the determination results (A, B, . . .); and an output that receives the determination result (A, B, . . .) and outputs pixel data within the specified window. It is composed of a register section (44).

[Industrial application field]

The present invention relates to a high-speed sequential filter circuit that can perform two-dimensional sequential filter processing at high speed.

An ordered filter scans a window set in a signal over the entire signal, sorts the values of each sample within the window, and outputs samples (values) in a specific order.

To explain with reference to FIG. 8, 111 on the left side is input data, and W is a window. In this example, the window contains 11,512 input data (each sample of the input signal or its value), but if you sort it and arrange it in ascending order, it will become 11,125, but if the sample to be extracted is in the center, in this example, l is extracted and becomes the output data. The window W advances to the right at a pitch of one sample, and the same processing is performed each time, so the output data becomes as shown in the figure.

The sample extracted from the window is not necessarily the center sample, but the largest one, the smallest one, the i-th sample specified as appropriate, etc. A filter that extracts the center value is a medium filter, a filter that extracts the maximum value is a max filter, etc. Called.

When this filter is used for signal processing, it can be used to remove noise in signals and shape signals, and when used for image processing, it can be used to effectively remove noise from grayscale images and to enlarge and shrink areas. It can be done and is used in a wide range of fields.

[Conventional technology]

The order filter takes time because it requires the operations of extracting samples within a window, sorting them, and extracting those that meet specified conditions. Therefore, various speed-up techniques for sequential filters have been proposed, and the present applicant has Dimensional Sorting Circuit” (Japanese Patent Application Laid-Open No. 59-117635)
etc.

Both (1) and (2) above are techniques for performing one-dimensional sequential filter processing at high speed based on a pipeline method. Figure 9 shows the basic concept of these methods. In FIG. 9, 20 indicates a signal string (image data) to be processed, and a window W (size 5 in this case) is scanned over this signal string (image data). 21 is a register that holds the sorting results of each data in the window at each point in time; for example, +8)
When there is (as shown in bl), 3-5-6-7-11 are stored in ascending (or descending) order from the left. Next,
(C) As shown in the figure, when the window W is shifted to the right by one data, the contents of the register are changed accordingly.The flow of this process is shown in (d) (el). , first compares each data in the register 21 with the data 7 that comes out of the window W as the window is shifted, and finds the data (7 in this example) that should be ejected from the register. Data 4
and each data in the register to determine the position to be inserted (d). Use this information to control the registers and change the data stored in the registers (transfer to left or right register, replace with input data)
. In this case, the register is controlled as shown in (e), and as a result, the result of sorting the data within the shifted window is held in the register. Since each of these processes can be completed within one clock, they can be executed at high speed based on the pipeline system. .

The above (2) is a technique for realizing two-dimensional sequential filter processing. Figure 10 shows the basic idea. 10th
In the figure, a window generation unit 31 sequentially inputs image data 20 and sequentially reconstructs two-dimensional pixels corresponding to a window W (here, 3×3) in the image. The data providing unit 32 sequentially transfers newly input pixels to the sorting unit 33 as the window is scanned. The figure shows a state where the window W on the input image 20 has moved one sample to the right from the left end, and the output data at this time is 8
．． 8.2. What about new data? , 5.13. Is the data providing unit 32 newly received data? , 5
．． 13 are sequentially sent to the sorting unit 33, and the previous inputs 2. 6
．． 8 and the inputs 3, 7, and 9 from the previous time are not sent (because they are in the sequential sorting section 33). The sequential sorting unit 33 is a one-dimensional sequential filter, and in this example, nine samples are sorted and arranged in ascending order, and the fifth sample from the end corresponding to the center of the window is output. Thereby, two-dimensional sequential filter processing can be realized.

[Problem that the invention seeks to solve]

One-dimensional sequential filter processing can be operated using the Vibration method and linked to a clock, but for two-dimensional sequential filtering, if the window size is NXM, a time proportional to M is required. There is a problem that the speed cannot be increased when the window size is large.

The present invention aims to improve this point and enable high-speed execution of two-dimensional sequential filter processing.

[Means for solving problems]

FIG. 1 shows the configuration of the present invention. 41 is a window register section into which image data is sequentially input pixel by pixel; 42 is the most significant bit of a pixel within the window from the window register section;
A bit judgment unit 43 takes in the second-order bit, and outputs the judgment result, and compares the judgment result with the set number (A).

The bit determination unit 44 outputs the comparison result (A, B, . . .) and outputs the data of the pixel within the specified window. This is the register section. The bit determination section 42 consists of a plurality of determination circuit groups (stages > 421, 422, . . . , and the bit determination section 43 consists of a plurality of stages 431, 432, . . .
Consists of...

Taking median filter processing using a 3×3 window as an example, the details of the configuration and operation of this circuit will be described below. In the following explanation, (abcd)2 indicates data expressed as a binary number, and a・2 +b−2+c2
Equivalent to +d.

[Effect]

The window register section 41 sequentially inputs each pixel according to the raster scan of the image, reconstructs the pixels within a 3.times.3 window, and provides the reconstructed pixels to the spot, pit, and hit determination section 42.

The bit determination unit 42 has stages 421 . Call 22.・・・・・・
It consists of Also, each stage has a module (judgment circuit) equal to the number of pixels in the window (9 in this case).
It consists of In stage 1 (421), each module has to judge whether the pixel in the window is larger than (1...)2.
shall indicate that this work is to be ignored. Therefore, in this case, only the most significant bits are compared. ), if they are greater or equal, the result is output to the bit determining section 4. Furthermore, depending on the result A (1 or O) of the bit determination unit 43, the value of each pixel is changed to (A...)
2, the result [=<> (for example, with a 2-bit signal line, if the pixel value is large, it is expressed as lOl, if it is equal, it is expressed as l11, and if it is small, it is expressed as 00.) Output to module.

In stage 2 (422), similarly to stage 1 (421), each module determines whether the pixel within the window is larger than (Al...)2, and sends the result to the bit determination unit 43. At the same time, according to the result B (1 or 0) of the corresponding stage of the bit determination unit 43, the result of comparing the value of each pixel with (AB...)2 is output to the corresponding module of the next stage. . Note that these determinations are made using each pixel obtained in stage 1 and (A...)
By using the comparison result of No. 2, the second-order bit can be obtained by newly comparing only the second-order bit.

Also, in stage 3 (423), stage 1゜2 (
421, 422), each module determines whether the pixel within the window is larger than (ABI・)2, outputs the result to the bit determination unit 43, and outputs the result to the bit determination unit 43. Result C of the corresponding stage
(1 or 0), change the value of each pixel to (A B C・
)2 and outputs the result to the corresponding module of the next stage. These determinations can also be obtained by newly comparing only the third bit by using the comparison results of each pixel and (AB...)2 obtained in the previous stage (stage 2). Can be done.

Furthermore, in stage 4 (424), stage 1゜2,
3 (421, 422, 423), each module has pixels in the window (ABCI)2
, and outputs the result to the bit determining section 43. These judgments are also at the previous stage (
By using the comparison results between each pixel and (ABC·)2 obtained in stage 3), it is possible to newly obtain the fourth bit by comparing only the fourth bit.

The bit determining unit 43 also includes stages (431, 432, . . . ) corresponding to the bit length of the data. Here, each stage (42
1, 422, . . .), and outputs the results to the beat/beat determination section and the output register section. Specifically, stage 1
, (431), the value of each pixel in the window is (l...
・) Count the number of pixels greater than or equal to 2, and calculate that number and a predetermined setting value M (for example, 5 in the case of a median filter, and in the case of an ordinal filter that outputs the third value) is 3.), and the result is A(
1 if larger than the set value M, 0 if smaller)
Output.

Next, in stage 2 (432), in the same way, the number of pixels in the window whose value is greater than or equal to (AI...)2 is counted, and the number is compared with the set value M. Output result B. Similarly, in stage 3 (433), the value of each pixel in the window is (ABI・)2
The number of pixels that are greater than or equal to is counted and compared with the set value M, and the result C is output. Furthermore, in the same manner at stage 4 (434), the number of pixels in the window whose value is greater than or equal to (ABC・)2 is counted, the number is compared with the set value M, and the result is Output.

In the output register 44, each bit data (A, B.

C, D) and outputs the result (ABCD)2.

The operation of the median filter will be explained using FIG. ■(1011)2.■(0110)2.・・・・・・
Compare only the most significant bit (shaded part) of (1...)2 (shaded part), and if the pixel values are larger or equal, set l, and if smaller, set 0 The determination result is output to the bit determination section 43. The stage 431 of the bit determination unit 43 counts the number l, which in this example is 4.
Since it is less than the set value M (5 in the case of the median value), the most significant bit of the median value is set to 0 (this is the A sent to the output register section 44). Furthermore, based on this result of the data l of the bit determination unit 43, each determination circuit (1), (2), . . . of the stage l of the bit determination unit 42
Each pixel in the window ■(1011)z,■(0110
)2゜... Compares only the most significant bit of (0...)2 (the part multiplied by 12I), and if the pixel value is large, lOl is equal, then 11 , the determination result of 00 is output to each corresponding determination circuit of stage 2 of the bit determination section 42.

Value of pixel within window (1011) 2. <011
0)2. . . . and (1...)2, it is sufficient to compare the most significant bits. 21... need only input the most significant bit of the value of the pixel within the window.

The next stage 2 (422) determines the second bit of the median value. In this example, the determination result of stage 1 (421) and (1011) 2 . ■(
0110)2. Using the result of comparing only the second bit (shaded part) of ...... and the second bit (shaded part) of (01...)2, each pixel in the window Obtain the result of comparing the upper 2 bits with (01...) 2. Then, if the values of the upper two bits of the pixel are larger or equal, the judgment result is 1, and if the values are smaller, the judgment result is 0, which is output to the bit determining section 3. Stage 2 (432) of the bit determination unit 43 counts the number of 1s, and in this example, this is 8, which is larger than the set value (5 in the case of the median value), so the second bit of the median value is set to 1. (This is the B sent to the output register section 44). Furthermore, based on this result of stage 2 of the bit decision section, the decision result of stage 1 (421) and each i! i abandon■ (1011) 2. ■
(0110)2. Using the result of comparing only the second bit (shaded part) of . (01...) The result of comparing the upper two bits with 2 (11 if larger, 10 if equal, 00 if smaller) is calculated, and the result is applied to each stage 3 of the bit determination unit 43. Output to the corresponding judgment circuit.

The third bit of the median value is the judgment result of the previous stage, the third bit from the window register section, and (01
1.) Using the result of comparing the third bit of 2, count the 1 of the judgment result. In this example, this is 6, so the third bit of the median value is set to 1, and the fourth bit of the median value is counted. Similar processing is performed for bits to obtain 1 for the bits. In this way, oiit is sent to the output register section, and the median value is (
0111·)2.

FIG. 2(b) is an example of a sequential filter that outputs the third value. In this example, the setting value M is only 3, and the operation of each part is exactly the same as the example in FIG. 2 (al).

The basic part of this circuit can be constructed by combining the same modules, and it can be easily integrated into an LSI.

〔Example〕

Embodiments of the present invention are shown in FIGS. 3 to 5. This circuit can implement arbitrary order filter processing (maximum value - median value - minimum value filter processing) by external settings.

FIG. 3 shows the overall configuration, including a window register section 51,
It is composed of a bit determination section 52, a bit determination section 53, and an output register section 54. The input data at the upper left end is input in pixel units, and in this example, 4 bits are input simultaneously, and the output data at the lower right end is the data (4 bits) of the central pixel specified within the window in this example.

The window register section 51 includes an input register circuit 511
and window generation circuits 512 to 515 (the number of bits of an lli element is assumed to be 4). As shown in Figure 4(a),
The input register circuit 511 is composed of a D-type latch with a number of stages (three stages) corresponding to the bit length of the input data (four in this case), and sequentially reads the most significant bit to the least significant bit of the input data in units of units. It is provided to the window generation circuits 512 to 515 while being delayed by a certain amount of time. This delay is due to pipelining. As shown in FIG. 4(b), the window generation circuits 512 to 515 are composed of a plurality of D-type latches and a shift register SR having a length corresponding to the width of the image. bit, second-order bit, etc.), receives sequential data input, and receives two-dimensional data within the window (9 bits in this example, 5211° 5212
, . . .) are sequentially reconfigured in a pipeline manner and provided to the bit determination unit 52.

The bit determination unit 52 is composed of stages 521 to 524, the number of which corresponds to the bit length of the input data, and each stage is further composed of determination circuits having the same structure and having the same number (9) as the number of pixels in the window. ing. Figure 4 (C
) indicates the configuration of the stage 522, 5221 to 5229
are nine judgment circuits. The other stages have the same configuration. In stage 1 (521), each judgment circuit (5211
~5219), the pixels within the window are (1
000) is larger than 2, and if it is larger, the result 1 is notified to the bit determination unit 53. Furthermore, according to the result of the bit determination unit 53, the result is A(1
or 0), the value of each pixel is compared with (AOOO)2 and the result (=<>) is output to the corresponding modules 5221 to 5229 of stage 2 (522). In stage 2 (522), the output from stage 1 (521) (
5211 to 5219) and the window generation circuit 513
Upon receiving the outputs (indicated by 5221 to 5229), each module 5221 to 5229 respectively determines whether or not the pixel within the window is larger than (A100)2, and notifies the bit determination unit 53 of the result. , according to the result of the corresponding stage of the bit determination unit 53, and if the result is B (1 or O), the value of each pixel is (ABOO
)2 is output to the corresponding modules (5231 to 5239) of the next stage 523. In stage 3 (523) and stage 4 (524), stage 1. 2 Performs the same processing as (521, 522).

FIG. 5(a) shows the configuration of the determination circuit. Although this figure shows the configuration of the determination circuit 5222, the other determination circuits have similar configurations. The determination circuit consists of two 1-bit comparison circuits and one multiplex circuit. In the determination circuit 5222, the input DIN is data corresponding to each pixel in the window of each bit from the window register circuit (in this case, 5222
22) is input. The determination result (5212 in this case) output from the corresponding determination circuit of the previous stage is input to the inputs EF and LF. The output LJ outputs the result of comparing the input DIN and (ABOO)2 based on the result of the previous stage, and notifies the bit determination unit 53 of the result. Next, the result from the bit determination unit 53 is inputted from the input S, and based on this, the multiplex circuit selects the comparison circuit CMP+ and the comparison circuit CM.
Select the output of P2, via output EN and LN,
It is output to the corresponding determination circuit 5232 of the next stage.

The bit determining section 53 includes circuits 531 to 534 for determining the number of stages corresponding to the bit length of input data. Each decision circuit has an address (L Js+1 to L , Js+9
, Ca -C]), and the output of each judgment circuit (LJs, 1 to LJs, 9) at each stage (s) and the set value C (Co =
C3) is input as an address in binary representation as 7, and its contents are output. FIG. 5(b) shows the configuration of the bit determination unit 531, and the above addresses L Js, 1 to L Js, 9
is 5219 (A a ) ~ 5211 (A e )
In this case, Ca=Ca corresponds to A9 to Al2. The output is 5
Shown as 2. The arithmetic logic of each decision circuit is shown in the following equation. However, Js is the output of the decision circuit.

......(Equation 1) However, C is a setting value given from the outside, and in the case of the maximum value filter, C=9, and in the case of the median value filter, C=5,
In the case of a minimum value filter, C=1 will be given.

The output register 54, as shown in FIG. By inputting the bit-by-bit determination results corresponding to each pixel that are output with a delay from the decision circuits 531 to 534 and performing delayed synthesis, it is possible to obtain four bits of predetermined sequential filter processing results simultaneously and sequentially.

FIG. 6 shows a modification of the bit determination section 53. In this modification, each determination circuit 531 of each stage of the bit determination unit 52
Result output from ~534 L Js, 1~LJ,,t
, an adding circuit 92 that adds the counting result to externally input data (Mb), and a comparing circuit 93 that compares the addition result with a set value C. By setting Mb=o, this circuit operates exactly the same as the bit determining circuit of the embodiment. Furthermore, in this modification, a plurality of bit determination units 71 to 73 and bit determination units 74 to 76 are prepared as shown in FIG. By using this as an input to the adder circuit of the next stage 76, the window size can be changed.

〔Effect of the invention〕

As explained above, according to the present invention, two-dimensional sequential filter processing can be executed at high speed, and furthermore, since the basic parts of the sequential filter circuit can be configured in the same module, LSI
This has the effect of being easy to convert. Further, by passing the operation result (intermediate) of the bit determining section to another bit determining section, there is an effect that the size of the window of the order filter can be freely expanded.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the present invention, FIG. 2 is a diagram explaining the principle of the present invention, FIG. 3 is a block diagram showing the overall configuration of an embodiment of the present invention, and FIGS. 4 and 5 are 3 is a block diagram showing details of each part, FIG. 6 is a block diagram showing a modification of the present invention, FIG. 7 is a block diagram showing an example of expanding the window size, and FIG. 8 is an explanatory diagram of a one-dimensional ordered filter. , FIG. 9 is an explanatory diagram of the sorting procedure of the sequential filter, and FIG. 10 is an explanatory diagram of the two-dimensional sequential filter. Figure 9

Claims (2)

[Claims] (1) A high-speed sequential filter circuit characterized by having the following requirements [1] Image data obtained by raster scanning an image is input pixel by pixel, and two-dimensional pixels corresponding to an n×m window are At the same time, the binary value l of each pixel in the window is
The most significant bit of the value expressed in bits, the second bit,
. . . It has a window register unit (41) that outputs each bit of the least significant bit sequentially with a delay. [2] The number of stages corresponding to the number of bits l of the pixel (
421, 422, . . . ). Each stage has a number of determination circuits equal to the number of n×m pixels in the window. In the first stage (421), each decision circuit receives the most significant bit of the pixel within the window, compares it with 1, notifies the result to the bit decision section (43), and outputs the result (A) from the bit decision section.
) is added and the judgment result is output to the corresponding judgment circuit of the next stage. The next and subsequent stages (422,...
), each judgment circuit receives the second bit, third bit, etc. of the pixel within the window, and converts it into binary numbers (A100...)_2, (AB10...・・・・・・
・)_2, the result is notified to the bit determination section, and the determination result, which is added with the result (B, . . .) from the bit determination section, is output to the corresponding determination circuit of the next stage. [3] The number of stages corresponding to the number of bits l of the pixel (
431, 432, . . . ). Each stage (431, 432, ...) of the bit determination section (43) receives the determination result of each determination circuit output from each stage (421 to 424) of the bit determination section (42), The bit judgment unit (42
) and the output register section (44). [4] Each stage (431, 4
It has an output register for delay-synthesizing each bit data that is delayed and output from 32, . . . ). (2) The bit determining unit (43) is a bit determining unit (52)
a counting circuit (91) that counts the results output from each judgment circuit of each stage; an adder circuit (92) that adds the counting results to externally input data (Mb); 2. A high-speed sequential filter circuit according to claim 1, characterized in that it is comprised of a comparison circuit (93) for comparing with (C).