JPH01153739U - - Google Patents
Info
- Publication number
- JPH01153739U JPH01153739U JP5115088U JP5115088U JPH01153739U JP H01153739 U JPH01153739 U JP H01153739U JP 5115088 U JP5115088 U JP 5115088U JP 5115088 U JP5115088 U JP 5115088U JP H01153739 U JPH01153739 U JP H01153739U
- Authority
- JP
- Japan
- Prior art keywords
- gate array
- cmos gate
- power supply
- utility
- logic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5115088U JPH01153739U (en:Method) | 1988-04-15 | 1988-04-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5115088U JPH01153739U (en:Method) | 1988-04-15 | 1988-04-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01153739U true JPH01153739U (en:Method) | 1989-10-23 |
Family
ID=31277178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5115088U Pending JPH01153739U (en:Method) | 1988-04-15 | 1988-04-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01153739U (en:Method) |
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1988
- 1988-04-15 JP JP5115088U patent/JPH01153739U/ja active Pending