JPH01151684U - - Google Patents
Info
- Publication number
- JPH01151684U JPH01151684U JP4903488U JP4903488U JPH01151684U JP H01151684 U JPH01151684 U JP H01151684U JP 4903488 U JP4903488 U JP 4903488U JP 4903488 U JP4903488 U JP 4903488U JP H01151684 U JPH01151684 U JP H01151684U
- Authority
- JP
- Japan
- Prior art keywords
- image data
- circuit
- outputs
- image signal
- frame memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Television Systems (AREA)
Description
第１図は本考案の一実施例を示す構成図、第２
図は第１図中の間引き回路の動作を説明する図で
ある。
１……フレームメモリ、２……高精細度読出し
制御回路、３，７……Ｄ／Ａ変換器、４……間引
き回路、５……ラインバツフア、６……ＮＴＳＣ
読出し制御回路。
Fig. 1 is a configuration diagram showing one embodiment of the present invention;
This figure is a diagram explaining the operation of the thinning circuit in FIG. 1. 1... Frame memory, 2... High definition readout control circuit, 3, 7... D/A converter, 4... Thinning circuit, 5... Line buffer, 6... NTSC
Read control circuit.
Claims (1)
と、前記フレームメモリからの高精細度画像デー
タをアナログ画像信号として出力する第１の変換
回路と、前記フレームメモリからの高精細度画像
データをライン単位で間引く間引き回路と、前記
間引き回路からの間引き画像データを１ライン分
記憶するラインバツフアと、前記ラインバツフア
に記憶された間引き画像データをＮＴＳＣ画像信
号レートで読出す制御回路と、ＮＴＳＣ画像信号
レートで読出された画像データをアナログ画像信
号として出力する第２の変換回路とを備えること
を特徴とする画像表示装置。 a frame memory that temporarily stores image data; a first conversion circuit that outputs the high-definition image data from the frame memory as an analog image signal; and a first conversion circuit that outputs the high-definition image data from the frame memory in line units. a thinning circuit for thinning out, a line buffer for storing one line of thinned image data from the thinning circuit, a control circuit for reading out the thinned image data stored in the line buffer at an NTSC image signal rate, and a control circuit for reading out the thinned image data stored in the line buffer at an NTSC image signal rate; and a second conversion circuit that outputs the image data as an analog image signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4903488U JPH01151684U (en) | 1988-04-11 | 1988-04-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4903488U JPH01151684U (en) | 1988-04-11 | 1988-04-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01151684U true JPH01151684U (en) | 1989-10-19 |
Family
ID=31275154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4903488U Pending JPH01151684U (en) | 1988-04-11 | 1988-04-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01151684U (en) |
-
1988
- 1988-04-11 JP JP4903488U patent/JPH01151684U/ja active Pending
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