JPH01151626U - - Google Patents

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Publication number
JPH01151626U
JPH01151626U JP4862788U JP4862788U JPH01151626U JP H01151626 U JPH01151626 U JP H01151626U JP 4862788 U JP4862788 U JP 4862788U JP 4862788 U JP4862788 U JP 4862788U JP H01151626 U JPH01151626 U JP H01151626U
Authority
JP
Japan
Prior art keywords
processing circuit
signal source
circuit
indicates
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4862788U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4862788U priority Critical patent/JPH01151626U/ja
Publication of JPH01151626U publication Critical patent/JPH01151626U/ja
Pending legal-status Critical Current

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  • Dc Digital Transmission (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aはこの考案の一実施例であるデジタル
信号処理回路のブロツク図、第1図bは第1図a
の各部の信号波形図、第2図aは従来のデジタル
信号処理回路のブロツク図、第2図bは第2図a
の各部の信号波形図である。 図において、1は信号A、2は信号B、3は処
理回路A、4は処理回路B、5は処理回路Cを示
す。なお、図中、同一符号は同一、または相当部
分を示す。
Figure 1a is a block diagram of a digital signal processing circuit that is an embodiment of this invention, and Figure 1b is a block diagram of a digital signal processing circuit that is an embodiment of this invention.
Figure 2a is a block diagram of a conventional digital signal processing circuit, Figure 2b is a diagram of signal waveforms at various parts of Figure 2a.
FIG. 3 is a signal waveform diagram of each part of FIG. In the figure, 1 indicates signal A, 2 indicates signal B, 3 indicates processing circuit A, 4 indicates processing circuit B, and 5 indicates processing circuit C. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 信号源Aと信号源B及び処理回路1とその間に
挿入された別の処理回路2そして、処理回路2と
同等の構成の処理回路3から構成される遅延補償
回路。
A delay compensation circuit comprising a signal source A, a signal source B, a processing circuit 1, another processing circuit 2 inserted between them, and a processing circuit 3 having the same configuration as the processing circuit 2.
JP4862788U 1988-04-11 1988-04-11 Pending JPH01151626U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4862788U JPH01151626U (en) 1988-04-11 1988-04-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4862788U JPH01151626U (en) 1988-04-11 1988-04-11

Publications (1)

Publication Number Publication Date
JPH01151626U true JPH01151626U (en) 1989-10-19

Family

ID=31274767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4862788U Pending JPH01151626U (en) 1988-04-11 1988-04-11

Country Status (1)

Country Link
JP (1) JPH01151626U (en)

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