JPH01151497U

JPH01151497U -

Info

Publication number: JPH01151497U
Application number: JP4745188U
Authority: JP
Priority date: 1988-04-07
Filing date: 1988-04-07
Publication date: 1989-10-19

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示すブロツク図、
第２図は従来の半導体記憶装置の一例を示すブロ
ツク図である。１……アドレスバツフア回路、２……デコーダ
、３……記憶部、４，４Ａ……入出力制御部、５
……アドレスバツフア回路、６……デコーダ、７
……選択回路、８……フラグ、９……入出力制御
部、４１，４１Ａ……入出力制御回路、４２……
デーダバツフア回路、９１，９２……入出力制御
回路、９３……選択回路、９４……フラグバツフ
ア回路。 FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing an example of a conventional semiconductor memory device. DESCRIPTION OF SYMBOLS 1... Address buffer circuit, 2... Decoder, 3... Storage section, 4, 4A... Input/output control section, 5
... Address buffer circuit, 6 ... Decoder, 7
...Selection circuit, 8...Flag, 9...Input/output control section, 41, 41A...Input/output control circuit, 42...
Data buffer circuit, 91, 92... input/output control circuit, 93... selection circuit, 94... flag buffer circuit.

Claims

[Scope of utility model registration request]

On one semiconductor chip, there is a memory section that writes and reads first data to an address specified by a first address selection signal, and a memory section that writes and reads first data to and from an address specified by a first address selection signal, and a memory section that writes and reads first data to and from the address specified by a first address selection signal. a first input/output control section that controls write/read and input/output and outputs a synchronization control signal; and when the select signal is at a first level, the first input/output control section
a selection circuit that selects and outputs an address selection signal of , and selects and outputs a second address selection signal when the signal is at a second level; and an address that corresponds one-to-one with the storage section; a flag for writing and reading a second data to an address specified by an address selection signal; and when the select signal is at the first level, a second read and write signal and the synchronization control signal are used to read and write data from the storage section; writing/reading and input/output of second data to the flag is controlled in synchronization with the flag, and when the select signal is at a second level, the second data is written to the flag by a second read/write signal. A semiconductor memory device comprising: a second input/output control section that controls reading and input/output.