JPH01146444A - Exchange having bus type data terminal equipment - Google Patents

Abstract

PURPOSE:To attain 1:N communication arranged remotely through the use of a digital exchange by ANDing or ORing the signals of each data terminal equipment inputted to the digital exchange so as to send the result to each data terminal equipment via the digital exchange. CONSTITUTION:An exchange is provided with plural data terminal equipments 100 and a terminal equipment 100 including plural data interfaces 20 connected to each data terminal equipment 10, sending/receiving a signal and sending a prescribed logic signal at reception standby state. The terminal equipment 100 is connected to a digital exchange 40. Moreover, a logic means 60 is connected to the digital exchange 40. A data from the data terminal equipment 10 is sent to the digital exchange 40 through a corresponding data interface 20 and the logic means 60 ANDs or ORs the signals. The output of the logic means 60 is sent to each data terminal equipment 10 through each data interface 20 from the digital exchange 40.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (@Figures 8 and 9) Problems to be solved by the invention Steps to solve the problems v Ci 1) Effect
(Figure 1) Example
(Figures 2 to 7B) Effects of the invention [Summary] This invention relates to a digital switching device having a data interface for connecting data terminals, and in particular to a switching device having a path type data terminal. 1 in the accommodation method
The purpose is to enable a communication form similar to N-to-N communication, improve operability and ease of maintenance when installing and moving terminals, and accommodate multiple data terminals and enable communication similar to bus type communication. and a terminal device including a plurality of data terminals and a plurality of data interfaces 7ace connected to each data terminal and transmitting and receiving signals, and transmitting a high IMfl logic signal or a low logic signal when waiting for reception, and a digital exchange. , a logic circuit that receives signals sent from a plurality of data interfaces via a digital exchange, takes these logic terms or logical interest rates, and sends the signals to a plurality of data interfaces.

[Industrial application field]

The present invention relates to a digital switching device having a data interface for connecting data terminals, and more particularly to a switching device having a bus-type data terminal.

[Conventional technology]

For example, as shown in FIG. 8, a path-type data terminal unaccommodated system has been known in which a plurality of data terminals 21 to 2nt are connected in parallel to a dedicated bus 1 to perform data communication with each other. This system enables one-to-N communication in which one terminal can communicate with any other terminal via a 1-ft dedicated bus.

For example, from data terminal 2I to other data terminals 21 to 2n
When communicating with one of the terminals 21, the address of the other terminal is sent to the path, and each receiving terminal determines whether the address is addressed to itself or not, thereby ensuring that there is no conflict with other terminals. communication is possible.

It is also conceivable to connect this type of data terminal to an exchange and perform communication similar to bus connection.

As an example of this, a system using a digital switching network as shown in FIG. 9 is known. In FIG. 9, data sent from data terminal 2 is transmitted from data interface device 3. It is configured to be input to a digital switching network 5 via a line circuit 4 for data interface devices. When a caller dials a communication destination prior to data communication, a path P is set within the digital switching network 5 that connects the line circuit 4 of the specific communication destination and the line circuit 4 of the communication source. The input data passes through the path Pt to the communication destination line circuit 4.
．． Data interface device 3° is sent to data terminal 2. By changing the dial designation of this communication destination, it becomes essentially an l-to-N communication mode.

[Problem that the invention seeks to solve]

However, in the former path type data end unaccommodated method (2), the path setting distance is restricted by the capabilities of the transmitting/receiving driver and receiver of each data terminal, and there is a limit to the installation of data terminals over long distances.

■ Because common bus money is used, there is no need to move data terminals,
At the time of expansion, data communications between other data terminals may be affected by noise, and such communications must be interrupted.

There are other problems.

On the other hand, the latter method is based on a point-to-point connection in which the terminal and the exchange are connected via an external line, the exchange is interposed, the exchange determines the other party, and a path P is established. Although the problem is solved, each time data communication is performed, the communication destination must be identified by dialing the destination and an ICI path within the digital exchange 5 must be set, so basically communication is one-to-one. 1 and communicate with multiple terminals at any time (1 to N)
In this case, an exchange operation is required to specify the destination one by one.

There are problems like this.

An object of the present invention is to enable a communication form similar to 1-to-N communication in a bus-type endless system using a digital exchange, and to improve operability and ease of maintenance when installing and moving terminals. The object of the present invention is to provide an exchange system that accommodates a plurality of data terminals and enables communication similar to that of a bus type.

[A precautionary measure to resolve the problem]

To explain the principle of the present invention in FIG. 1, a switching device having a path type terminal according to the present invention has a
A terminal device [1] including a plurality of data interfaces 20t connected to each data terminal 10 and transmitting and receiving signals, and transmitting a constant logic signal when waiting for reception.
00f: Get ready. This terminal device 100 is connected to a digital exchange 40. Furthermore, the signals sent from the plurality of data interfaces 20 are transferred to the digital exchange 40.
The data received through the digital switch 40 are logically ANDed or ORed and sent to the plurality of data interfaces 2 through the digital exchange 40.
Connected to the digital exchange 40 are logic means 60 for sending 0 to 0.

[Effect]

Each data terminal device 100 consists of a terminal 10 that processes data signals and a data interface 20 that interfaces with other parties such as communication procedures.
The data from the data interfaces 20 are sent to the digital exchange 40 through the respective data interfaces 20, and are ANDed or ORed by the logic means 60. logical means 60
The output is sent from the digital exchange 40 to each data terminal 10 through each data interface 20.

To explain using an example in which the logic means 60 is an AND circuit, it is assumed that the data interface 20 sends out a high logic signal when in the reception standby state, and by taking the AND, it is determined that when there are no communication requests from all terminals. , the received signal will be high logic. Therefore, when data is transmitted from one data terminal 10, the logical product 60 performs a logical product and the ratio signal becomes the same as the transmitted data, so the communication source determines that there is no data collision, and If the data specifies the communication destination (1), it will be accepted. If data is sent from multiple data terminals 10 at the same time, a data collision will occur, and the logical means The output of 60 does not match the data sent by each data terminal, and the data communication destination can know the data collision.

゛Furthermore, when the logic means 60 is a logical sum, the data interface 20 sends out a low logic signal when in the reception standby state, and by calculating the logical sum, it is determined that when there is no communication request from all terminals, , the received signal will be a logic low. Therefore, when transmitting data from one data terminal 10, the signal logically summed by the logic means 60 is the same as the transmitted data, so the communication source determines that there is no data collision and Subsequent communication is possible, and the communication destination accepts the data if it specifies itself. When transmitting data from multiple data terminals 10 at the same time, a data collision occurs, and the output of the logic circuit 60 does not match the data sent by each data terminal, and the data communication destination cannot know about the data collision. I can do it.

〔Example〕

One embodiment will be described with reference to figures M2 to i7B.

FIG. 2 shows the overall configuration of the switching device, and this example includes four data terminals 10A to 10D (hereinafter also referred to as 10 as a representative), and a data interface device 220.
Data exchange is controlled via the person 20D (hereinafter also referred to as c, represented by the reference numeral 20). Here, the data terminal 10 and the data interface device [20] constitute a terminal device 100. Data interface device 20
is connected to data interface device line circuits 30 to 30D (hereinafter sometimes represented by the reference numeral 30) via transmission paths. In this embodiment, the data interface device 20
Suppose that the signal transmits a high level signal.

Details of the data interface device 20 and the data interface device line circuit 30 are shown in the third factor.

The data interface device 20 has a buffer 21 that is connected to the data terminal 10 and temporarily stores communication data, and a line termination W622. is digitized into the format shown in the IN4 diagram and sent to the driver 28, and a signal with a similar format sent from the digital exchange network side to the receiver 291 is separated into a data signal and a control signal. The data interface device 20 also includes a terminal control section 23 that controls the line terminal section 21 and the line termination section 22, and a transmitter/transmitter that transmits and receives control signals between the line termination section 22 and the terminal control section 23. The receiver 24 further includes a key bat 25 for pressing a dial of a communication destination, a data call key 26, and an indicator light 27 for indicating completion of data call connection, etc. The reason why the buffer 21 is required is that bus-type data terminals transmit data at a high speed of several Mbps when given the right to use the path, but the bus in the digital switching network 42 generally transmits data at a speed of several Mbps.
This is because data can only be sent at about 4Kbps.

On the other hand, the line termination section 31 provided in the data interface device line circuit 30 separates the signal sent from the data interface device 20 via the receiver 34 into a data signal and a control signal, and the data signal is digitalized. The control signal is sent to the output gate on the exchange side and sent to the transmitter/receiver 32. In addition, the signal sent through the input port on the digital exchange side is
Together with the control signal sent from the common control W644 of the digital exchange 40 via the transmitter/receiver 32t, it is sent to the data interface device 20 via the driver 35ft on the data transmission line side. An interface 33 for relaying control signals is provided between the transmitter/receiver 32 and a common control unit 44, which will be described later. The output ports are respectively connected to a Lunaplexer 41, which will be described later.

! Note that, as shown in FIG. 2, a digital switching network 42. A day multiplexer 43 is connected, and a digital mixing trunk 60 as a logic circuit is provided downstream of the day multiplexer 43, and a digital mixing trunk 60 is provided as a logic circuit to logically AND signals inputted from each data terminal at a predetermined timing and output signals from each data terminal 10 to 10. It is configured to be input to the multiplexer 41 for each IOC.

Multiplexer 41. digital exchange network 42
> and the day multiplexer 43 are controlled by a common control section 44.

A digital mixing trunk 60 is connected to each data terminal 1.
Four reception registers 61 to 61 that store data signals from the day multiplexer 43 corresponding to IODs 0 to 61
D, an AND gate 62 that takes the logical product of the signals stored in the registers 61 to 61D, and four transmission registers 63A to 63D that store the outputs of the AND gate 62 corresponding to the respective data terminals 10A to 100, respectively. have The timing of signal input/output to each of the registers 61A to 61D and 63 to 63D is controlled by a timing signal from a timing circuit 64.

Operation 1c of the embodiment system configured as described above
This will be explained with reference to Figures 7B to 7B.

(1) When transmitting data from 10 data terminals to data terminal IQB Here, each data terminal (10 people ~ l0D) l-! , each connected data interface device (ff
i(20A~20D)? It is assumed that all of the υ are connected to the digital mixing trunk υ (60) via the digital gIL exchange network (42).

This connection is made to data interface device 1 (20A-20
This is done by closing the data call key 26 in D) and operating the key bat 25 to send the access number of the digital mixing trunk (60) to the exchange.

As described above, when no communication is being performed, each terminal sends out a high level signal (high logic signal). The data terminal 10A transmits the address of the IOB.

In the following explanation, the data and address outputted from the data terminal 10A are assumed to be a signal ADI (consisting of input 1, person 2, . . . input 1). This signal ADZ is once accumulated in the buffer γ21, then inputted to the line termination unit 22, and after being digitized in the format shown in FIG.
Sent out.

The digitized nine signals are inputted to the line termination section 31 via the receiver 34, where the control signal and the data signal D1
It is separated into The control signal is sent to the transmitter/receiver 32. The interface 33 is also input to the common system a1 section 44, and the data signal D1 is input to the multiplexer 41. At this time, the other data terminals 1013 to IOD are inputting a signal indicating a high logic "1" to the multiplexer 41 (see the fifth figure).

The multiplexer 41fl sequentially multiplexes the input signal D1 from the data terminal 10A and the "1" signals from the data terminals 108 to IOD and sends them to the digital switching network 42 in a predetermined time slot. These signals are transferred to a common controller 44 in a digital switching network 42.
After a predetermined time slot exchange is performed under the control of
) is input and stored. As shown in FIG. 6A, nine data terminals D are sent to the register 61A from ten data terminals.
1 is stored as AI, A2--person i, and the other registers 61B to 61D contain "1", respectively, because terminals other than the data terminal 10A are outputting high logic signals.
is set. Also, at the next timing, nine signals input D1. When "month" is sent to the AND gate 62 and a logical product is performed, it becomes equal to the information of the terminal that is transmitting the data and is stored in each receiving register 63A to 63D.At this time, each register 63A to 63D is As shown in the 6th figure, the signal input D1 is stored as Al, A2@・work input l, respectively.Then, at the next timing, the receiving registers 63 to 63
A logical product signal D1 from D is input to a multiplexer 41 and is connected to a digital switching network 42. The line circuits 30 to 308 for each data interface device are sent through the day multiplexer 43, and further sent to the data terminal 1 through each data interface device 20 to 200.
The same signal ADZ is supplied to 0A-10D (5th A
figure).

That is, when transmitting a signal ADZ consisting of data terminals 10BK and 12 people 2...1 people from 10 data terminals, as shown in the 7th person @, each data terminal 10A to 10DK signal ADZ is transmitted from the digital exchange network 42. Sent out. Therefore, the 10 data terminals determine that there is no data collision since the received data is the same as the transmitted data, and the data terminal 10B determines that the data received from the receiving side is the data of its own address. and import subsequent data. On the other hand, since the data received from the receiving side do not match, the other data terminals 10C and IOD determine that the address is not their own and ignore the input data.

(2) When transmitting data from multiple data terminals 10A and IOB (@colliding case) The data terminal 10A is sent to Al, input 2 from the time point east in Figure 5B.
. . . A signal person D1 consisting of an input l is transmitted from a data terminal 10B from a time t to a signal B consisting of Bl, B2--Bi.
Suppose that each DI starts to be transmitted. At time 1+1 (time t, between ~1°) shown in FIG. 6B, the receiving register 61A
K stores the signal A1, the other receiving registers 61B to 61DK store the [IJ level signal, and the next time tl! The logic input signal 1 from the AND gate 62 is sent to each transmit register 63.
Stored in person~63D. Then, at the next time t's shown in figure tJLSB, this signal ADZ is sent to each data terminal 10 to 100 as shown in figure g7B.

Time t shown in FIG. 6B, (ls Time t shown in FIG. 5B,
), the reception register 61A receives signal 4, the reception register 618 receives signal B1, and the other reception register 61C
, 61DK stores the rlJ level signal, and at the next time, the AND gate 62 performs an AND operation on the values stored in each of the receiving registers 61A to 61[). Depending on this AND, the data changes to another signal X due to the influence of signal B1,
This signal X is at time t! t (FIG. 6B) is stored in each transmission register 663A to 63D. Then, at the next time point shown in FIG.
D signal X is sent to each data as shown in figure m7B.
Sent from person to IOD. Therefore, data terminal 10
10B is the signal X received at time tts in FIG. 5B.
Determine data collision from Other data terminal 10C,
It also determines that the IOD is not a signal indicating its own address and does not take in data. And data terminal 1
Person 0 and 10B enter a standby operation at the ninth point where they retransmit the data after a predetermined period of time.

In addition, instead of outputting "1" from the data terminal that has not completed all data transmission and calculating the logical product as described above, "0" is output.
Alternatively, the logic circuit 60 may perform a logical sum by outputting the following. Further, the path setting on the exchange side may be a fixed path or may be set at the beginning.

〔Effect of the invention〕

According to the present invention, a plurality of data terminals are connected in parallel to a digital exchange, and the signals of each data terminal inputted to the digital exchange are ANDed or ORed, and then each data is transmitted through the digital exchange. Since the data is transmitted to the terminal, 1:N communication between nine remotely located terminals is possible using a digital switch, and data terminals can be added or moved without interrupting data communication. It is possible to provide a switching device having a bus-type data terminal that can expand the installation area of the terminal.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the invention. Figures 1X2 to 7B illustrate one embodiment, and Figure 2 is a block diagram showing the overall configuration. FIG. 3 is a detailed block diagram of the data interface device and the line circuit for the data interface device. FIG. 4 is a diagram showing the format of signal transmission. The @5 person diagram and the @5B diagram are diagrams showing the transmission/reception status of each data terminal when there is no data collision and when there is data collision. The 6-person diagram and the 6-B diagram are diagrams showing the storage timing of the transmitting and receiving registers. FIG. 7B is a signal 7-can diagram in the case of no data collision and the case of data collision, respectively. FIGS. 8 and 9 are conceptual diagrams illustrating the conventional bus type data end unaccommodating system, respectively. 10A-10D: Data terminal 20 people ~ 20D: Data Inter 7 Ace device 30 people ~
30D: Line circuit for data interface device 40: Digital exchange 41: Multiplexer 42: Digital exchange network 43: Day multiplexer 44: Common control section 60: Digital mixing trunk 61, N to 61D: Receiving register 62: AND gate 63 people to 63D : Transmission register 100: Terminal device 112-8 1, ＼ Agent Patent attorney Igata Sada'Nimo °, ~: Principle diagram of the present invention, Figure 1 @ 1 Iris signal sequence diagram ( 1 Te bag moss 5) base −
7A Figure ≠ 95 Figure 2f 2 2n Conformity 6 Figure $9 Figure

Claims (1)

[Claims] A plurality of data terminals (10) and each data terminal (10)
), a terminal device (100) including a plurality of data interfaces (20) that transmit and receive signals and send out a high logic signal or a low logic signal when waiting for reception, a digital exchange (40), and a plurality of data interfaces. Logic means (20) that receives signals sent from the digital exchange (40), ANDs or ORs these signals, and sends them to the plurality of data interfaces (20) via the digital exchange (40). 60) A switching device having a bus-type data terminal.