JPH01145588A - Compressing device of test pattern - Google Patents

Abstract

PURPOSE:To reduce memories of a tester and to shorten a time for a test, by constructing a test pattern compressing device to be a hardware device for exclusive use. CONSTITUTION:A test pattern before compression is stored in a general-purpose memory 11 and a buffer memory 14. By a half of capacity of the memory 11, subsequently, a test pattern group to be a candidate for a subroutine is transferred to a buffer memory 12 of high speed. Next, the candidate pattern group and the test pattern in the memory 14 are compared with each other in a high-speed processing by a comparator 13 for exclusive use. The result of the comparison is recorded in a recording element 15. In this way, the reduction of memories of a tester and the shortening of a time for a test are realized.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an automatic test pattern compression device used when testing logic circuits. [Prior Art] Fig. 2 shows a conventional test pattern compression device. In the method shown in Figure 0, the device used is a general computer, not a dedicated computer. In the figure, (1) is the test pattern before compression,
(2) is a program for compression, and (3) is a test pattern after compression.

The operation of the conventional compression method will be explained. In FIG. 2, the test pattern (1) before compression is stored as a file in the storage device of the computer (6) in the figure. As an effective means for compressing this test pattern (1), a loop (
Detection (!I!A repeating pattern appears many times) Detection or subroutine (!I!A repeating pattern appears many times)
There is a detection. Detection is performed on the computer (6) using these two methods. This is the program (
This is done by software processing according to 2). The compressed test pattern (3) is output as a separate file on the same computer (6), and the location of the loop or subroutine is clearly indicated.

[The problem that the invention attempts to solve]

Conventional test pattern compression methods were configured as described above, which required a huge amount of calculation time.Unfortunately, it would not be practical to use methods such as limiting the width of the crimping loop or clearly indicating the location of subroutines. The problem was that it was not durable.

This invention was made to solve the above problems, and it is possible to detect loops without specifying the location of subroutines by limiting the width of loops in advance, and also to detect subroutines. The purpose of this invention is to obtain a test pattern compression device that can perform

[Means for solving problems]

A test pattern compression device according to the present invention performs loop detection, subroutine detection, etc. from a test pattern in a functional test of a logic circuit, and compresses the pattern.

[Effect]

The test pattern compression device according to the present invention compresses one test pattern by performing loop detection and subroutine detection using hardware. [Embodiment] An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram of the device of this invention, and the instantaneous arrows indicate the flow of data (test pattern here). In Figure 1, I is a general-purpose memory, ■ is a sub-buffer memory, and (to) is a dedicated comparison. instrument, α4 is buffer memo IJ
, (51 is a detection and recording section.

In the test pattern compression device as described above, first,
The test pattern before compression is stored in general-purpose memory 0 and buffer memory α4. Next, a group of test patterns that are candidates for subroutines are transferred to sub-buffer memory υ, which has half the capacity of general-purpose memory 0 but is faster. Subsequently, the dedicated comparator (to) compares the candidate pattern group with the test pattern in the buffer memory α station through high-speed processing.

The comparison result is recorded in the recording section (2).

In the above embodiment, the operation has been described only in the case of subroutine detection, but it is also possible to perform the same operation for loop detection, repeat (the same test pattern appears continuously) detection, or a combination thereof.

〔Effect of the invention〕

As mentioned above, with this invention, F! - By converting the test pattern compression device into a dedicated hardware device, automatic subroutine detection, which was previously impossible to perform, can be performed within a practical time. 0 which can reduce the amount of time required and test time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a test pattern compression device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional device. Dedicated comparator, α4: x 7 memory, (2
): O indicating detection and recording section

Claims (1)

[Claims] A test pattern compression device is characterized in that it automatically compresses a test pattern when executing a functional test for verifying a logic circuit that tests a logic circuit.