JPH01144396A - Drive controller for pulse motor - Google Patents

Abstract

PURPOSE:To reduce the burden of a CPU, and to drive a pulse motor at high speed by previously storing the change pattern of the number of driving pulses to a storage means such as a ROM. CONSTITUTION:The change pattern of the number of the drive of a pulse motor 8 is stored previously into a ROM 3. A CPU 1 inputs a head address selecting the change pattern of pulse number in time series driving the pulse motor 8 to a latch section of a latch and counter 2. The head address is stored in a counter section of the latch and counter 2, and a head address in the relationship of the corresponding time series of the ROM 3 and a pulse number value is assigned first. The pulse number of the head address is output at a digital value from the ROM 3, and the digital value is input to a D/A converter 4, converted into an analog value, and input to a voltage/frequency conversion circuit 5. The CPU 1 is phase-changed in response to pulses from the voltage/ frequency conversion circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a drive control device for a pulse motor that drives, for example, a mechanical part that requires high-speed performance.

(b) Prior Art Generally, when driving a machine at high speed and high torque, it is necessary to drive a pulse motor with a constant current and to control the number of applied pulses in a trapezoidal manner over time. In other words, the torque and rotational speed of the motor are in a contradictory relationship with each other, and as the rotational speed increases, the torque decreases. Therefore, when driving the motor rotation to a high continuous torque, the pulses are gradually increased from a low speed without suddenly increasing the speed. Conventionally, to perform trapezoidal control such as reducing the number of pulses to There is a 3S combination.

(c) Problems to be Solved by the Invention When performing trapezoidal control using the CPU described above, an interrupt is generated to the CPU every time a pulse is input, and if operation 1γ is to be performed to change the pulse, the interrupt processing Because it takes time, it becomes difficult to allocate time to other processes, and therefore the CP
In the case of control using U, there is a limit to the maximum frequency at which high speed can be achieved, and the maximum frequency becomes small, which poses a problem in increasing speed.

On the other hand, if a trapezoidal control waveform is output using the R1γ circuit system without using a CPU, depending on the motor, the waveform may not necessarily be a perfect trapezoid as shown in Figure 2(a).
), it may be more appropriate to output an ioB waveform such as ioB waveform, but there is a problem in that it is not possible to have delicate flexibility when the waveform output by the so-called control system becomes a stomach waveform.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a pulse motor drive control device that is capable of controlling Takatsuki high torque and having flexibility in the output trapezoidal waveform. It is said that

(d) Means and operation for solving the problem The motor drive control device of the present invention includes a storage means for prerecording a change pattern of the number of pulses input to the pulse motor over time in address sequence tα; Addressing means for sequentially specifying addresses of the storage means and outputting the 111th change pattern of the number of pulses stored in the storage means, and converting each pulse number of the output change pattern of the number of pulses into an analog (/j) A D/A converter and this D/A
A voltage/frequency conversion circuit that receives the analog voltage of the converter and outputs a pulse signal with a frequency corresponding to the output value thereof, and a CPU that outputs a signal for advancing the pulse motor by one step each time the pulse signal is received. It is composed of.

In this pulse router drive control device, a change pattern of the number of pulses is recorded in advance in a recording means such as a ROM.For example, the trapezoidal waveform shown in FIG. This pulse number variation pattern is selected by the controller, and the CPU, that is, the addressing means, specifies the start address of the pulse number variation pattern.Then, the pulse number variation pattern is sequentially output from the storage means. and this pulse value is the D/A change ta
At 23, the analog voltage (11'l') is converted into 4 signals, and the converted analog voltage is further converted into 13 pulses according to the voltage value in a voltage/frequency conversion circuit, and this pulse signal is input to the CPU. Each time the CPU receives this human-powered pulse signal, it advances the pulse motor one step and performs speed control according to the input frequency.

(B) Example The present invention will be explained in more detail with reference to Examples below.

FIG. 1 is a circuit block diagram of a pulse motor drive device showing one embodiment of the present invention. In the same figure, CPUI
Latch & Count 2 the start address that selects the change pattern of the number of pulses in the time series that drives the pulse motor 8.
The signal is input to the latch unit, and the latch unit latches it. This start address is stored in the counter section of the latch & counter 2, and first the start address of the relationship between the corresponding time series and the number of pulses 4f in the ROM 3 is specified. ROM3 outputs the number of pulses at the start address as a digital value,
This is input to the D/A converter 4, converted to an analog value, and input to the voltage /J,'i1 wave number conversion circuit 5. Then, the number of pulses corresponding to the input voltage level, that is, pulses with a frequency corresponding to the first rise in FIG. 2(a), are input to the interrupt terminal INT of the CPUI. From then on, the counter of latch and counter 2 is incremented by one step each time the clock signal is input manually, and the address of ROM3 is incremented by 1l according to the increment of 20 counter.
The number of pulses in the ROM 3 is incremented to the lith order, and the corresponding number of pulses in the ROM 3 is output as a digital value, and the D/A converter 4,
Through the voltage/frequency conversion circuit 5, a pulse with a frequency corresponding to the pulse value output from the ROM 3 is sent to the CPU
is input to the interrupt terminal rNT. In other words, CPUI
The pulses of the frequency corresponding to the change pattern of the number of pulses stored in ROM3 are respectively connected to the interrupt terminal INT.
is man-powered. Each time this pulse is input, the CPU 1 inputs it to the latch circuit 6 and drives it by the digital signal of this latch circuit. The circuit 7 advances the pulse motor 8 by one step and continues rotation for 8 consecutive times.D/A change f in Fig. 1
As shown in Figure 3 (a), it is assumed that the output of the J converter 4 is at a certain low level voltage at first, then increases at a predetermined slope, and then reaches a high level and a constant voltage level. Then, the output of the voltage/frequency conversion circuit 5 becomes
As shown in Figure (b), when the analog output is at a low level, the number of pulses is relatively small, and when the slope of the analog level increases linearly, the frequency of the pulses also increases, and the analog output When the signal is at a high and constant level, a pulse with a high frequency corresponding to the high level is output. Such a pulse signal, that is, D/
A pulse signal corresponding to the analog level output from the Ai converter 2' 44 is input to the CPUI, and the pulse motor 8 is controlled. ROM3 simply contains the data shown in Figure 2 (a).
, it is possible to record not only the waveform shown in FIG. 2(b) but also the pulse number change pattern for each 1ift, so the CPU selects which of the 35 waveforms to select and specifies the start address. It is only necessary to output a signal, and even if the drive system including the pulse motor is variously different, this can be handled.

(f) Effects of the Invention According to the present invention, the change pattern of the number of pulses for driving the pulse motor is recorded in advance in the ROM, etc. tα means ↑, α
Then, the CPU selects which pattern in this ROM and specifies the start address, and then the digital value read from ROM3 is converted to an analog value by the D/A converter LFI, and then the voltage is /Since pulses with a frequency corresponding to the number of pulses are input from the frequency conversion circuit, CP'
U changes phase 1i! according to this input pulse! 1! l
Since the negative 1u of CI'U is reduced, the pulse motor can be operated at high speed without reducing the maximum wave number. Since the change pattern of the number of pulses can be memorized,
It has the advantage of being flexible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a pulse motor drive control device showing one embodiment of the present invention, FIG. 2(a), FIG. 2(t))
3 shows a waveform diagram showing a change pattern of the number of pulses in high-speed control of a pulse motor, and FIG. 3 shows the output of the D/A converter and the number of pulses output from the voltage/frequency conversion circuit in the circuit device of the embodiment shown in FIG. 1. 3 is a waveform time chart for explaining the relationship between the two. 1: cPU, 2: latch & counter, 3: nOM
, 4: D/A converter, 5: voltage/frequency conversion circuit, 8: pulse motor. For patents) 9.1 Shimadzu Corporation Representative Patent Attorney Shigeru Nakamura Figure 1 Figure 2 (a) Figure 2 (b)

Claims (1)

[Claims] (1) A storage means for storing in advance in address sequence a pattern of changes in the number of pulses input to the pulse motor over time, and the number of pulses tα recorded in the storage means by sequentially specifying the addresses of the storage means. address designation means for sequentially outputting the change pattern of the number of pulses; a D/A converter that converts each pulse number of the output change pattern of the number of pulses into an analog value; and a D/A converter that receives the analog output of the D/A converter and A voltage/frequency conversion circuit that outputs a pulse signal with a frequency corresponding to an output value, and a C that outputs a signal for advancing the pulse motor by one step each time the pulse signal is received.
A pulse motor drive control device consisting of a PU.