JPH01144139A - Sequential address generator - Google Patents

Abstract

PURPOSE:To realize a memory access at high speed by producing the access address data to the continuous areas of a memory by performing an arithmetic operation via a processor. CONSTITUTION:A clock signal CCK is produced based on thee specific address data Xp received from a CPU 1 and an up-counter 4 and a ternary ring counter 5 have their contents varying successively based on the signal CCK. Thus it is not required for the CPU 1 to calculate the actual access address data and the sequential access address data that can be automatically changed is obtained just with output of the data Xp. Then the accesses are carried out successively to plural continuous memory areas. As a result, the time required to a memory access as a whole can be shortened.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a sequential address generation device, and more specifically, when performing sequential access to a predetermined area of memory, the present invention relates to a sequential address generation device. The present invention relates to a novel sequential address generation device for generating changing address data.

<Prior Art and Problems to be Solved by the Invention> Conventionally, in a rask scan type graphic display device, - As numerically shown in FIG. (EMP)
A segment memory (SBF) is provided which is connected to a memory management processor (IMF) via a memory management processor (IMF) and exchanges graphic data with the memory management processor (IMF).

An image processing processor (DSP) is provided which inputs the graphic data read from the segment memory (SBF) and exchanges data with the matrix processing module (MυL). The output data is supplied to the linear interpolation calculator (DDA) through the clip processor (CLIP) and the drawing processor (DPU), and the x, y coordinate data output from the linear interpolation calculator (DDA) is directly stored in the frame memory ( PM). Furthermore, the contents of the frame memory (FM) are transferred to the display device (C
RT), the graphic data is displayed visually.

By configuring the portion above the segment memory (SBF) with a normal processor and the portion below the image processing unit (DSP) with a bit slice processor, the data communication load for exchanging graphic data is reduced. The present invention is intended to reduce as much as possible, and to increase the processing speed for displaying graphic data stored in a segment memory (SBF).

In addition, in the rusk scan type intelligent graphic display device having the above-mentioned general configuration, the drawing processor (DPU) supplies data to the color look-up table (hereinafter abbreviated as LUT) in the frame memory (PM). Instead, a configuration is adopted in which the process is performed by a memory management processor (MMP) that manages a segment memory (SBF), and a drawing processor (DPU) is used to achieve high-speed coloring processing.

The operation of supplying data to the LUT by the memory management processor (IMP) will be described in detail.

First, data is supplied to the LUT using a CRT display device (not shown) to prevent display flickering.
Therefore, if the instruction execution cycle in the memory management processor (MMP) is long, little or no data is supplied during the horizontal blanking period, and the vertical Data supply during the blanking period occupies a significantly large weight. To explain in more detail, the above memory management processor (MMP)
CISC (Complicated In5
When using the LUT, it is impossible to supply data to the LUT during the horizontal blanking period because the instruction execution cycle based on software is long, and data is supplied only during the vertical blanking period. must be carried out. As a result, for example, 4
Since the number of times of vertical blanking required to supply data for 096 colors increases, it takes several seconds. There is a problem in that it takes a long time to display the image.

Furthermore, if the user specifies that the contents of the LUT be different for each displayed figure, the time required to change the displayed figure will similarly increase. .

Conversely, the RI as the memory management processor (MMP)
SC (Reduced In5tructlon)
When using Set Computer), the instruction execution cycle based on software is shortened, but in LUT, because a large number of color data are set based on the three elements R, G, and B, one When setting color data, for example, as shown in FIG. 6, R, G.

Data must be sequentially supplied to each area of B. Therefore, it is necessary to perform addressing to cycle the chip select in the order of R, G, and B without changing the lower bits of the address data, so a considerable number of steps are required for addressing. Even if the instruction execution cycle per step is short, the time required to execute instructions for the number of steps required for addressing becomes considerably long, and the overall speed cannot be increased much, so Cl5C
You will have the same problem as if you used . In other words, for each of R, G, and B, data for 4096 colors is stored, so 212 pieces of addressing need to be performed, but although there are 3 types of color elements, only 2 Addressing cannot be expressed as a power. Therefore, the processor must calculate address data corresponding to each color element, which increases the time required.

In addition, although addressing has been explained above when data is sequentially supplied to an LUT, similar problems arise when accessing hatching memory or font memory, etc. .

In other words, since the number of bits of hatching pattern data, font pattern data, etc. is significantly greater than the number of bits that can be transferred in one memory access, it is not necessary to access consecutive memory areas multiple times. However, it is necessary to calculate the access address data each time there is an access, and the time required to calculate the access address data is long, which increases the time required for the entire memory access. It's put away.

<Object of the invention> This invention was made in view of the above problems,
It is an object of the present invention to provide a sequential address generation device that can generate access address data for continuous areas of a memory without causing a processor to perform calculations.

Means for Solving the Problems> In order to achieve the above object, the sequential address generation device of the present invention is provided with initial value data from the outside and whose contents are sequentially changed every time a clock signal is supplied. and a clock generating means that generates a clock signal at a time interval determined based on the number of times the address data is supplied by receiving predetermined address data from the outside and supplies the clock signal to the counting means. There is.

However, the counting means is composed of a decoder and an n-ary ring counter, and the decoder generates a clock signal to be supplied to the ring counter every time predetermined address data is supplied from the outside, and n
It is preferable to generate a clock signal to be supplied to the counting means by inputting a signal outputted from the ring counter and predetermined address data supplied from the outside every time the clock signal is supplied.

In this case, the decoder is in an operating state in which it does not generate any clock signal in response to address data supplied from the outside, a state in which it generates a clock signal for the counting means every time address data is supplied, and n
Preferably, the state for generating the clock signal for the counting means is selected each time address data is supplied.

Further, it is preferable that the ring counter has an initial state set in advance.

Furthermore, the counting means may be an up counter.

Function> With the sequential address generation device having the above configuration, when predetermined address data is supplied from the outside to the clock generation means, a clock signal is generated at a time interval determined based on the number of times the address data is supplied, Supplied to counting means. In the counting means, the contents are sequentially changed based on the initial value supplied from the outside on the condition that the clock signal is supplied. Therefore, by outputting the contents of the counting means, the contents are sequentially changed. Changing address data, ie sequential address data, can be obtained.

The counting means is composed of a decoder and an n-ary ring counter, and the decoder generates a clock signal to be supplied to the ring counter every time predetermined address data is supplied from the outside.
If the clock signal is to be outputted from the ring counter every time the clock signal is supplied n times and a clock signal is supplied to the counting means using predetermined address data supplied from the outside as input, the external clock signal is output from the ring counter. Each time predetermined address data is supplied, the decoder generates a clock signal and supplies it to the n-ary ring counter, so the contents of the ring counter can be sequentially changed.
Each time the clock signal is supplied to the ring counter, a predetermined signal is supplied to the decoder. Then, the signal from the ring counter and predetermined address data are supplied to the decoder, thereby generating a clock signal to be supplied from the decoder to the counting means. Therefore, address data that changes sequentially can be obtained every time the predetermined address data is supplied n times.

In this case, the decoder may be in an operating state in which it does not generate any clock signals in response to address data supplied from the outside, a state in which it generates a clock signal for the counting means every time address data is supplied, and a state in which the decoder generates n-time address data. If the state is to select a state in which a clock signal is generated for the counting means each time it is supplied, a clock signal is not generated in response to address data supplied from the outside, and therefore no sequential address data is generated at all. A state in which a clock signal is generated every time address data is supplied, and sequential address data that changes sequentially in an f-to-1 relationship with the address data supply is generated, and a clock signal is generated every n address data supplies, It is possible to select a state for generating sequential address data that changes sequentially in an n:1 relationship with address data supply.

In addition, if the ring counter has an initial state set in advance (for example, a state in which the R chip select signal is output as shown in the embodiment), the timing of sequential address data generation is determined by the initial state. Sequential address data can be generated with accurate timing by eliminating the inconvenience of being affected by address data.

Furthermore, if the counting means is an up counter, it is possible to generate sequential address data that increases sequentially.

That is, when it is necessary to perform at least multiple memory accesses to multiple consecutive memory areas, the start address data of the multiple consecutive memory areas is supplied in advance to the counting means, and this state is used as a reference. When predetermined address data is supplied to the clock generation means, a clock signal is generated at a predetermined timing based on the supply of the address data and is supplied to the count means, so that the contents of the count means are sequentially increased. Therefore, by extracting the contents of the counting means, it is possible to generate a desired sequential address and sequentially access a plurality of consecutive memory areas.

<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 1 is a block diagram showing an embodiment of the sequential address generation device of the present invention, in which a central processing unit performs memory access by generating access address data, and performs necessary processing according to a procedure determined by a program. Device (hereinafter abbreviated as CPU)
(1), internal data bus ■, internal address bus ■, up counter (4) that generates sequential address data, ternary ring counter ■ that generates LUT memory chip select signal, and selects address data. Supply control signals to the selector ■, the buffer connecting the internal data bus ■ to an external data bus (not shown), the up counter (4), the ternary ring counter ■, the selector ■, and the buffer, respectively. decoder Q3).

To explain in more detail, the CPU (1) generates predetermined address data (Xp) in steps determined by the program, and generates predetermined address data (Xp) through the internal address bus G).
Send to.

The decoder 8) decodes C through the internal address bus O).
Address data (Xp
) and generates a decode signal corresponding to the up counter (
4), the ternary ring counter (2), the selector (4), and the buffer are supplied as control signals. Specifically, for example, if the address data (Xp) is L
If the value (XL) indicates that the UT (not shown) should be accessed, the address data (X
A clock signal is supplied to the ternary ring counter (5) every time the B chip select signal (BO2) (see Figure 2 H) is supplied from the ternary ring counter (5). A counter clock signal (CCK) (see Fig. 2 J) is supplied to the up counter (4), and a selection signal (S) for selecting output data from the up counter (4) is supplied to the selector ■. (8) (Fig. 2 E
). In addition, the above address data (Xp
) is a value (Xk) indicating that the font memory (not shown) should be accessed, the counter clock signal ( CCK) and a selection signal (S (8) for selecting the output data from the up counter (4) to the selector (e).
).

Further, when the address data (Xp) is a value (Xs) indicating that access to the system memory (not shown) is to be performed, output data from the selector (internal address bus C3 for e) A selection signal (S (8)) is supplied to select the buffer. By supplying an input/output enable signal to the buffer described above, data is exchanged between the internal data bus and the external data bus. let

The up counter (4) should be accessed sequentially by being supplied with initial value data (CTAD) from the CPU (1) through the internal data bus (■) while a load signal is being supplied from the decoder [F]). The start address data of the memory area is set, and then the counter clock signal (CCK) is sent from the decoder θ).
The contents are incremented by 1 each time .

The ternary ring counter (5) is set to a preset initial state (for example, a state in which the R chip select signal (RC8) is output), and then the decoder (
Every time a clock signal (RCK) (see FIG. 2) is supplied from 8), a select signal for sequentially selecting the R chip, G chip, and B chip of the LUT memory is output cyclically.

Then, the B chip select signal (BO5) is supplied as is to the decoder (2).

The selector ((5) selectively sends address data output from the CPU (1) or address data output from the up counter (4) to an external address bus (not shown).

The operation of the sequential address generation device described above is as follows.

A memory access strobe signal (ST
B) (see Figure 2 A) is output, and CP
First, from U(1), address data (Xi
), and then the address data (XL) assigned for accessing the LUT is sequentially output the necessary number of times (see FIG. 2B). Note that when performing the above operation, the LU
It outputs a Tm control signal (LUTC8) (see FIG. 2C) and a selection signal (RWC5) (see second diagram) indicating whether the access is for writing or reading data.

Since each signal is output as described above, the decoder (
A load signal is supplied from 8) to the up counter (4), and the initial value (CTAD) is supplied through the internal data bus ■.
is set.

After the initial value (CTAD) is set for the up counter (4), there is a blanking period! , at the timing detected by CPU (1).
Since the address data (XL) is output from U (1) the necessary number of times, the address data
At the timing when L is supplied, the LUT control signal (LUTC
5) and the selection signal (S (8)) are set to low level. In this state, the R chip select signal (RC8) (see Figure 2 C) is output from the ternary ring counter (5). Therefore, the initial value (CTAD) of the up counter (4) is supplied as access address data to the R chip (not shown) of the LUT memory, and the internal data bus (1), the buffer, and Data sent through external data bus (DR)
(see FIG. 2M) is written to the R chip. Next, when the same address data (XL) is supplied, the contents of the up counter (4) are held as they are, and the G chip select signal (GC (8) (second (see Figure C) is output, so for the G chip (not shown) of the LUT memory,
The initial value (CTAD) of the up counter 4) is supplied as access address data, and data (DC) is sent from the CPU (1) through the internal data bus, the buffer, and the external data bus (see Figure 2 M). is written to the G chip. If the same address data (XL) is supplied again, the contents of the up counter (4) are held as they are, and the B chip select signal (B C (8)) is sent from the three-way ring counter (5). Since the up counter (see Figure 2 C) is output, the up counter (4
) is supplied as access address data, and the internal data bus ■,
Data (DB) (see Figure 12M) of the buffer and sent out via the external data bus is written to the B chip.

After that, if the same address data (XL) is supplied, under the condition that both the memory access strobe signal (STB) and the B chip select signal (B C (8) are at low level) is satisfied. Since the counter clock signal (CCK) which becomes low level only rises, the contents of the up counter (4) are incremented by "1" (see the second figure).Then, in the same way as above, the contents of the ternary ring counter (5 ) chip select signals (RC8) (GC(8) (BC5) are output sequentially from
B) can be written.

As is clear from the above explanation, there is no need for the CPU (1) to perform any calculation operation of address data;
It is sufficient to simply output write data while outputting address data allocated for accessing the LUT, and the time required for data writing can be significantly shortened.

Therefore, the number of scan lines in the CRT display device is 1024, and moreover, there are 4 scan lines for the LUT.
When data for 096 colors is stored, by writing data during the horizontal blanking period, data writing to the LUT can be completed while displaying 4 frames. This can significantly shorten the time required from startup to graphic display, and also prevent color changes while drawing one scan line, reliably preventing flickering. Can be done.

In addition, the contents of the LUT are specified by the user, and even if a LUT with different contents is used for each figure to be displayed, the time required for the figure to actually be displayed when the displayed figure is changed. The time can be significantly reduced.

In addition, address data (Xs) is sent from the CPU (1).
is supplied, the address data (X
s) is output as is, and memory access is performed based on the access address data calculated by CPU (1).

<Embodiment 2> FIG. 3 is a block diagram showing another embodiment, and the difference from the above embodiment is that read-only memory files (hereinafter abbreviated as ROM files) (91) (92)...
- (9n) is provided to supply the sequential address data output from the up counter (4), and each ROM file (91) receives the sequential address data from the up counter (4) as input.
(92)...(9n) is provided with a decoder that supplies a selection signal, and the local data is read from each ROM file (91) (92)...(9n). Data bus (11) and internal data bus ■
The only difference is that a buffer (12) is provided, which is connected between the decoder [F] and supplied with an input/output enable signal.

Therefore, in the case of this embodiment as well, sequential access to the LUT, CPU
In addition to being able to perform memory access based on the access address data calculated in (1), ROM files (91) (92)...(
9n).

That is, ROM file (91) (92) - (9n)
When accessing the LUT, as shown in FIG. Initial settings for 4) are performed. Thereafter, it is only necessary to continuously supply the address data (Xk) from the CPU (1) to the decoder ■ instead of the address data (XL) in the above embodiment, and as shown in FIG. ) is supplied to the decoder [F]), the counter clock signal (C
CK) can be supplied to generate address data that increases sequentially by 1, and ROM file access can be performed based on the generated address data.

Therefore, for hatching pattern data, font pattern data, etc. that require at least multiple memory accesses, ROM files (91) (92)
)...Create sequential data to access (9n) and ROM files (91) (92)...
(9n) can be accessed sequentially.

In addition, Fig. 4 A, B, C, D, and E correspond to Fig. 2 A, B, respectively.
, C, D, E, and FIG. 4 F, G.

H corresponds to J, L, and M in FIG. 2, respectively.

Furthermore, as is clear from the above explanation, even when applied to a system using a ROM that requires a long access time, it is not necessary to provide a wait control circuit at all, and simply provide a NOP step in the program. The system configuration and program as a whole can be simplified.

Furthermore, in any of the above embodiments, the consumption of the address space of the CPU (1) can be significantly reduced.

It should be noted that the present invention is not limited to the above-described embodiments, and the same applies to memories other than LUTs, hatching pattern memories, and font memories that require sequential access to at least a plurality of lower levels. In addition, it is possible to use a down counter instead of an up counter depending on the memory configuration, and various other design changes can be made without changing the gist of the invention. It is possible to apply

<Effects of the Invention> As described above, this invention generates a clock signal based on specific address data output from the CPU, and is provided with a counting means whose contents change sequentially based on the clock signal. , there is no need to calculate actual access address data in the CPU, and sequential access address data that can be automatically changed can be generated by simply outputting specific address data, eliminating the need for multiple sequential accesses. This has the unique effect of significantly reducing time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the sequential address generation device of the present invention, FIG. 2 is a timing chart explaining the operation of the sequential address generation device of FIG. 1, and FIG. 3 shows another embodiment. A block diagram, FIG. 4 is a timing chart explaining the operation of the sequential address generation device of FIG. 3,
FIG. 5 is a block diagram showing a schematic configuration of a rask scan type graphic display device, and FIG. 6 is a schematic diagram showing the configuration of an LUT and the relationship between access address data. (4)... Up counter, ■... -3-way ring counter, ■... Decoder, (Xp) (XL) (Xk)... Address data, (CCK)... Counter clock signal, (
B C(8)...B chip select signal, (RCK)
...Clock signal patent applicant Daikin Industries, Ltd.

Claims (1)

[Claims] 1. Counting means (4) to which initial value data is supplied from the outside and whose contents are sequentially changed each time a clock signal (CCK) is supplied; XL
), (Xk), the clock generating means (5) (8) generates a clock signal (CCK) at a time interval determined based on the number of times of address data supply and supplies it to the counting means (4). A sequential address generation device comprising: 2. The clock generation means is composed of a decoder (8) and an n-ary ring counter (5), and
The decoder (8) receives predetermined address data (X
A clock signal (RCK) is generated to be supplied to the ring counter (5) every time the clock signal (RCK) is supplied, and a signal is output from the ring counter (5) every time the clock signal (RCK) is supplied n times. ,
and a clock signal (CCK) which is supplied to the counting means (4) by inputting predetermined address data (XL) supplied from the outside.
) The sequential address generation device according to claim 1, wherein the sequential address generation device generates the following address. 3. An operating state in which the decoder (8) does not generate any clock signals (CCK) in response to address data (Xs), (Xk), (XL) supplied from the outside, and means for counting each time address data is supplied. (4), and the clock signal (CCK) for the counting means (4) every n address data supplies.
2. The sequential address generation device according to claim 2, wherein the sequential address generation device selects the state in which the address is generated. 4. The sequential address generation device according to claim 1, wherein the n-ary ring counter (5) has an initial state set in advance. 5. The sequential address generation device according to claim 1, wherein the counting means is an up counter (4).