JPH01142011U - - Google Patents
Info
- Publication number
- JPH01142011U JPH01142011U JP3879488U JP3879488U JPH01142011U JP H01142011 U JPH01142011 U JP H01142011U JP 3879488 U JP3879488 U JP 3879488U JP 3879488 U JP3879488 U JP 3879488U JP H01142011 U JPH01142011 U JP H01142011U
- Authority
- JP
- Japan
- Prior art keywords
- processing unit
- arithmetic processing
- connects
- connector
- converts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は本考案の実施例の構成を説明する図で
、第２図は本実施例の中継装置要部の構成を説明
する図で、第３図は本実施例の中継装置の電気回
路の構成を表した図で、第４図は従来技術による
実施例の構成を示した図である。
１……供試装置（制御装置）、２……中継装置
、３……演算処理装置（ＣＰＵ）、、４，５……
専用ケーブル、６……端末機、７……ベースプリ
ントボード（入出力変換部）、７ａ……入力変換
部、７ｂ……出力変換部、８……マザープリント
ボード、９……ＤＩＮコネクタ、１０……収納ケ
ース。
FIG. 1 is a diagram for explaining the configuration of an embodiment of the present invention, FIG. 2 is a diagram for explaining the configuration of the main parts of the relay device of this embodiment, and FIG. 3 is an electric circuit of the relay device of this embodiment. FIG. 4 is a diagram showing the configuration of an embodiment according to the prior art. 1... Device under test (control device), 2... Relay device, 3... Arithmetic processing unit (CPU), 4, 5...
Dedicated cable, 6...Terminal, 7...Base printed board (input/output conversion section), 7a...Input conversion section, 7b...Output conversion section, 8...Mother printed board, 9...DIN connector, 10 ...Storage case.
Claims (1)
て、外部機器との入出力信号の正誤を試験する試
験装置において、 制御装置に入出力信号を送受してその正誤を判
定する演算処理装置と、演算処理装置と制御装置
の中間に専用ケーブルで接続した中継装置で構成
され、中継装置は送受する信号を演算処理装置の
信号レベルに変換する入力変換部および制御装置
の信号レベルに変換する出力変換部を搭載したベ
ースプリントボードと、このベースプリントボー
ドを集合接続するコネクタと専用ケーブルを接続
するコネクタを搭載したマザープリントボードを
備えたことを特徴とする試験装置。[Scope of Claim for Utility Model Registration] In a test device that connects an external device to a control device that electrically controls it and tests the correctness of input/output signals to and from the external device, It consists of an arithmetic processing unit that determines correctness and a relay device that is connected with a dedicated cable between the arithmetic processing unit and the control device.The relay device includes an input converter and a control unit that converts the transmitted and received signals to the signal level of the arithmetic processing unit. A test device characterized by comprising a base printed board equipped with an output converter that converts the signal level of the device, a mother printed board equipped with a connector that collectively connects the base printed boards, and a connector that connects a dedicated cable. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3879488U JPH01142011U (en) | 1988-03-24 | 1988-03-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3879488U JPH01142011U (en) | 1988-03-24 | 1988-03-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01142011U true JPH01142011U (en) | 1989-09-28 |
Family
ID=31265332
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3879488U Pending JPH01142011U (en) | 1988-03-24 | 1988-03-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01142011U (en) |
-
1988
- 1988-03-24 JP JP3879488U patent/JPH01142011U/ja active Pending
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