JPH01141393A - Digital clock device - Google Patents

Abstract

PURPOSE:To decrease the number of signal lines which execute connection to an external apparatus for receiving the supply of time data by outputting digital time data in a serial mode. CONSTITUTION:The parallel digital time data is generated by a time data generating means A and the time is displayed by a display means B in accordance with the time data. The parallel digital time data generated by the time data generating means B is converted by a parallel/serial converting means C to the serial digital time data which is then outputted to the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital clock device that generates parallel digital time data and displays time using the time data.

[Conventional technology]

This type of digital clock device is used, for example, in a vehicle to inform the driver of the current time on a digital display. On the other hand, vehicles such as taxis, trucks, and tanker trucks use time-series information collection devices such as tachographs, which record time-series information about vehicle travel, such as speed, mileage, and travel time. Equipment may be installed. Therefore, a system has been proposed in which a digital clock device supplies time data necessary for a time-series information collection device.

FIG. 13 shows the configuration of the proposed system. In the figure, 1 is a digital clock;
a CPU 2 that counts clock signals from a crystal oscillator (not shown) and outputs digital time data representing the current time in parallel form; a display section 3 that receives parallel digital time data from the CPU 3 and displays the time; CPU
It has an external parallel output 61 which is a branch of the two parallel outputs.

Reference numeral 50 denotes a time-series information collection device, and the time-series information collection device 50 has an input port 0 that receives and takes parallel digital time data. It is interconnected with the external parallel output 61 of clock 1.

[Problem that the invention seeks to solve]

In the conventional configuration described above, the digital clock 1 outputs digital time data in parallel from the external parallel output 61, so when supplying the digital time data from the digital clock 1 to an external device such as the time series information collection device 50, It is necessary to connect the two using a flat cable FC that has a connector CN at both ends with a large number of pins, which requires the use of expensive connectors and cables for interconnection, which increases costs and requires the placement of connectors. In addition, a large space is required to route the cables, which is not desirable from the standpoint of effective use of space.

It is also possible to provide the external device with a clock function so that the connection to the digital clock is not necessary, but in this case, two clocks would be required, which would be uneconomical.

Therefore, the present invention aims to provide a digital clock device that reduces the number of signal lines for supplying digital time data to external equipment.

[Means for solving problems]

In order to solve the above-mentioned problems, a digital clock device according to the present invention, as shown in the basic configuration diagram of FIG. display means B for displaying time based on parallel time data, and parallel-to-serial conversion means C for converting the parallel time data generated by the time data generation means B into serial digital time data; It is characterized in that the serial digital time data converted by means C is outputted to the outside.

[For production]

In the above configuration, parallel digital time data is output from the time data generating means A to the display means B for displaying time. This time data is converted into serial digital time data by the parallel-serial conversion means C and output to the outside. As a result, the number of signal lines between the external device that uses the serial digital time data and the digital clock device can be significantly reduced compared to the case where parallel digital time data is output.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the digital clock device according to the present invention, and in the figure, the same parts as those described above with respect to FIG. 13 are given the same reference numerals.

The CPU 2 included in the digital clock device 1 outputs parallel digital time data to the display section 3.
to display the current time. The CPU 2 also outputs serial digital time data, which is connected to the connector CN at both ends.
As shown in FIG. 3, the signal is inputted to an input port 32 of a time-series information collecting device 50, which includes an input section 13 and a recording section 14, through a single signal line SL having . The digital clock device 1 is incorporated, for example, in a combination meter M of a vehicle as shown in FIG. 3, and its display section 3 is arranged on the panel surface together with the meter display section.

As shown in FIG. 4, the CPU 2 includes a ROM 5 in which programs are stored, an arithmetic unit 6, a RAM 7 in which time data and time data address values are stored, a timing control unit 12 that controls the timing of a basic clock, and a display. It consists of a segment PLA 8, output ports 9 and 11, and an input port 10.

In addition, as a peripheral circuit, a display unit 3 consisting of a 7-segment LCD, VFT, etc. is connected to the output port 02, and time setting set switches SWI, SWz are connected to the human-powered boat 10 via input terminals I, L. It is connected. Further, a crystal oscillator X'tal for providing a basic clock is connected to the timing control section 12 via input terminals I3 and 14.

Further, serial digital time data is output from the output port 11 via the output terminal 01. The serial output becomes H level at the initial setting when the power is turned on.

RAM? As shown in FIG. 5(a), the time data in the box includes 4 bits of start identification data starting from the MSB,
4 bits of data, 4 bits of 10 o'clock data, 4 bits of 1 o'clock data
bit, 10 minute data 4 bits, 1 minute data 4 bits,
and 8-bit end identification data, a total of 32 pits, all of which are set to "0" during initial setting when the power is turned on. Note that the start and end identification data are data indicating the start and end of transmission of serial digital time data.

The time data stored in the RAM 7 is output from the output terminal OI as serial data every second, as shown in FIG. 5(b). Therefore, the generation time of serial data corresponding to 1 bit is 1/32 second.

Further, the time data address value stored in the RAM 7 is set to the address value of the MSB of the time data (MSB of the start identification data). In addition, each data is BCD
Set by code.

In the above configuration, the processing of the CPU 2 is shown in FIG.
This will be explained with reference to the flowchart in FIG.

FIG. 6 shows the main processing. First, initialization is performed in step S1, and the time data in RAM 7 is cleared to "0".
The output terminal OI is set to "1" (H level), and then, in step S2, the digital time data serial output subroutine shown in FIG. 7 is processed. Then step S,
The key is used to manually set the time. This process sets the current time to the time data in the RAM 7 by operating the cent switches sw, , sw. At this time, the start and end identification data of the time data are MSB of the start identification data as shown in FIG. 5(b).
is "0", and all other bits are set to "1". Also, AM/PM data is 10001” at AM.
, is set to “0000” at PM (the reverse is also possible), and 1
The 0 o'clock to 1 minute data are each set by the BCD to the times set by the set switches SW, SW2.

Next, in step S4, the set time data is
Counting is started based on the basic clock output from the timing control section 12 and the time is updated. Also AM and P
M switching is automatically updated. Next, proceed to step Ss and transfer the time data to segment PLA8 and output port 0.
Parallel digital time data is output via □, the time is displayed on the display section 3, and the process proceeds to step S2.

Next, the digital time data serial output subroutine will be explained with reference to the flowchart of FIG. First, in step SZ+, it is determined whether the time data is set in the RAM 7, and if it is not set, the process is performed in step S2.
□ sets output terminal OI to “1” via output port 11
(H level), and then in step S23 the RA
Set the time data address of M7. That is, the address value of the MSB of the time data is set as the time data address value, and the process returns to the main routine of FIG.

If it is determined in step S2I that the time data has been set, a timer is driven in step S24 based on the basic clock of the CPU 2, and it is determined whether 1/32 second has elapsed. If 1/32 second has not elapsed, the process returns to the main routine; if it has elapsed, the process proceeds to step SZS and outputs the data at the address stored in the time data address value, that is, the MSB of the time data to the 1-bit output terminal o1. .

Next, in step szi, the time data address value is decremented by 1, and then in step 52? It is determined whether the address value has been decremented by -32 from the address value of the MSB of the time data. This determination process is performed, for example, by separately storing the address data of the MSH in the RAM 7, subtracting it from the time data address value, and determining whether the difference is 32". Alternatively, the number of times the time address value is decremented is determined. You may also count the time address value. If it is decremented by -32, all 32 bits of time data have been output, and the process returns to the main routine. If it is within -32, the process proceeds to step 5211 and the time address value is incremented by -1. The address value set is set as a new time address value, and the process returns to the main routine.Steps S24 to 5ell described above
As a result of the processing, the time data in the RAM 7 is sequentially outputted from the output terminal 01 as serial digital time data as shown in Fig. 5 (Fig. 5).

The serial digital time data thus output is supplied as time data to the time series information collection device 50 via one signal line SL.

Next, the time-series information collection device 5o as an external device to which serial digital time-series data is supplied will be described.

As shown in FIGS. 3 and 8, the time-series information collecting device 50 includes a human power section 13, a recording section 14, a storage bag 15 that is detachably attached to the recording section 14, and a running sensor 1.
It consists of 6. The input unit 13 associates various states, such as working states, such as loading and unloading, with each one of the plurality of state keys 17 in advance, and selectively operates this person key 17. By doing this, you can input various states. Furthermore, by operating the mode switching key 18, it is possible to input a different state for one of the state type keys 17.

Furthermore, the input information can be displayed on the display section 20. A clear key 19 for clearing input etc. is also provided. As part of the status key, there are provided a key for distinguishing between empty and actual vehicles and a key for distinguishing whether the vehicle is traveling on an expressway or on a general road. Even if these two keys are pressed, they do not return to other state keys.

Further, a display section 23 is provided to indicate the remaining storage capacity in the storage pack 15. Further, although not shown in the figure, a power source is provided inside the device, and the recording section 14 and storage back 15 are operated by this power source.

The recording unit 14 has an insertion/removal port 24 through which a memory bag (RAM bag) 15 is inserted and removed, and when the memory bag 15 is inserted, various data from the input unit 13 and signals related to driving of the vehicle are sent from the driving sensor 16. can be stored in the memory section within the memory block. In addition, a clear display section 26 checks the remaining capacity of the memory section in the memory pack 15, and if there is no memory at all, it will display that fact, and if there is even a little memory, it will indicate that it has not been cleared. Display portions 27 displaying the following are displayed.

Further, when the eject button 25 is operated, the eject ready indicator lamp 28 is lit for a certain period of time. Further, the storage bag is configured to be locked when it is attached, and the lock is released by operating the eject button 25.

The storage bag 15 houses, for example, an 8×2.048 bit data storage section therein, and has a built-in battery that protects the stored data when the storage bag 15 is taken out from the recording section 14. Although not shown in the figure, a connector connected to a connector in the recording section 14 is attached to the back surface.

The traveling sensor 16 generates a pulse when the vehicle travels a unit distance and supplies it to the recording section 14 .

FIG. 9 shows an example of the electrical configuration of such time-series information collecting device 50, and the input section 13 is equipped with a microcomputer (hereinafter referred to as C
(referred to as PU) 31 is provided. Vehicle mounted battery 39
The power is received from the charging circuit 37, and the power supply control circuit 35 charges one of the two batteries V□, Vl12, and the other supplies operating power to various parts, and the two batteries V□, Vl
□ is used by switching. An input port 32 for receiving serial time data output from the digital clock 1 is connected to the CPU 31, and a ROM 36 in which a vehicle code is stored is also connected. Furthermore, the key operation unit 34 such as the various keys 17, 18, and 19 described in FIG.
1, various processes are performed according to the state input, and a display corresponding to the input is performed by a light emitting diode or the like, and these are collectively referred to as a display section 33.

The CPU 31 manually controls the on/off state of the ACC switch in the engine switch of the vehicle, that is, the switch SW3 that operates as a switch that supplies power to a radio or other device other than the main functions of the vehicle when the engine is not running. When the switch SW3 is on, the display of each light emitting diode on the display section 33 is displayed continuously, but when this switch SW3 is off, the vehicle battery 39
The lights should be on for about 10 seconds to protect the lights. Also, when the vehicle's light switch is turned on, this is input to the CPU 31 through the switch SW4, and in this case, the display unit 20.
The display brightness of 33 is lowered to make it easier to see.

Similarly, the recording unit 14 is also provided with a CPU 40. This CPU 40 can also be used as the CPU 31. The CPU 40 is connected to the CPU 31 of the input unit 13, and can exchange data with each other.
As described in FIG. An alarm buzzer 44 is connected to notify the state that the capacity is running out. Furthermore, when the operation of the pack ejection button 25 is input to the CPU 40 and the ejection button 25 is operated, the monostable multivibrator 41 is driven, and its output drives the pack lock release section 42 for a certain period of time, and the storage pack 15 is released. The lock status is released.

Furthermore, the signal from the running sensor 16 is sent to a running signal generation circuit 45.
The signal is then input to the CPU 40. CPU
The memory pack 15 is detachably connected to the memory pack 40 . Power for each CPU of the input section 13 and recording section 14 is supplied from a power supply control circuit 35, and other power for each display section and the like is supplied from a battery 39 via a display power supply circuit 38.

When an operator operates a status key or the like, the CPU 31 of the input unit 13 lights up a display element corresponding to the operation, stores status data for the status key, and transmits it to the CPU 40 of the recording unit 14. It also transfers time data received by the input boat 32 to the recording unit 14. memory pack 1
5 is detected by the CPU 40, this data is transmitted to the CPU 31, and displayed on the display section 23.

In the recording unit 14, when the memory pack 15 is attached, the CPU 40 stores predetermined item data in the memory pack 1.
Write within 5. For example, pack insertion code, and ROM3
6, the vehicle code, month, date, and time are written. If the time is corrected before the pack is installed, the clock correction flag bit is written when the pack is set. Furthermore, CPU4
0 writes state data such as the operation state of the keys of the input section 13 and the vehicle stoppage state to the storage section in the memory pack 15 every 30 seconds from the state that the memory pack 15 is attached. In addition, 1cPU40 accumulates the mileage and time from when the memory pack 15 is attached to when it is removed.
The cumulative amount is calculated by actual and empty vehicles, and by highways and general roads. Therefore, the RAM in the CPL 140 is provided with separate counters for each of these accumulations. When the storage pack 15 is removed, these cumulative values are dented into the storage section of the storage pack. Also, at the time of removal, other predetermined item data, such as a code indicating removal, date, time, etc., are recorded.

In addition, in the running signal generation circuit 45, 15 out of 30 seconds
If there is a running pulse for more than a second, it is determined to be running, and the judgment data and pulse information generated for each unit distance are stored in the CP.
Supplied to U40. The CPU 31, which judges the presence or absence of a running pulse every second, and the CPU 40 of the recording section are initialized when the memory pack 15 is inserted and when the eject button 25 is operated. When the memory pack 15 is inserted, all RAM except the CPU flag area is
The area is cleared and the data of each item at that time is written. When the eject button 25 is pressed, the data at that time is first written and then the CPU is initialized. After this initialization, the RAM is cleared except for the flag area.

As mentioned earlier, the CPU 40 of the storage unit 14 stores the keys operated by the input unit 13, vehicle codes, data in the storage unit, and clock data in chronological order, that is, over a certain period of time, in the storage unit of the memory pack 15. It is stored sequentially as data for each vehicle or as a distance series, that is, data for each fixed distance traveled by the vehicle. The format for writing data to this storage pack 15 is, for example, as follows.

That is, as shown in FIG.
AMI to RAM8 are formed, among which RAM
I to RAM3 are memories that sequentially store the serial time data shown in FIG. 10(b), and RAM4 is a memory that stores the serial time data shown in FIG.
Memory for setting $B (1 bit each) and variable n (5 bits). Also, RAM5 to RAM7 are RAM
This is a memory for setting the time data stored in the RAM 3, and the serial time data in FIG. 10 (tl) is the serial time data output from the digital clock device l shown in FIG. Of these, PM/AM data and 10:00 to 1 minute data are shown.

On the other hand, in the diagram, 8-bit parallel information data is stored in RAM 8. Each bit of the data is given a meaning to identify the state based on various vehicle information. For example, in the stopped state in MSB, “0”
”, it is “1” when the vehicle is running, the second bit is “1” if the vehicle is empty, and “1” is the actual vehicle.The third bit is “1” when the vehicle is overspeeding, and “0” when the vehicle is at normal speed. shall be. Such information data is set by the operation of the key operation section 34 or the detection output from the travel sensor 15. The information data of this RAM 8 is read out every 30 seconds, and it is determined whether there is a change in the contents. If there is a change, it is because the vehicle information has changed.
The time data at that time is transferred to the RAMs 5 to 7 in the figure, and the changed information data and the time data at that time are set in the RAMs 5 to 7 and 8. This is output to the storage pack 15 and stored at a predetermined address in the ROM provided in the pack 15. Note that since each RAM 1 to 8 has 8 bits, 4 bits of start identification data are also included, but this is not directly related to the processing of the CPU.

In the above configuration, the processing of CPU31.40 is
This will be explained with reference to the flowchart in FIG. FIG. 11 shows the main processing. First, in step S1 initialization is performed and RAMI to 8 are cleared. Next, Figure 10 (bl
The serial-to-parallel conversion subroutine for converting serial time data to parallel time data shown in FIG. The serial time data as shown in Figure 5 (bl) output from the CPU is
Convert to parallel time data so that 31.40 can be processed. Next, in step S, parallel information data such as start and end of running is stored in other RAMs of the CPUs 31 and 40.
In step s4, it is determined whether the parallel information data has changed. If it has changed, step S
5, the parallel information data is set in the RAM 8, and if it has not changed, step S is skipped and step S continues.

Determine the capacity of the memory pack (ROM card) 15 by
If there is no storage capacity, the display section 26 is turned on in step S to inform the operator that the storage pack 15 has no capacity. If there is capacity, the process proceeds to step S8, where it is determined whether the capacity is less than 1/2 of the total, and 1
/2 or less, the display section 27 is turned on in step S. When the capacity is 1/2 or more, and after the display unit lighting process in step S9, in step SIO, the memory pack 15
The parallel information data set in the RAMs 5 to 8 and the time data at that time are stored in the area of the memory pack 15 at the set address in step S11. Through this processing, states such as start, end, overrun, overspeed, etc. are stored in the memory pack 15 in chronological order.

Next, the serial-to-parallel conversion subroutine of step S2 will be explained with reference to the flowchart of FIG. First, in step SK+, the state of flag A in the RAM 4 is determined, and if it is not "0", the process advances to step S219. If it is "O", the state of the flag B is determined in step s2□, and if it is not "0", the process proceeds to S29, and if it is "0", in step S23, the MSB in the serial time data of is "0" as described above, so this is performed to detect the MSB. If a falling edge is not detected, the process returns to the main routine, and if a falling edge is detected, one RAMI and 2 are cleared in step S24, and then the timer is driven based on the basic clock of the CPU in step SZS.

Next, in step 52&, it is determined whether the timer has elapsed for 1764 seconds. This process sets an intermediate value with respect to the time axis of the MSB occurrence period (1/32 second) in the data for each start a.

If l/64 seconds have not elapsed, return to the main routine,
If the time has elapsed, the flag B is set to "1" in step Sa7. Next, in step 5zll, the first data of the serial time data (MS of start identification data)
B) is set to the MSB of RAMI (RAMI-1).

Then, at step sgq, n=7, and at step SKI
. It is determined whether the timer has passed 1/32 seconds. This process determines the intermediate value on the time axis of the serial time data generation period (1/32 second), that is, the point at which 1764 seconds have elapsed from the time of generation. If 1/3 second has not elapsed, return to the main routine; if it has elapsed, proceed to step 5.
2II corresponds to serial time data. RAM1
is stored in each bit (RAMI-2 to RAMI-8).

Next, in step S2, 2, n is -1, and step S2.
3 to determine whether n=0. If n = 0, all 8 bits of RAMI have not stored serial time data, so return to the main routine, and if n = 0, R
Since 8 bits of serial time data (start identification data and PM/AM data) have been stored in AMI, flag B is reset to "O" in step 5214), and the set state identification of RAMI is canceled. Next, step S2. , and S2+&, it is determined whether the start identification data and the P M/A M data are normally stored in the RAMI. That is, if AM data is stored, "70H" (01110000) is set in RAMI, and if PM data is stored, "71" is set in RAMI.
H" should have been set, so if the RAMI data is not both values, the process returns to the main routine. If either value is set, flag A is set in step 5217, and step S2, 8 cents n=16.

Next, step S21. It is determined whether the timer has passed 1/32 seconds. Similar to step S210, this process sets a time 1/64 seconds after the generation of the serial time data, that is, an intermediate time with respect to the time axis of the data. Next, step S2□. The serial time data at the intermediate time is read by RA.
Sequentially stored in M2.3.

Next, in step S2□1, n is -1, and in step S2□
2, it is determined whether n=0. RA if n=o
Since all 16-bit serial time data is not stored in M2 and M3, return to the main routine and set n=0.
If so, all 16 bits of serial time data have been stored in the RAM 2.3, so the process proceeds to step S2□3, where the driving of the timer is stopped and the counting of the basic clock is stopped.

Next, in step S2□4, the contents of RAM1 to 3 and the RA
Compare the contents of M5 to M7, and if they do not match, return to the main routine, and if they match, proceed to step Szzs
Save the time data set in RAMI to 3 by
Load from 5 to 7. As a result, parallel digital time data that can be processed by the CPUs 31 and 40 is set in the RAMs 5 to 7. In this way, various types of vehicle information are stored in the memory pack 15 in chronological order.

Although a time-series vehicle information collection device is exemplified as an external device, other external devices that require time data may be used.

〔effect〕

As described above, according to the present invention, digital time data is output in serial form, so the number of signal lines for connection with external equipment receiving the time data is reduced, and connection is facilitated.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the basic configuration of the present invention, Figure 2 is a schematic diagram of the main parts of the digital clock device and time-series vehicle information collection device according to the present invention, and Figure 3 is an embodiment mounted on a vehicle. 4 is a block diagram showing an example of the configuration of the CPU of the digital clock according to the present invention, and FIG. 5(a) and To) are the RA of the CPU in FIG.
FIG. 6 and FIG. 7 are flowcharts showing the processing performed by the CPU in FIG. 4, respectively. FIG. Figure 9 is a block diagram showing an example of the configuration of the equipment in Figure 8; Figure 10 (al, bl is the RAM of the CPU in Figure 9).
and a diagram showing input serial digital time data, No. 11
12 are flowcharts showing the processing performed by the CPU of FIG. 9, and FIG. 13 is a block diagram of the main parts of a conventional digital clock and time-series vehicle information collection device. 1...Digital clock device, A...Time data generation means (CPU2), B...Display means (display part)
, C...parallel-serial conversion means (CPU2). Patent applicant Yazaki Sogyo Co., Ltd. 1 Figure 2 Figure 8 Figure 5 Figure 6 Figure 7 Figure 10

Claims (1)

[Scope of Claims] Time data generation means for generating parallel digital time data; display means for displaying time based on the parallel time data generated by the time data generation means; and parallel time generated by the time data generation means. A digital clock device comprising: parallel-to-serial conversion means for converting data into serial digital time data; and outputting the serial digital time data converted by the parallel-to-serial conversion means to the outside.