JPH0113456Y2 - - Google Patents
Info
- Publication number
- JPH0113456Y2 JPH0113456Y2 JP13338482U JP13338482U JPH0113456Y2 JP H0113456 Y2 JPH0113456 Y2 JP H0113456Y2 JP 13338482 U JP13338482 U JP 13338482U JP 13338482 U JP13338482 U JP 13338482U JP H0113456 Y2 JPH0113456 Y2 JP H0113456Y2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- circuit
- switch
- capacitor
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000003321 amplification Effects 0.000 claims description 5
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005389 magnetism Effects 0.000 description 1
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
【考案の詳細な説明】
本考案は音響機器に組込まれる音響効果増幅回
路に係り、グラフイツクイコライザとトーンコン
トロールの機能を1つの増幅回路に持たせたもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sound effect amplification circuit incorporated in audio equipment, in which the functions of a graphic equalizer and a tone control are provided in one amplification circuit.
グラフイツクイコライザあるいはトーンコント
ロールはそれぞれ独立した音響増幅器であり、従
来、これら2つの機能を装備するには大幅は価格
上昇が見込まれていた。 A graphic equalizer or tone control is each an independent audio amplifier, and in the past, it was expected that the price would increase significantly to provide these two functions.
本考案は簡単な素子を追加するだけでグラフイ
ツクイコライザの機能およびトーンコントロール
機能を持たせることが可能となる音響効果増幅回
路を提供することを目的とする。 An object of the present invention is to provide a sound effect amplification circuit that can have a graphic equalizer function and a tone control function by simply adding simple elements.
以下本考案を図面に示す実施例により説明す
る。増幅器A1の非反転入力端子は抵抗R1を介
して入力端子INに接続され、反転入力端子は互
いに並列に接続された2個以上(図示例では2
個)の可変抵抗VR1,VR2を介して非反転端
子に接続され、かつ抵抗R2を介して出力端子
OUTに接続されている。可変抵抗VR1,VR2
の中間部はそれぞれ回路1,2を介して接地され
ており、摺動子3,4と接地との間には、それぞ
れ、コンデンサC1,C3と、連動するスイツチ
S1,S2と、抵抗R5,R8と、半導体インダ
クタL1,L2とが設けてある。半導体インダク
タL1,L2は、それぞれ、コンデンサC2,C
4および抵抗R4,R7からなるRC回路と、抵
抗R6,R7と、演算増幅器A2,A3とからな
り、インダクタンス素子と同様の作用をなすもの
である。 The present invention will be explained below with reference to embodiments shown in the drawings. The non-inverting input terminal of the amplifier A1 is connected to the input terminal IN via the resistor R1, and the inverting input terminal is connected to two or more inverting input terminals connected in parallel to each other (in the illustrated example, two or more
) is connected to the non-inverting terminal via variable resistors VR1 and VR2, and is connected to the output terminal via resistor R2.
Connected to OUT. Variable resistance VR1, VR2
The middle portions of are grounded via circuits 1 and 2, respectively, and between the sliders 3 and 4 and the ground, there are capacitors C1 and C3, interlocking switches S1 and S2, and resistors R5 and R5, respectively. R8 and semiconductor inductors L1 and L2 are provided. Semiconductor inductors L1 and L2 are connected to capacitors C2 and C, respectively.
4 and resistors R4 and R7, resistors R6 and R7, and operational amplifiers A2 and A3, and performs the same function as an inductance element.
この回路において、いま、スイツチS1をイン
ダクタL1側に接続した場合には、スイツチS2
は抵抗R8を短絡した接続位置となり、第2図の
ように、可変抵抗VR1の摺動子3と接地との間
にコンデンサC1とインダクタL1とが挿入さ
れ、可変抵抗VR2の摺動子4と接地との間にコ
ンデンサC3とインダクタL2とが挿入された回
路が形成される。すなわち、第4図の鎖線に示す
ように、C1とL1、C3とL2の容量、インダ
クタンスによつて決定される周波数においてピー
クをもつたグラフイツクイコライザとして機能す
る回路が形成される。 In this circuit, if switch S1 is connected to the inductor L1 side, switch S2
is the connection position where resistor R8 is short-circuited, and as shown in Fig. 2, capacitor C1 and inductor L1 are inserted between slider 3 of variable resistor VR1 and ground, and the slider 4 of variable resistor VR2 and A circuit is formed in which a capacitor C3 and an inductor L2 are inserted between the ground and the ground. That is, as shown by the chain line in FIG. 4, a circuit is formed that functions as a graphic equalizer having a peak at a frequency determined by the capacitance and inductance of C1 and L1, and C3 and L2.
一方、スイツチS1を抵抗R5側に切換えた際
には、スイツチS2はコンデンサC3を短絡する
ように切換わり、第3図に示すように、可変抵抗
VR1の摺動子3と接地との間にコンデンサC1
と抵抗R5が挿入され、可変抵抗VR2の摺動子
4と接地との間に抵抗R8とインダクタL2とが
挿入された回路が形成される。この場合は、コン
デンサC1と抵抗R5の作用により高域側に高い
レスポンスを持つ特性が得られ、抵抗R8とイン
ダクタL2との作用により低域側に高いレスポン
スを持つトーンコントロールとしての第4図の実
線のような特性を持つ回路となる。 On the other hand, when the switch S1 is switched to the resistor R5 side, the switch S2 is switched to short-circuit the capacitor C3, and as shown in FIG.
Capacitor C1 between slider 3 of VR1 and ground
A circuit is formed in which a resistor R5 and a resistor R5 are inserted, and a resistor R8 and an inductor L2 are inserted between the slider 4 of the variable resistor VR2 and the ground. In this case, due to the action of capacitor C1 and resistor R5, a characteristic with a high response on the high frequency side is obtained, and due to the action of resistor R8 and inductor L2, a tone control with a high response on the low frequency side is obtained. The result is a circuit with characteristics as shown by the solid line.
以上述べたように、本考案の音響効果増幅回路
は、スイツチの切換えによつてグラフイツクイコ
ライザの機能とトーンコントロール機能とが実現
できるようになし、基本となる回路は一種だけと
したので、簡単な構成で安価に目的とする2つの
機能を得ることができる。また、インダクタを半
導体により構成したので、ハム等の磁気の影響を
受けることがなく、スペースフアクタも良いとい
う長所がある。 As mentioned above, the sound effect amplification circuit of the present invention can realize the graphic equalizer function and the tone control function by switching the switch, and since it uses only one type of basic circuit, it is easy to use. The two desired functions can be obtained at low cost with a simple configuration. Furthermore, since the inductor is made of a semiconductor, it has the advantage of not being affected by magnetism such as hum, and of having a good space factor.
第1図は本考案の一実施例を示す回路図、第2
図および第3図は該回路のスイツチ切換えによつ
て実現される回路図、第4図は第2図および第3
図の回路の特性図である。
A1〜A3……増幅器、C1〜C4……コンデ
ンサ、L1,L2……半導体インダクタ、R1〜
R8……抵抗、VR1,VR2……可変抵抗。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
3 and 3 are circuit diagrams realized by switching the circuit, and FIG. 4 is a circuit diagram realized by switching the circuit.
FIG. 2 is a characteristic diagram of the circuit shown in FIG. A1-A3...Amplifier, C1-C4...Capacitor, L1, L2...Semiconductor inductor, R1-
R8...Resistor, VR1, VR2...Variable resistor.
Claims (1)
の非反転入力端子及び反転入力端子間に並列接続
された、中間部が接地された2個の可変抵抗と、
前記一方の可変抵抗の摺動子と接地間に、第1の
コンデンサと第1の半導体インダクタの直列回路
または前記コンデンサと第1の抵抗の直列回路を
切り替え接続するための第1のスイツチと、該第
1のスイツチと連動して、前記他方の可変抵抗の
摺動子と接地間に、第2のコンデンサと第2の半
導体インダクタの直列回路または第2の抵抗と第
2の半導体インダクタの直列回路を切り替え接続
するための第2のスイツチとを備え、スイツチの
切替えによりグラフイツクイコライザ機能または
トーンコントロール機能を有する様に構成したこ
とを特徴とする音響効果増幅回路。 an amplifier that non-inverts and amplifies an input signal; two variable resistors connected in parallel between a non-inverting input terminal and an inverting input terminal of the amplifier and whose intermediate portions are grounded;
a first switch for switching and connecting a series circuit of a first capacitor and a first semiconductor inductor or a series circuit of the capacitor and a first resistor between the slider of the one variable resistor and ground; In conjunction with the first switch, a series circuit of a second capacitor and a second semiconductor inductor or a series circuit of a second resistor and a second semiconductor inductor is connected between the slider of the other variable resistor and the ground. 1. A sound effect amplification circuit comprising a second switch for switching and connecting the circuit, and configured to have a graphic equalizer function or a tone control function by switching the switch.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13338482U JPS5936614U (en) | 1982-09-01 | 1982-09-01 | sound effect amplification circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13338482U JPS5936614U (en) | 1982-09-01 | 1982-09-01 | sound effect amplification circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5936614U JPS5936614U (en) | 1984-03-07 |
JPH0113456Y2 true JPH0113456Y2 (en) | 1989-04-20 |
Family
ID=30300897
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13338482U Granted JPS5936614U (en) | 1982-09-01 | 1982-09-01 | sound effect amplification circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5936614U (en) |
-
1982
- 1982-09-01 JP JP13338482U patent/JPS5936614U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5936614U (en) | 1984-03-07 |
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