JPH01133488A - Reproducing device - Google Patents

Abstract

PURPOSE:To improve the method for use by executing the prescribed skew compensation automatically when a video signal is not recorded for a block reproduced continuously with a first field and a second field. CONSTITUTION:A reproducing device includes a reproducing signal supplying part 100, a luminance signal extracting part 101 and a color difference signal extracting part 102. A field index detecting circuit 10 at the luminance signal extracting part 101 detects that the field index of the reproducing signal is not changed and by executing the skew compensation based on the detecting output, the synchronizing phase of the output is always stably correctly maintained.

Description

Detailed Description of the Invention [Field of Application in the Ea Industry] The present invention relates to a playback device, for example, a playback device that constantly synchronizes a medium such as a still video (SV) in which recording is performed on each track in units of fields. It is designed to perform correct reproduction while maintaining signal continuity.

[Prior Art J] As shown in FIG. 2, an example of a conventional device of this type is, for example, in the case of field playback in which the same track on a disk is repeatedly played back, 180° offset occurs in the vertical synchronization signal at the rising point of the PG pulse. Therefore, a %H delay line (OL) 22 is used, and the %HDL 22 is generated every time the disk goes around at the PG pulse. A switch 23 switches between a signal that does not pass through and a signal that passes through HDL 22 to maintain the continuity of the synchronization signal. Also, 2
In the case of frame playback, in which signals from two tracks are played back alternately, the two tracks are usually frame recording signals recorded continuously, and the playback signal is output as is, assuming that there is no phase offset in the synchronization signal. There is.

[Problems to be Solved by the Invention] In the above-mentioned conventional example, data is continuously recorded on two tracks, one track has a 0DD (first) field, and the other has an EVEN (second) field. This was done on the assumption that each field was recorded. However, in reality, when comparing detailed parts of two images or using them as special effects, the still video recorder is forced into frame mode and two completely unrelated images are recorded one field at a time. It is required that they be displayed alternately. therefore,
Both images may be recorded only in the first field,
Alternatively, if only the second field is recorded, there is a drawback that skew (image disturbance) occurs at the top of the reproduced screen.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks so that the signals of two adjacent tracks can be
It is an object of the present invention to provide a reproducing device which can always maintain the continuity of a synchronizing signal and reproduce good images regardless of the combination of fields.

[Means for Solving the Problems] In order to achieve such an object, in the present invention, two reproduced field signals are divided into the first field and the second field.
Detect the combination of fields,
Thereby, it is possible to select whether or not to perform compensation by %H delay.

That is, the present invention provides a reproducing means for reproducing a designated block of a video signal recorded field by field in each storage block of a recording medium;
A setting means for setting frame playback, and when frame playback is set by the setting means, the first field and the second field are not recorded consecutively in the block played by the playback means. In some cases, it is characterized by comprising means for performing predetermined skew compensation.

[Function] According to the present invention, the fields of adjacent tracks are
and a repetition of the second field, or a repetition of either the first or second field, and the detection signal determines that if the field is the first and second repetition, the reproduction is performed. The signal can be extracted as is, or if the field is either the first or second repetition, the reproduced signal and the signal delayed by 34H can be switched and extracted for each field.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In the figure, 100 is a reproduced signal supply section, 101 is a luminance signal extraction section, and 102 is a color difference signal extraction section.

First, the luminance signal extraction unit 101 of this embodiment, which best represents the features of the present invention, will be described. 1 is the playback signal YPB
This is an input terminal for inputting a reproduced luminance signal with a synchronization signal that has been reproduced and demodulated from a magnetic recording medium and has been subjected to processing such as dropout compensation. Reference numeral 2 denotes a PG pulse input terminal, through which PG pulses indicating start and end timings during field signal recording are manually input. P for frame playback
By switching the tracks of the reproducing head at the timing of the G pulse, the signal for one frame can be reproduced from two tracks without disturbing the synchronization signal.

3 is a V pulse input terminal, which includes Vsync (vertical synchronization signal), and IH to 2H before and after Vsync, respectively.
A long V pulse is input. The opening/closing of the switch (SW) 20 is controlled at the timing of the V pulse described above, and the IHDL (1 horizontal scanning period [-= 8
3.556 μsec] Add the outputs of delay line) 18 or stop the addition. 4 is an input terminal for a control signal that distinguishes whether playback is in field mode or frame mode, and controls SWI 9 depending on whether only one track or two tracks are being played. High, and Low when two tracks are played back alternately. 5 is the final output luminance signal.

10 is a field index (Fl) detection circuit, which separates horizontal synchronization and vertical synchronization of the synchronization signal added to the reproduced luminance signal manually inputted from the input terminal 1;
By comparing the phase of the vertical synchronization signal and the phase of the horizontal synchronization signal, a low signal is output for the first field, and a high signal is output for the second field. 11 is D-FF
(flip-flop) circuit, Fl detection circuit lO
The field index circuit IO detects the ODD and EVEN of the reproduced luminance signal input by inputting the V pulse input from the input terminal 3, and connects the output to the delay line (DL) 25 for a sufficient period of time to output the result. 12 is a D-FF circuit; D-FF
The positive output of the circuit 11 is read with the same pulse as the D-FF circuit 11 described above.

13 is an EX-NOR (exclusive negative OR) circuit;
The Q outputs of the two D-FF circuits 11 and 12 are input. 14 is a D-FF circuit, which outputs a signal Q that is inverted every time the PG pulse from the input terminal 2 is inputted manually. 15 is an AND circuit, which manually inputs the output signal of the D-FF circuit 14 and the output signal of the EX-NOR circuit 13.

16 is an AND circuit, which inputs the output of the AND circuit 15 and the pulse inputted from the input terminal 3 manually. The output of the AND circuit 16 controls a switch 23, which will be described later, and when both inputs are lligh, that is, the signal to be reproduced is always only one field, and the output of the D-FF circuit 14 is on the high field side. In addition, in the case of a portion other than the V pulse section, the switch 23 is set to the old gh side, that is, the %H delay line output, which will be described later, is selected as the final output. 17 is an AND circuit which manually inputs the V pulse input from the input terminal 3 and the field/frame No. 48 input from the input terminal 4. The output of the AND circuit 17 controls 5W2G and is switched (SW) only when playing one track and only when it is not in the V pulse section.
20 is closed and the adder 21 performs interpolation.

18 is an IH delay line (IHDL), which transmits the reproduced brightness signal input manually from input terminal 1 to the IH section (63, 5
56μ5ec). Reference numeral 19 is a switch, which connects the reproduced brightness signal input from input terminal 1 and the above-mentioned IH.
In the case of a frame (control signal: Low), the luminance signal manually input from input terminal 1 is selected and output, and in the case of a field (control signal: )Iigh), the output signal of the IHDL18 is input. Select and output. 20 is an on/off switch that determines whether or not to send the output of 1) the IDL 18 to an adder 21, which will be described later;
It is made conductive only when the control signal from the input terminal 4 is High. 21 is an adder, which connects the reproduced brightness signal inputted from input terminal 1 and the open/close switch 20.
and the output signal of

22 is! 14 HDL, 54 H (31,778
μ5ec). 23 is a two-man SW that selects the final output signal, and when the control signal is Low, the output signal of 5W19 is selected, and when the control signal is Low, the output signal of 5W19 is selected.
In this case, the output signal of the station HDL 22 is outputted to the output terminal 5 as the final output. 24 is a NOR (Negative OR) circuit, and when the output of the above-mentioned AND circuit 15 is Low (the phase of the horizontal synchronization signal of the reproduction signal input to the input terminal 1 and the output signal output from the output terminal 5 is if it matches)
The flip-flop circuit 14 is reset in synchronization with the output of 0L25, which will be described later. 25 is DL (delay line),
The input VD signal is delayed for a certain period of time at least until after the Fl detection circuit outputs the detection result.

In other words, this NOR always resets the 14 flip-flops when the reproduced signal is a frame, and resets it once every 1 frame (2 field reproduction) when the reproduced signal is a frame. Distortion of playback output image due to switching (ODD-0
It works to prevent the same signal from being output for two consecutive fields, such as 09.

In other words, regarding the operation of DL No. 25, this DL finishes reading the field index (ODD of the field,
11 until the end of determining EVEN and outputting the result)
It functions to delay the reading clock of the flip-flop 12, and further functions to reset the flip-flop 14 after the flip-flop 11 reads the ODD and EVEN determination results of the field being reproduced at that time.

Next, the reproduced signal supply section 100 of this embodiment will be explained. 30 is a video floppy disk, on which video signals are formed on concentric tracks. A PG detector 32 detects a PG bin embedded in the video floppy disk 30. 34 is a motor that rotates the video floppy disk 30.

35A and 35B are playback heads, 36 is a Y process circuit, and 37 is a switch. 3
8 is a V separation circuit which separates and extracts the vertical synchronizing signal from the output of the Y process circuit 36.

40 is a DPSK demodulator which extracts a predetermined frequency component from the output taken out via the switch 37 and converts it into a DPSK demodulator.
By performing SK demodulation, it is determined whether the recorded video signal is a field video signal or a frame video signal. A BPF 42 extracts a portion related to the chroma (color signal C) component from the output from the switch 37. 44 is a C process circuit, which processes the output of the BPF 42.

46 is a T flip-flop circuit, and the PG detector 32
The phase of the output is inverted according to the output of 48 and 50
is an AND gate, 51 is an inverter, and 52 is an OR gate. When the output of the OR gate 52 is "High", the switch 37 is connected only to the terminal of the playback head 35^, for example, and when "LO!IT" Switch 37 is connected to a terminal of playback head 35B. Therefore, in order to alternately switch the signals from the reproduction heads 35A and 358 for each field, when the AND gate 48 is active, the signals are alternately switched and outputted by the switch 37.

57 is a controller, and gates 48 and 5
Generates a signal to control 0. 59 is a switch for specifying frame playback, and 61 is a switch for specifying field playback. Reference numeral 62 denotes a switch for specifying automatic mode, which automatically switches between field reproduction and frame reproduction in accordance with the reproduced In (index) signal. When field playback is specified, the controller 57 outputs “
If frame playback is designated, outputs "Low".

Furthermore, the color difference signal extraction unit 102 of this embodiment will be explained. Reference numeral 6 denotes an input terminal to which the color difference signals R-Y and B-Y taken out from the C process circuit 44 are formed line-sequentially and inputted. 7 is an output terminal for taking out the color difference signal RY, and 8 is an output terminal for taking out the color difference signal B-Y. 7
1 and 73 are IHDLs, and 75 is an adder. 76
A and 76B are interlocking switches, and interlocking switch 7
6A selects the output of the adder 75, the interlock switch 76B selects the output of the IHDL 71, and when the interlock switch 76A selects the output of the IHDL 71, the interlock switch 76B selects the output of the adder 75. and remove it. 77 and 79 are %HDL.

78A and 78B are interlocking switches, and color difference signals RY and II are controlled by the output of the AND circuit 16 and taken out from the interlocking switches 76A and 76B.
-Y to 34 by y211DL77 and 79 respectively
Select whether to delay H or take it out as is.

FIG. 3 is a circuit diagram showing another example of the color difference signal extraction section 102 described above. In the figure, the same parts as those in the color difference signal extracting section 102 shown in the first figure are given the same reference numerals, and the explanation thereof will be omitted. 80 is a y2HDL, 81 is a switch, and the switch 81 determines whether the color difference signals R-Y and Y, which are formed line-sequentially and manually input, are delayed by %H by the %HDL 80 or taken out as they are. Control and select by output.

According to the circuit shown in FIG. 3, only one % HDL is required.

From the above, for example, when playing in frame mode, the luminance signal Y and color difference signal C (R-Y and B-Y
) will be relatively shifted by IH, but for this reason, if the luminance signal Y is passed through the IH delay line, the signal will deteriorate, so it is better to leave the luminance signal Y as it is to obtain a higher quality image.

Next, the operation will be explained by taking an example of a case in which it is specifically used.

[I] When reproducing only one track (when field reproduction is specified) In this example, only one field is reproduced, so the output of the FI detection circuit 10 is fixed to only High or Low. Therefore, the Q outputs of the two D-FF circuits 11 and 12 are the same, and the output of the EX-NOR circuit 13 is always High. Therefore, the output of the AND circuit 15 is the output of the D-FF 14, that is, a signal that is inverted every two fields regardless of field playback or frame playback, so the control signal that controls the switch 23 is It is always Low, and is inverted at the timing of the PG pulse from input terminal 2 at other locations. Here, if the control signal is Low, it is selected by 5W19 and the f, -tuL output signal is output,
In the case of High, since a % HDL output signal is output, the discontinuity of the synchronization signal of the reproduced luminance signal input to the input terminal 1 is improved. Further, since the D-FF circuit 14 is reset when the Q output is High, there is no effect on the above-mentioned operation.

[I! ] When two tracks recorded with synchronization signals of different phases (first field and second field) are played back alternately (when frame playback is automatically set according to the played 10 signals) In this example, the first and second fields are played repeatedly for each field, so 2
The Q outputs of the two [1-FF circuits 11 and 12 have opposite polarities. Therefore, the output of the EX-NOR circuit 13 is always Low, and the AND circuits 15 and 16 of the next stage are
The output also becomes Low, and the switch 23 outputs the input luminance signal from the input terminal 1 selected by the switch 19 as the final output.

In this state, the D-FF circuit 14 is reset on a field-by-field basis, so that no disturbance of the output signal occurs even when changing from frame to field reproduction.

[III] When two tracks recorded with synchronous signals of the same phase (first field or second field) are played back alternately (when frame playback is set by the switch 59 even if the fields are different from each other) ) In this case, even if two tracks are switched for each field, only one field is reproduced, so the output of the Fl detection circuit 10 is the old GH or L
Since it is fixed at ow, two D-FF circuits 11 and 1
The Q outputs of 2 are the same, and the output of the EX-NOR circuit 13 (7) is always High, and the switch 23 is connected to the switch 19 and y2H for each field, as in the case of field reproduction.
The output from the OL 22 is alternately selected and output. Here, what is selected by the switch 19 is the luminance signal input manually to the input terminal 1, and the signal output from the y2HDL 22 is not interpolated by the adder 21 because the switch 20 is always open during frame playback, but is input to the input terminal 1. This signal is obtained by delaying the luminance signal manually inputted to terminal 1 by %H, and a reproduced signal without disturbing the synchronization signal can be obtained.

As is clear from the above, according to this embodiment, a field index detection circuit is provided to detect that the field index of the reproduced signal does not change, and in that case, compensate for the skew. The synchronized phase of the output can always be stably and correctly maintained in response to the combinations of the first field, yield, and second field of various field indexes of the field signal.

Therefore, with an extremely simple circuit configuration, an output without synchronization holes can be easily obtained.

Furthermore, although the present embodiment illustrates reproduction from a magnetic disk as an example, the present invention is not limited to this, and the present invention may be applied to an optical disk or a solid memory (semiconductor, etc.). Furthermore, it goes without saying that each storage block on the memory may or may not be fixed in advance.

[Effects of the Invention] As is clear from the above, according to the present invention, frame playback is set when the video signal is not continuously recorded in the first field and the second field in the block to be played back by the playback means. In this case, the predetermined skew compensation is automatically performed, resulting in extremely convenient use.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional example, and FIG. 3 is a circuit diagram showing another example of color difference signal extraction. 1.2.3, 4.6-... Input terminal, 5.7.8... Output terminal, lO... Field index (Fl) detection circuit,
11.12.14...D-FF circuit, 13-EX-N
OR circuit, 15.16.17...AND circuit, 18.22.25,71.73,77.79.80-.
・DL (delay line), 19.20.23...switch (
SW), 21.75...Adder, 24...NOR circuit, 30...Video floppy disk, 32...PG
Detector, 34...Motor, 358, 35B...Reproduction head, 36...Y process circuit, 37.59, 61, 62, 76^, 76B, 78A, 7
8B, 81...Switch, 38...V separation circuit, 40...DPS demodulator, 42...BPF. 44...C process circuit, 46...T flip-flop circuit, 48.50...AND gate, 51...inverter, 52...OR gate, 57...controller.

Claims (1)

[Claims] 1) A reproduction means for reproducing a designated block of video signals recorded field by field in each storage block of a recording medium, and setting either field reproduction or frame reproduction. a setting means for setting frame reproduction by the setting means, and if the first field and the second field are not recorded consecutively in the block to be reproduced by the reproduction means, a predetermined A playback device comprising means for performing skew compensation. 2) The reproducing apparatus according to claim 1, wherein the block is composed of concentric tracks formed on a disk-shaped recording medium.