JPH01133298A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To simplify a method for relieving a defective bit by composing a preliminary memory to relieve the defect of a main memory of a general semiconductor memory having a form to output plural bits. CONSTITUTION:When a word line defect detecting signal 115 is generated from the output of a word line address converting part 7, one of the preliminary memory cell out of preliminary memory 9 is responded to a preliminary word line address signal 114 and a data line address signal 110 and selected, and as the result, the defect concerned the word line of a main memory 1 is relieved by the memory 9. In the same manner, when a data line defect detecting signal is generated from the output of a data line address converting part 8, one of the preliminary memory cell out of a preliminary memory 10 is responded to a preliminary data line address signal 116 and a word line address signal 111 and selected, and as the result, the defect concerned the data line of the memory 1 is relieved by the memory 10. Thus, the preliminary memory can be composed of the general semiconductor memory having the form of plural bits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] 'The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device suitable for an extremely large capacity memory.

[Conventional technology]

First, a memory device with a conventional configuration will be described in order to explain the basic functions of the present invention. Conventionally, a defect relief method as shown in FIG. 12 has been used in semiconductor memory devices (Example 1).

An example of this is I Niss Niss See, Digest of Technical Pavers.

February 1981, pages 8o to 81 (ISSCC
DIGEST 0F TECHNICAL PAPER8゜Feburua
ry 1981. p, 8O-81). In this example, a method is used to select a spare memory by comparing an external address with a defective address written to an internal program element on-chip.

That is, a specific external address signal Xotx,.

...Decoder transistor Q0 in response to lX11
゜..., If the program element is configured so that all Qn are turned off, specific external address signals X, , X, etc.

...Node A becomes high level in response to jXn,
Spare memory is what is selected.

On the other hand, redundancy on a full wafer was implemented in memory block units. An example of this is I.E.E., Journal of Solid State Circuits, Volume 5C-15, Volume 1, No. 4db, August 1980, pp. 677-686 (I.E.E. ,
Journal of 5olid-3tate C1
rcuits Vol, S-15, No, 4Au
gust 1980. pp. 677-686) (Example 2).

This method uses an external controller to switch to a good memory block if an individual memory block is defective. In this way, external storage control for bad blocks is required.

In addition, Special Publication No. 46-25767, Special Publication No. 47-6534
As described in , the address of the defective bit is stored in the associative memory, a match is detected between the stored contents of the external address and the defective bit address, and a new address is output to the spare memory.
A redundant method for reading normal bits has been devised (Example 3)
).

[Problem to be solved by the invention]

The first problem common to the above conventional techniques is that the amount of spare memory is limited. For example, in Example 1, at most 1
Memories that can only be repaired with defects of about 0 bits and which fail to be repaired, or memories with multi-bit defects that cannot be repaired, are to be discarded. On the other hand, in order to increase the number of relief bits, the scale of the redundant circuit increases, which lowers the yield of semiconductor memory devices.

The problem with the second conventional example is that the amount of spare memory used for relief is large in memory block unit relief.
The occupancy rate of spare memory on the wafer increases. In other words, it is difficult to put it into practical use because the defect relief method and external controller are complicated, and on the other hand, if one memory block contains one defective cell, this memory block is replaced with another memory block, which reduces the amount of spare memory used. The problem is that there are too many.

The problem with the third conventional example is that an associative memory is used as the address translation device. This associative memory cell requires 8 to 10 transistors per cell, and as the logic around the memory device increases, the associative memory is expensive, making the entire system extremely expensive. Put it away. On the other hand, associative memory has a circuit configuration that stores the address of the defective bit, detects a match between the external address and the address of the defective bit, and outputs a new address from the spare memory, so it is difficult to cope with an increase in the number of defect repair bits. There is.

Therefore, a basic object of the present invention is to provide a semiconductor memory device in which the method for repairing defective bits is relatively simple and the hardware for realizing this repair is also relatively simple. It is in.

[Means to solve the problem]

According to one embodiment of the present invention, the above object is solved as follows.

That is, in order to relieve defective bits (defective memory cells) in the main memory (1), the first and second spare memories (9, 1) are
0), a word line address conversion section (7), and a data line address conversion section (8) are arranged.

As is well known, the main memory (1) has a plurality of memory cells, and one memory cell of the plurality of memory cells receives a word line address signal (111) and a data line address signal (111).
110).

A word line address signal (111) is also supplied to the input of the word line address conversion section (7), and a data line address signal (110) is also supplied to the input of the data line address conversion section (8). The word line containing a defect (defective part) on the main memory (1) is Wl (4) is the word line address signal (
111), a word line defect detection signal (115) indicating the existence of the defect related to the word line is generated from the second output of the word line address converter (7). Similarly, when the data line Di (6) containing a defect (defective part) on the main memory (1) is selected by the data line address signal (110), the second data line address converter (8) A data line defect detection signal (117) is generated from the output indicating the existence of the defect related to the data line. At the same time that the word line defect detection signal (115) is generated from the second output of the word line address converter (7), the word line defect detection signal (115) is generated from the first output of the word line address converter (7) to the first spare memory (9). ) new spare word line address signal (114) for selecting the spare word line (Wl) of
is generated. Similarly, data line address converter (8)
At the same time, the data line defect detection signal (117) is generated from the second output of the data line address converter (8), and the spare data line (dl) of the second spare memory (10) is generated from the first output of the data line address converter (8). A new spare data line address signal (116) is generated for selecting the 6 first spare memory (9).
The first input of the spare word line address signal (114
), and the second input of the first spare memory (9) is responsive to the data line address signal (110). Similarly, a second input of the second spare memory (10) is responsive to said spare data line address signal (116) and a second input of the second spare memory (9) is responsive to said word line address signal. (111) (see Figures 1 and 2).

[Effect]

The first spare memory (9) has a plurality of child memory cells. When the word line defect detection signal (115) is generated from the second output of the word line address converter (7), the first
One of the spare memory cells of the spare memory (9) of the spare memory (9) receives the spare word line address signal (114).
and a data line address signal (110), and as a result, a defect related to the word line of the main memory (1) is relieved by the first spare memory (9).

Similarly, the second spare memory (10) has a plurality of child memory cells. When the data line defect detection signal (117) is generated from the second output of the data line address conversion section (8), one of the plurality of child memory cells of the second spare memory (10) selected in response to the spare data line address signal (116) and the word line address signal (111), so that defects associated with the data lines of the main memory (1) are identified by the second spare memory (1-0). be rescued.

In response to the word line address signal (111), a spare word line address signal (114) and a word line defect detection signal (1
15) and a word line address converter (7) that generates a multi-bit output type general semiconductor memory, such as a non-volatile semiconductor memory (EPROM, EEPROM, fuse ROM, etc.) or a battery-backed semiconductor memory (battery-backed semiconductor memory). (amplified SRAM, etc.), and there is no need to use associative memory as in the past. Similarly, the data line address signal (11
The data line address conversion unit (8) which generates a spare data line address signal (116) and a data line defect detection signal (117) in response to the signal 0) is a general semiconductor memory with a multi-bit output format, such as a non-volatile memory. Semiconductor memory (EPRO)
M.

EEPROM, fuse ROM, etc.) or battery-backed semiconductor memory (battery-backed SRAM, etc.), and there is no need to use associative memory as in the past. As a result, main memory defect relief can be realized using a relatively simple method and hardware (see FIGS. 1 and 2).

Other objects and novel features of the invention will become apparent from the examples detailed below.

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram for simply showing the principle of the semiconductor memory device of the present invention. In the figure, 2o is a memory block chip that stores information, 1 is a main memory that is a collection of the block chips, 7.8 is an address translation device,
9.10 indicates a spare memory, respectively. Further, 2 is a data line address direction, 3 is a word line address direction, and 11.
12 is a spare address signal for the spare memories 9 and 1o.

Next, the operation of this block diagram will be explained. In the same figure,
The defective lines are 4 each for 13 defective bits.
, 5 in the word line direction (Wl, Wk in the figure), and 6 in the data line direction (D1 in the figure).

That is, in the block chip 20 of the main memory 1,
Since at least two memory cells 13a and 13b become defective bits in relation to the word line Wl (4), these defective bits 13a and 13b are defined as defects in the word line direction, and are located on the spare word line of the spare memory 9. word 1
It is saved by two spare memory cells related to iW1. Furthermore, since at least two memory cells 13c and 13d become defective bits in relation to the data line Di (6), these defective bits 13c and 13d are defined as defects in the data line direction, and are also considered defective bits in the spare memory 10. It is relieved by two spare memory cells related to data line d1. Further, the defective bit cell 13e is not defined as a defect in the word line direction or a defect in the data line direction, but is defined as a defect in the bit nature. However, for convenience, this defective bit cell 13e is regarded as a defect in the word line direction, and is relieved by one spare memory cell related to the spare word line Wk of the spare memory 9. still,
This defective bit cell 13e can be regarded as a defect in the data line direction and can be relieved by a spare memory cell in the spare memory 10.

Inspection of all memory cells in the block chip 20 of the main memory 1 to determine whether they are good or bad is performed by scanning in the word line direction and data line direction. This inspection and a defect relief method by writing a preliminary address signal and a defect detection signal to the address conversion devices 7 and 8 based on the inspection results will be described in detail later.

FIG. 2 is a block diagram for explaining in detail the semiconductor memory device of the present invention. In the figure, 1 is a main memory consisting of one or more memory block chips, 7 and 8 are word line and data line address converters, respectively, and 9 and 10 are
are spare memories for word line relief and data line relief, respectively; 108 is an input/output (Ilo) signal; 109 is a memory device control signal; 110 is a data line address signal (AX
), 111 represents a word line address signal (AY), and 112 represents a memory block selection signal (AZ). Also, 115
, 117 are input/output signals (Ilo
) and is a defect detection line. Further, 107 is a priority determination circuit which receives the output and determines the priority when a word line and data line address are defective at the same time, and the presence or absence of a defective address. Furthermore, 102 is an input/output switching circuit that switches between the input/output signal 119 of the main memory 1 and the input/output signal 120 of the spare memories 9 and 10;
7 selects one of the input/output signals 119 and 120.

Main memory 1, spare memory 9, 10. address conversion unit 7,
8 has already been explained in detail, so next we will refer to FIGS. 1 and 2 to check whether all the memory cells in the main memory 1 are good or bad and to check the address translation device 7 based on the results of this test. , 8 will now be described in detail.

That is, when a defect in the word line direction is detected regarding the word line Wl (4) by scanning the main memory 1 in the word line direction, the word line address signal 111 corresponding to the selection of the defective word line Wl (4) is detected. A spare word line address signal 114 (ay) for selecting a spare word line W1 of the spare memory 9 to a plurality of addresses of the word line address conversion device 7 determined by the memory block selection signal 112 (AZ) and the memory block selection signal 112 (AY). and word line defect detection signal 115 are written. Further, when a defect in the data line direction is detected regarding the data line Di (6) by scanning the main memory 1 in the data line direction, the data line address signal 110 corresponding to the selection of the defective data line Di (6) is detected. (AX) and memory block selection signal 11
A spare data line address signal 11 for selecting a spare word line d1 of the spare memory 10 at a plurality of addresses of the data line address converting device 8 determined by 2(AZ).
6(ax) and the data line defect detection signal 117 are written.

When the word line address signal 111 (AY) and memory block selection signal 112 (AZ) corresponding to the selection of the defective word line Wl (4) of the main memory 1 are supplied, the signal is determined by these signals (AY+AZ). A spare word line address signal 114 (ay) and a word line defect detection signal 115 are read out from a plurality of addresses of the word line address conversion device 7 in a multi-bit output format. Therefore, the spare word line W1 of the spare memory 9 is selected by this spare word line address signal 114 (a'y), and this spare word line W1 is selected in response to the data line address signal 110 (AX).
The spare memory cell above No. 1 is selected and defect relief is performed.

When the data line address signal 110 (AX) and memory block selection signal 112 (AZ) corresponding to the selection of the defective data line Di (6) of the main memory 1 are supplied, the signal is determined by these signals (AX+AZ). A spare data line address signal 116 and a data line defect detection signal 117 are read out from a plurality of addresses of the data line address conversion device 8 in a multi-bit output format. Therefore, by using the spare data line address signal 116 (ax), the spare memory 10
A spare data line d1 is selected, and a spare memory cell on this spare data line d is selected in response to a word line address signal 111 (AY) to perform defect relief.

Therefore, in FIG. 2, the input/output switching circuit 1
02 selects the input/output signal 119 of the main memory 1, but if a defective part of the main memory 1 is selected, the priority determination circuit 1 responds to the defect detection signals 115 and 117.
The input/output switching signal 118 is activated via the input/output signal 07 to select the input/output signal 120 of the spare memory 9-10. That is, in FIG. 2, the terminal 108 is the input/output (Ilo) terminal of the entire semiconductor memory device, and this input/output terminal 1
Writing of digital information to memory cells in the main memory 1 or the spare memories 9 and 10 is carried out via the input/output terminal 108, while the writing of digital information to memory cells in the main memory 1 or the spare memories 9 and 10 is carried out via the input/output terminal 108. Reading of digital information is executed from.

In addition, FIG. 3 shows an E P ROM in which the address converters 7 and 8 can be electrically written and erased by ultraviolet light.
(E 1 electrically program
FIG. 4 is a block diagram of an embodiment configured by an EEPROM (Electrically E-PROM) in which both writing and erasing are electrically possible for the address conversion unit 7.8.
rasable and programmable R
FIG. 5 is a block diagram of an embodiment configured by an address converter 7,
8 battery backed amplifier S RAM (S
tatic Random Access Memor
y); FIG. In particular, in FIG. 5, the switching circuit 5 supplies the battery voltage VB to the SRAM when the power supply V^ is cut off, so that S
Spare address signals 114, 116 held in RAM
Also, the disappearance of the defect detection signals 115 and 117 is avoided. Incidentally, these address conversion sections 7.8 can use nonvolatile memory such as a fuse type ROM.

FIG. 6 shows a block diagram of a semiconductor memory device according to another embodiment of the present invention, and differs from FIG. 2 only in that a latch circuit 200 is added to the data line address converter 8, and the rest is similar to the second embodiment.
It is similar to the figure. As shown in FIG. 6, the latch circuit 20
The data line address signal 110 (A
X) and a memory block selection signal 112 (AZ) are supplied, and the output line 202 of the latch circuit 200 is connected to the input/output line (Ilo) 116 to 117 of the data line address conversion unit 8. By using this latch circuit g200, it becomes easy to write the spare data line address signal 116 and the data line defect detection signal 117 to the data line address conversion section 8.

That is, based on the test results of the main memory 1, the spare data line address signal 116 and the data line defect detection signal 117 are
is latched by the latch circuit 200 via the input line 201, and then latched by the latch circuit 200 via the output line 202.
The spare data line address signal 116 and the data line defect detection signal 117 can be written to a plurality of addresses of the data line address conversion section 8 from the data line address conversion section 8 . The plurality of addresses of the data line address conversion section 8 to which this writing is performed can be determined by the data line address signal 110 (AX) and the memory block selection signal 112 (AZ). In addition, in operations other than such write operations,
The latch circuit 200 is controlled to be inactive.

Further, it goes without saying that a latch circuit similar to this latch circuit may be added to the word line data address conversion section 7 and this latch circuit may be operated in the same manner as described above.

FIG. 7 shows a block diagram of a semiconductor memory device according to another embodiment of the present invention, in which the data line defect detection signal 117 of the data line address converter 8 is in a multi-bit format, and the decoder circuit 214 is in the multi-bit format. This decoder circuit 214 is controlled by the data line defect detection signal 117.
A switch circuit 216 controlled by the decode output signal 215 of the decoder circuit 214 selects the input/output signal 213 of the spare memory 9, and a switch circuit 217 controlled by the decode output signal 215 of the decoder circuit 214 simultaneously selects the input/output signal of the main memory 1. This embodiment differs from the embodiment shown in FIG. 2 in that 119 is selected, but the rest is the same as that shown in FIG. For example, if the semiconductor memory device shown in FIG. 7 has an 8-bit input/output (Ilo) configuration, the second and third Ilo will be shared by the spare memory 10, and the first and fourth to eighth main memories 1 will share the Ilo. can be shared.

FIG. 8 shows a block diagram of a semiconductor memory device according to another embodiment of the present invention, and the second feature is that a third spare memory 11 is added for relieving memory cells with bit defects in the main memory 1. This is a difference from the embodiment shown in the figure. In the semiconductor memory device of FIG. 8, in the case of bit defect relief as shown in FIG. 9, both the word line defect detection signal 115 and the data line defect detection signal 117 are at the "1" level.
The spare memory selection signal 403 becomes P1'' level, and the third
The spare memory 11 is selected.

FIG. 10 shows a block diagram of a semiconductor memory device according to another embodiment of the present invention. The figure shows new internal addresses (114, 116), which are the outputs of the word line and data line address converters 7 and 8, and the semiconductor memory device so that word line and data line defects can be repaired using the spare memory 414.1 chip. An internal/external address switching circuit (406) that switches between applied external addresses (110, 111).

408) is added, which is the difference from the embodiment shown in FIG. In the semiconductor memory device of FIG. 10, in the case of the data line relief failure mode as shown in FIG. 11, the word line failure detection signal 115 is ◯''.

The data line defect relief signal 117 becomes the "'1" level,
The output 118 of the priority determination circuit 107 becomes the KI Olj level. As a result, internal/external address switching circuit 4
06 is connected to the external word line address AY, and its output is connected to the word line address (ay) of the spare memory 414 via the spare memory address signal line 410. Further, the internal/external address switching circuit 408 is connected to the new internal data line address ax, and its output is connected to the data line address (ax) of the spare memory 414 via the spare memory address signal line 412. Further, the spare memory 414 is in a selected state because the chip selection signal 11 becomes the II OIj level, and similarly, the input/output signal 120 of the spare memory 414 is selected by the input/output switching circuit 102. Through the above operations, defect relief is executed, and normal cells are read and written from and to the spare memory. In addition, in the case of word line relief, the word line defect detection signal 115 is
I IT level, data line defect relief signal 117 is 'O'
'' level, and the process is executed in the same way.Furthermore, in the case of a bit defect defect mode, the word line defect detection signal 115
is at “0” level, data line defect relief signal 117 is at 110
The level becomes I+, and the spare memory 414 stores a new internal data line address ax and a new internal word line address a.
y is connected and defect relief is performed.

On the other hand, when the main memory 1 is in the normal mode with good cells, the word line defect detection signal 115 and the data line defect relief signal 11
7 are both u I P level, and the output 118 of the priority determination circuit 107 is at "1" level, that is, the chip selection signal of the spare memory 414, and 11 is at the "1" level, resulting in a non-selected state. Further, in the input/output switching circuit 102, the input/output signal 119 on the main memory 1 side is selected, and normal memory cells are read and written.

In the above, 1, for example, in the spare memory 414.

Using a memory with the same configuration as main memory 1, the left side memory array of the X decoder of the same memory is allocated for data line defect relief, the right side memory array is for word line defect relief, and each data line relief line or word line relief line is One to several lines are allocated for bit defect relief. This results in a data line defect in one chip.

Three failure modes, word line defects and bit defects, can be repaired, and the efficiency of use of the spare memory used for repair can be improved. Further, in this embodiment, the additional spare memory chips can be added by first increasing the number of defect detection bits in the address conversion section, and then controlling the chip selection signal of the added spare memory based on the information of the bits.

As mentioned above, FIG. 10 has the advantage that only one chip is required for the spare memory, and when the redundant control circuit 3 is made into a chip or a module, the number of wires between the spare memory and the redundant control circuit is smaller compared to FIG. 2. have. Therefore, it is suitable for relatively small capacity semiconductor memory devices.

〔Effect of the invention〕

Spare memory 7.8゜414 for relieving defects in main memory 1
can be constructed from a general semiconductor memory with a multi-bit output format, and the method for repairing defective bits is relatively simple, and the hardware for realizing this repair is also relatively simple. equipment can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for simply showing the principle of the semiconductor memory device of the present invention, FIG. 2 is a block diagram for explaining in detail the semiconductor memory device of the embodiment of the present invention, and FIG. FIG. 2 is a block diagram of an embodiment in which the address conversion section shown in the figure is constructed from an EPROM. FIG. 4 is a block diagram of an embodiment in which the address translation section of FIG. 2 is constructed from an EEPROM. FIG. 5 is a block diagram of an embodiment in which the address converter shown in FIG. 2 is configured by an SRAM backed up by a battery. 6 to 8 are block diagrams showing semiconductor memory devices according to other embodiments of the present invention, FIG. 9 is a state diagram for explaining the operation of the embodiment of FIG. 8, and FIG. A block diagram showing a semiconductor memory device according to another embodiment of the invention; FIG. 11 is a state diagram for explaining the operation of the embodiment of FIG. 10; FIG. 12 is a block diagram illustrating a conventional semiconductor memory device. Tano Issei 2 Kunikatsu J Area y /g $ 5 times 2nd figure $ Z ko 1 times 1 Zuman // Sub 4 pieces progress soil guidance 16 Tsuta solid

Claims (1)

[Claims] 1. A semiconductor memory device that: (1) has a plurality of memory cells, and selects a predetermined memory cell from the plurality of memory cells in response to a word line address signal and a data line address signal. (2) a spare memory for relieving a defect in the main memory; and (3) a spare word line whose input is supplied with the word line address signal and is supplied to the spare memory. a word line address conversion generating an address signal on a first output thereof and a word line failure detection signal on a second output thereof indicating the presence of a defective memory cell of said main memory associated with said word line address signal; (4) having said data line address signal applied to its input and generating at its first output a spare data line address signal that is applied to said spare memory; 1. A semiconductor memory device comprising: a data line address conversion section that generates a data line defect detection signal at its second output, which indicates the presence of a defective memory cell in the memory. 2. The semiconductor memory device according to claim 1, wherein the spare memory comprises first and second spare memories, the data line address signal is supplied to the first spare memory, and the word line address signal is supplied to the first spare memory. is supplied to the second spare memory. 3. The semiconductor memory device according to claim 2, wherein the spare word line of the first spare memory is selected for a plurality of addresses of the word line address conversion section determined by the word line address signal. The spare word line address signal and the word line defect detection signal are written,
The spare data line address signal for selecting a spare data line of the second spare memory and the data line defect detection signal are set at a plurality of addresses of the data line address converter determined by the data line address signal. A semiconductor memory device characterized in that it is written. 4. The semiconductor memory device according to claim 3, wherein when the word line defect detection signal is generated from the second output of the word line address converter, a plurality of spare memories of the first spare memory At least one spare memory cell is selected from the cells in response to the spare word line address signal and the data line address signal, and as a result, a defect related to the word line of the main memory is relieved, and the data line address conversion section When the data line defect detection signal is generated from the second output, at least one spare memory cell from the plurality of spare memory cells of the second spare memory receives the spare data line address signal and the word line address signal. A semiconductor memory device characterized in that the semiconductor memory device is selected in response to a data line of the main memory, and as a result, a defect related to a data line of the main memory is repaired. 5. The semiconductor memory device according to any one of claims 1 to 4, wherein the word line address conversion section and the data line address conversion section are constituted by a multi-bit output type semiconductor memory. semiconductor memory device. 6. A defect relief method using a semiconductor memory device according to claim 2, wherein a plurality of addresses of the word line address converting unit determined by the word line address signal are connected to a spare word line of the first spare memory. The spare word line address signal and the word line defect detection signal for selecting the second spare memory are written to the plurality of addresses of the data line address converter determined by the data line address signal. a first step of writing the preliminary data line address signal for selecting a data line and the data line defect detection signal, and the word line defect detection signal is generated from the second output of the word line address conversion section; when the first spare memory is to be used, at least one spare memory cell is selected from a plurality of spare memory cells of the first spare memory in response to the spare word line address signal and the data line address signal, and as a result, the memory of the main memory is selected. When a defect related to a word line is relieved and the data line defect detection signal is generated from the second output of the data line address converter, at least one spare memory cell is selected from a plurality of spare memory cells of the second spare memory. a second step of selecting a memory cell in response to the spare data line address signal and the word line address signal, thereby relieving a defect related to the data line of the main memory. Method. 7. The defect relief method according to claim 6, wherein the word line address conversion section and the data line address conversion section are constituted by a multi-bit output type semiconductor memory. .