JPH01133162A - Cache memory control system - Google Patents

Abstract

PURPOSE:To improve the hit ratio of the whole cache memory by providing the title system with a means for executing a prescribed instruction at the time of accessing a memory from an instruction processor and setting up the means by a microinstruction. CONSTITUTION:A main memory access from the instruction processor 1 is sorted into three cases and processing to be executed at the time of generating a cache miss by said access is changed by respective sorted cases. In the case of a memory access with high locality, registering operation in the cache memory and updating operation in an LRU memory 23 are executed. In the case of a memory access with low locality, the registering operation is executed, but the updating operation is not executed. In the case of a memory access having no locality, both the registering operation and updating operation are suppressed. Any one of said operations is specified by a control bit part 11a in a specific field of the microinstruction set up in a microinstruction register 11. Consequently, the discharge of the data with high locality by the data with low locality can be reduced and the hit ratio of the whole memory 21 can be improved.

Description

[Detailed Description of the Invention] [Summary] An LRU memory update processing method that performs data registration processing in a cache memory and replacement control of the contents of the cache memory in an information processing device equipped with a cache memory and controlled by a microprogram. Regarding cache memory, processing in which the locality of the address distribution of the instructions and data executed in the information processing device on the main memory is extremely small or not present at all.

The purpose of this is to prevent the contents of the LRU memory from being updated, and to prevent the contents of the LRU memory from being updated. In an information processing device that includes a storage control device including a memory and a main memory and is controlled by a microprogram, when there is no data in the cache memory when the instruction processing device accesses the memory, the main memory An instruction to register or not register the above data in the cache memory, and if registration in the cache memory is instructed, perform or perform an operation to update the LRU memory that holds the reference history. The instruction processing device or the storage control device is provided with means for instructing whether or not the data is present, and the means is configured to be set by a microinstruction.

[Industrial Application Field] The present invention relates to a process of registering data in a cache memory in an information processing device equipped with a cache memory and controlled by a microprogram, and an update process of an LRU memory that controls replacement of the contents of the cache memory. Regarding the method.

A small-capacity but high-speed cache memory provided in an information processing device stores a copy of a portion of the data on the main memory (MS), and decodes instructions and processes data based on the decoding results. When data exists in the cache memory in response to a memory access request from an instruction processing device that performs an operation, the cache memory responds and the apparent main memory access time from the instruction processing device is reduced. This shortens the term.

In general, memory access requests generated from the instruction processing device are concentrated in a part of the memory space in the short term, and the address distribution is such that data that has been accessed once is likely to be accessed again. The cache memory utilizes this property to store a memory block (for example, 32 to 64 bytes) that includes the address requested by the instruction processing device to access the memory.
By registering the information in the cache memory, the performance of the information processing device is improved.

Furthermore, according to the locality of this address distribution, when registering one block of data on the main memory (MS) in the cache memory, if there is no "free" area on the cache memory, the most recent amount It turns out that it is effective to remove blocks that are not referenced and register them in that area.

This replacement method generally uses LRU (Least Rec
The memory that stores the reference history is called the LRU memory.

However, the locality of the address distribution of memory accesses largely depends on the functions executed on the instruction processing device.

For example, the functions performed on the instruction processing device include error handling in addition to decoding and executing machine instructions.

There are various operations such as communication processing with a service processor (SVP) and emulation processing of specific high-performance instructions.

Among these functions, in main memory accesses by functions other than decoding and executing machine instructions, the locality of the address distribution of the memory access is extremely small or completely absent, so the data related to the processing is Registering data in the cache memory is often useless, and in some cases, this registration operation may cause data that was originally highly localized to be evicted, resulting in a decrease in the cache memory hit rate. There is a problem that causes
Registration control for effective cache memory and LR
Update control for U memory is required.

In particular, with the recent spread of computer systems, the data processing by computers has diversified and the amount of processing has increased, and there is an endless demand for improvements in the processing power of these computer systems. However, there is a growing need for efficient usage methods.

[Prior art and problems to be solved by the invention] FIG. 3 is a diagram schematically showing an example of the configuration of a conventional information processing device.

First, a microinstruction is set in the microinstruction register 1 in the instruction processing device 1 shown in the figure, and the microinstruction is executed.

When a main memory fetch instruction is set in the microinstruction register 11, a microinstruction control circuit (not shown) sends the main memory fetch request to the storage control device 2, and at the same time outputs the main memory address.

Next, the TAG memory 22 is searched according to some bits of the main memory address (usually the lower pinto), and the comparison circuit (C) 22a determines whether the data block of the main memory access exists in the cache memory 21. If there is a hit, the cache memory 2 is checked.
1 is read out and sent to the instruction processing device 1 via the data line.

At the same time, the contents of the LRU memory 23 are read, the reference history information thereof is updated, and written to the L11lυ memory 23, thereby completing the operation of the main memory fetch command.

If there is a cache miss, a fetch request is output from the storage control circuit 24 of the storage control device 2 to the main storage device (MS) 3, so that the main storage 3
One block of data including the corresponding address is read out to the data line. (This operation is called move-in) At this time, among the l block data that was moved in,
The fetched address data is output to the instruction processing device 1 via the data bypass line.

In such a conventional cache memory control method, irrespective of the operation executed on the instruction processing device 1, in the case of a cache miss, registration in the cache memory 21 is performed by the cache registration instruction signal ■. As operations and update operations of the LRU memory 23 were being performed, main memory accesses with little or no locality in the address distribution (e.g., error handling, communication processing with the service process (SVP)) , emulating processing of specific machine instructions, etc.), data with high locality is removed by moving in data with low locality, lowering the hint rate of the entire cache memory and reducing the processing capacity of the information processing device. There was a problem with letting it happen.

In view of the above-mentioned conventional drawbacks, the present invention provides, in an information processing device equipped with a cache memory and controlled by a microprogram, a registration operation for the cache memory in processing with little locality of the address distribution of main memory access.
The purpose of this invention is to provide a method for efficiently accessing cache memory by suppressing update operations to LRU memory.

[Means for solving problems]

FIG. 11 is a diagram showing the principle of the cache memory control system of the present invention.

The above problem is solved by a cache memory control method configured as follows.

(both the instruction processing unit 1 and the cache memory 21)
．． and a storage control device 2 equipped with an LRU memory 23 that performs replacement control of the cache memory 21 using an LRU method and retains a reference history, and a main memory 3, and is controlled by a microprogram. When the processing device 1 accesses the memory, if there is no data in the cache memory 21, the data in the main memory 3 is registered in the cache memory 21, or
Or an instruction whether to register or not, and the cache memory 21 mentioned above.
When registration is instructed to the instruction processing device 1., the instruction processing device 1.
Alternatively, the storage control device 2 is provided, and the means 11a is configured to be set by a microinstruction.

[Effect]

That is, according to the present invention, main memory accesses from the instruction processing device are classified into the following three types, and the processing when a cache miss occurs due to the main memory access from the instruction processing device is determined according to each classification case. Try to change it.

(11 Memory access with high locality: Same as the conventional method, registration operation for cache memory and LR
Performs update operation for U memory.

(2) Memory access with low locality: A registration operation to the cache memory is performed, but an update operation to the LRIJ memory is not performed.

That is, the LRU memory indicates the block with the lowest priority, and by not updating this, the priority of the block will be lowered and the data block with high locality will be evicted at the next cache miss. deter.

(3) Memory access without locality: In this case, registration operations to the cache memory and update operations to the LRU memory are suppressed.

The above three operations can be instructed by microinstructions set in the microinstruction register in the instruction processing device, and in the microprogram for executing each case, for example, a specific microinstruction that accesses the main memory can be specified. Since the field is used to indicate one of the three cases mentioned above, it is possible to register the data in the cache memory according to the nature of the memory data (i.e. locality) when accessing the main memory. Therefore, data with high locality is less likely to be evicted by data with low locality, and the hint rate of the entire cache memory can be improved.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram showing the principle of the cache memory control system of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention, in which (a) shows an example of the configuration of a microinstruction register,
(b) is a diagram illustrating an example of an instruction for a registration operation for a cache memory and an update operation for an LRU memory by a microinstruction, and specifies the microinstruction set in the microinstruction register 11 in FIGS. 1 and 2. Means for decoding the field (control bit section) 11a and instructing the type of control for the cache memory is necessary for carrying out the present invention.

The cache memory control method of the present invention will be explained below with reference to FIGS. 1 and 2.

Even if the present invention is implemented, the registration operation for the cache memory 21, the update operation for the LRU memory 23, and the overall main memory access operation will not be particularly different from the conventional method, so they will be omitted here. A registration operation for the cache memory 21 according to the type of processing to be executed.

The method for controlling update operations for the LRU memory 23 and the LRU memory 23 will be mainly explained.

In the present invention, as shown in FIG. 2(a), the storage control device 2
A control signal (2) instructing a registration operation for the cache memory 21 and an update operation for the LRU memory 23 is sent to the storage control circuit 24, and the storage control circuit 24 stores the decoding table shown in FIG. 2(b). Accordingly, the cache registration operation and the LRU memory update operation are controlled.

For example, if the control bit part 11a of the microinstruction set in the microinstruction register 11 is 01'', as is clear from the decode table shown in FIG. 2(b),
The cache registration instruction signal (2) turns on, and the move-in data sent from the main memory (MS) 3 is written into the cache memory 21.

At this time, if there is no "empty" area in the cache memory 21, the block that has been least referenced in the past is evicted according to the reference history read from the LRU memory 23, and the main storage ( MS)
The move-in data from 3 is registered, and the read L
The contents of the reference history in the RU memory 23 are updated and written.

It goes without saying that when an eight-move index is registered in the cache memory 21, the TAG memory 22 is updated.

Next, when the control bit 11a of the microinstruction indicates 10°, the move-in data from the main memory bag W(MS) 3 is registered in the cache memory 21 in the same manner as above, but the LRU The memory 23 is controlled so that only read operations are performed and no update operations are performed. Therefore, the above registration operation will be performed in the oldest area indicated by the LRU memory 23.

Since the contents of the Bg LRU memory 23 are not updated, the area where the above registration was performed has the lowest priority.
The next time a cache miss occurs, cache memory 2
When the registration operation for 1 is performed, the data in this area is evicted, so a data block with a higher priority than this data block will not be picked out.

Next, the control focus 11a of the microinstruction is “11”.
, the data at the corresponding address of the move-in data from the main memory device (MS) 3 is only sent to the instruction processing device l via the data bypass line.
The registration operation for the cache memory 21 is also controlled so that the update operation for the LRU memory 23 is not performed, and the operation of the main memory fetch instruction is completed.

By controlling in this manner, appropriate cache memory control can be performed depending on the content of the processing executed by the instruction processing unit, that is, the locality of the address distribution.

In this embodiment, an example has been described in which the registration and updating method is instructed by the data set in the control focus unit 11a of the main memory fetch command, but in addition to this method, for example, the storage control device 2 A control flag is provided in the memory M control circuit 24, and this control flag is set in the microinstruction register 11 in the instruction processing device 1 according to the locality of the address distribution. The same effect as above can be obtained by setting a specific value to control the registration operation for the cache memory 21 and the update operation for the LRU memory 23 when the main memory fetch instruction is executed next. It goes without saying that this will happen.

As described above, the present invention is based on the fact that in an information processing device equipped with a cache memory and controlled by a microprogram, there are various aspects of the locality of the address distribution of main memory accesses depending on the type of processing executed. For example, a control focus section is provided in a specific field of a microinstruction that fetches the main memory in a microprogram corresponding to the processing mode, and based on a control signal obtained by decoding the control bit section, the cache is The feature is that the registration operation for the memory and the update operation for the LR[I memory are controlled.

〔Effect of the invention〕

As described above in detail, the cache memory control method of the present invention includes at least an instruction processing device, a cache memory, and replacement control of the cache memory.
In an information processing device that is controlled by a microprogram and that uses the J method and is comprised of a storage control device equipped with an LRtl memory that retains a reference history and a main memory, when the instruction processing device accesses the memory, the cache memory is If the data does not exist in the main memory, an instruction is given as to whether or not to register the data in the main memory to the cache memory, and if registration in the cache memory is instructed, the reference history is retained. The instruction processing device includes means for instructing whether or not to perform an update operation of the LRU memory.

Alternatively, since the above-mentioned means is set by a microinstruction in a storage control device, it is possible to register the data in the cache memory according to the nature of the memory data (i.e., locality) when accessing the main memory. Therefore, data with high locality is less likely to be evicted by data with low locality, and the hint rate of the entire cache memory can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the cache memory control method of the present invention. FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is a diagram schematically showing a configuration example of a conventional information processing device. It is. In the drawing, ■ indicates an instruction processing device. 11 is a microinstruction register. 11a is a control bit section; 2 is a storage control device; 21 is a cache memory, and 22 is a TAG memory. 22a is a comparison circuit (C). 23 is an LR [I memory; 24 is a storage control circuit; 3 is main memory. ■ is a control signal. ■ is a cache registration instruction signal. Tangled beach ■ Hari tentacle (lr)) P-5 To 11 month of the first month 1 Iri and Hootr; 4 Ha mo 2
figure

Claims (3)

[Claims] (1) A storage control device comprising at least an instruction processing device (1), a cache memory (21), and an LRU memory (23) that performs replacement control of the cache memory (21) using an LRU method and retains a reference history. A device (2);
In an information processing device that consists of a main memory (3) and is controlled by a microprogram, an instruction processing device (1)
When accessing memory from
1) If the data does not exist in the main memory (3), an instruction is given as to whether or not to register the data in the main memory (3) to the cache memory (21), and an instruction is given to register the data in the cache memory (21). In this case, the LRU memory (23) that holds the above reference history
The instruction processing device (1) or the storage control device (2) is provided with means (11a) for instructing whether or not to perform an updating operation, and the means (11a) is set by a microinstruction. A cache memory control method characterized by: (2) The cache memory control system according to claim 1, wherein the instruction means (11a) is set in a specific field of a microinstruction. (3) Instruction means (
11a) is set by executing a specific microinstruction.