JPH01132736U - - Google Patents
Info
- Publication number
- JPH01132736U JPH01132736U JP1988025813U JP2581388U JPH01132736U JP H01132736 U JPH01132736 U JP H01132736U JP 1988025813 U JP1988025813 U JP 1988025813U JP 2581388 U JP2581388 U JP 2581388U JP H01132736 U JPH01132736 U JP H01132736U
- Authority
- JP
- Japan
- Prior art keywords
- printer head
- power line
- common power
- optical printer
- light emitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003287 optical effect Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 2
- 230000002265 prevention Effects 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
- Exposure Or Original Feeding In Electrophotography (AREA)
- Dot-Matrix Printers And Others (AREA)
Description
第１図は本考案の光プリンタヘツドの要部拡大
平面図、第２図は第１図のＹ―Ｙ線断面図、第３
図は従来の光プリンタヘツドの要部拡大平面図、
第４図は第３図のＸ―Ｘ線断面図である。
１，１１……絶縁性基板、２，１２……共通電
力線、６，１４……発光ダイオード、７，１５…
…駆動用ＩＣ素子、９……電線。
Fig. 1 is an enlarged plan view of the main parts of the optical printer head of the present invention, Fig. 2 is a sectional view taken along the line Y--Y of Fig. 1, and Fig.
The figure is an enlarged plan view of the main parts of a conventional optical printer head.
FIG. 4 is a sectional view taken along the line X--X in FIG. 3. 1, 11... Insulating substrate, 2, 12... Common power line, 6, 14... Light emitting diode, 7, 15...
...Drive IC element, 9...Electric wire.
Claims (1)
の発光ダイオードを直線状に配列取着して成る光
プリンタヘツドにおいて、前記共通電力線に電圧
降下防止用の電線を並列に接続したことを特徴と
する光プリンタヘツド。 An optical printer head comprising a plurality of light emitting diodes linearly arranged and attached on a common power line deposited on an insulating substrate, characterized in that an electric wire for voltage drop prevention is connected in parallel to the common power line. Optical printer head.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988025813U JPH01132736U (en) | 1988-02-26 | 1988-02-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988025813U JPH01132736U (en) | 1988-02-26 | 1988-02-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01132736U true JPH01132736U (en) | 1989-09-08 |
Family
ID=31246877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988025813U Pending JPH01132736U (en) | 1988-02-26 | 1988-02-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01132736U (en) |
-
1988
- 1988-02-26 JP JP1988025813U patent/JPH01132736U/ja active Pending