JPH01130390A - Wiring switch circuit - Google Patents

Abstract

PURPOSE:To prevent the increase of the mounting area and the cost by providing a dynamic RAM and a PROM on the same semiconductor substrate. CONSTITUTION:A wiring connected to a first diffusion layer electrode of a MOS transistor TR, a wiring connected to a second diffusion layer electrode of the MOS TR, a means (dynamic RAM) which is connected to the gate electrode of the MOS TR and stores wiring information, a means (PROM 44) which is connected to this wiring information storage means and stores information supplied to the dynamic RAM, and a means (refresh control circuit 43) which selects the dynamic RAM are provided on the same semiconductor substrate. It is necessary to periodically refresh the dynamic RAM, and it is periodically refreshed based on PROM data provided on the same integrated circuit. Thus, memory parts where cutoff and connection structures of wirings are realized in a small area, and the area and the cost of mounting for system constitution are reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a wiring switch circuit that makes wiring within a semiconductor integrated circuit variable, and in particular to a wiring switch that can reduce the mounting area and packaging cost. Regarding circuits.

[Prior art]

In conventional wiring switch circuits, for example, "Nikkei Electronics, September 8, 1986 issue, pp. 245-265
As described in page 1, information is retained by storing wiring switch information in a static RAM placed near the wiring.In addition, the information source includes a memory provided outside the semiconductor integrated circuit. A memory element such as a FROM is used, and wiring data is loaded from the FROM or the like to the RAM inside the circuit each time the power is turned on.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, since a static type RAM is used, a circuit composed of five transistors is required to store the configuration of 1 bit, and there is a problem that the area of the wiring information storage section becomes large. .

Furthermore, since a nonvolatile memory element such as FROM is required as an information source outside the circuit, there is a problem in that the mounting area and cost increase.

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide a wiring switch circuit that has a small area and does not require an external storage element even when a large amount of wiring information is required.

[Means to solve the problem]

In order to achieve the above object, the wiring switch circuit of the present invention includes a wiring connected to a first diffusion layer electrode of a MOS transistor and a wiring connected to a second diffusion layer electrode of the MOS transistor on the same semiconductor substrate. Wiring and its Mo8)-
A means (dynamic RAM) connected to the gate electrode of the transistor to store wiring information; a means (FROM) connected to the wiring information storage means to store information supplied to the dynamic RAM;
A feature of the present invention is that it includes a means (refresh control circuit) for selecting M.

Further, the dynamic RAM is composed of a MOS transistor, one diffusion layer electrode of the MOS transistor is connected to the gate electrode of the MOS transistor, the other diffusion layer electrode is connected to the readout circuit of the PROM, and the gate The electrode is characterized in that it is connected to the refresh control circuit.

[Effect]

In the present invention, dynamic R
By providing AM and FROM, the same effect as directly driving a wiring switch transistor with FROM can be obtained.

In other words, the dynamic RAM needs to be refreshed periodically, and the periodic refresh is performed based on FROM data provided in the same integrated circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a configuration diagram of a semiconductor integrated circuit in one embodiment of the present invention.

The semiconductor integrated circuit of this embodiment includes circuit modules 2 to 5,
and a wiring switch circuit 6 are provided on the semiconductor substrate 1, and each circuit module 2-5 is coupled to the wiring switch circuit 6 by wirings 7-10.

Further, the circuit modules 2 to 5 are connected to input/output lines 11 to 14 for communication with the outside of the semiconductor integrated substrate 1.

Note that the circuit modules 2 to 5 are a CPU, memory, programmable logic array (PLA), programmable logic device (PLD), etc.
The functions of each module are not particularly limited.

FIG. 2 is a configuration diagram of a transistor switch matrix in a wiring switch circuit according to an embodiment of the present invention.

The wiring switch circuit 6 in this embodiment is composed of a transistor switch matrix 20, and has three wirings 71-73. for each circuit module 2-5.
81-83, 91-93, 101-103 are connected.

Further, the transistor switch matrix 20 includes wiring cutoff transistors T, ~T,,T,. ~T23°T,.

~T4m, T,. ~Ts3. T7. ~T,,,T,. ~
T...

T. ~To, wiring connection transistor T,. ~T1.
.

T,,~T@2. and a memory circuit R for providing information to the gate electrode of each switching transistor.
R mouth, R2゜~R,3, R3゜~R3□, R4,~R4
2゜Rs, #R,,,R,,~R,,,R,,~R,,
,R,,~R1,.

It has R9° to Ro.

This wiring cutoff transistor allows Ov to be applied to the gate electrode.
When is applied, the wiring is cut off. Also, when 5V is applied to the gate electrode, the wiring connection transistor causes
Intersecting wires are connected.

FIG. 3 is a configuration diagram of a memory circuit in a wiring switch circuit according to an embodiment of the present invention.

The memory circuit in this embodiment is a known dynamic RA
M, and stores wiring information given to wiring connection transistors and wiring disconnection transistors.

That is, information is stored by storing charge in a capacitor C formed on one diffusion layer electrode of the transistor 30 or parasitically formed.

Also, the terminal 3 to which the capacitor C of the memory circuit is coupled
1 is connected to the gate electrode of each switch transistor (wire cutoff transistor, wire connection transistor).

When storing information in this storage circuit, the transistor 30
If 5V is applied to the gate electrode S of the terminal, and data is applied to the - side electrode, and the gate electrode S is set to Ov while the data is being applied, the transistor 30 is cut off and the information is transferred to the capacitor C. is memorized.

In this case, since the electrode of the transistor 30 is used under the condition that a reverse voltage is applied to the pn junction, a pn leak current flows, and the charge stored in the capacitor C is gradually discharged and information disappears.

The time it takes for this information to disappear is generally about 10 msec.

Therefore, by writing the same data again (refreshing) in a fraction of that time (approximately 2 ms), the voltage of the gate electrode of the wiring cutoff transistor or connection transistor is maintained within a constant voltage range. .

FIG. 1 is a configuration diagram of a memory circuit matrix and a circuit for refreshing the memory circuit in a wiring switch circuit according to an embodiment of the present invention.

Memory circuits R1° to Ra, R2° to R in this embodiment
33tR30~R,,,R4゜~R,,,Rs,-'R
s3. R,, ~R,,,R,, ~R,,,R,. ~R,
2, Rg. ~R,, the selection line 80~ is connected to the gate electrode S.
Data lines ~D are connected to one of the electrodes and arranged in an array.

In addition, the selection information of the storage circuit is stored in the refresh control circuit 4.
1 selection sS, ~S obtained by decoding the signal 41 from 3 with the decoder circuit 40.

1 selected zero out of 1 becomes 5v.

Also, regarding the data supplied to the memory circuit, FROM
Data from FROM 4.4 is read by read signal 42, and information is provided to data lines D0 to D3.

By periodically repeating this operation for each selection line, the information in the memory circuit is always retained.

Furthermore, data is written to the FROM 44 by applying write data, write signals, etc. via a write line 45 from outside the semiconductor integrated circuit 1.

In this way, when power is applied to the semiconductor integrated circuit 1, a refresh operation is automatically started, and the state of the wiring is determined when the refresh operation completes one cycle.

In this embodiment, one circuit module can be freely connected by writing wiring information in the FROM corresponding to the memory circuit that controls the switch transistor.

Further, by providing the FROM on the same semiconductor substrate, the number of external parts can be reduced, and the cost and mounting area can be reduced.

〔Effect of the invention〕

According to the present invention, a memory section that stores wiring cutoff and connection structure can be realized in a small area.

In addition, FR with a regular structure is used as a backup memory.
By providing the OM on the same substrate, the number of terminals of the integrated circuit can be reduced, and furthermore, an external FROM is not required.

Therefore, it is possible to reduce the mounting area and the mounting cost when configuring the system.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a memory circuit matrix in a wired switch circuit according to an embodiment of the present invention and a circuit for refreshing the memory circuit, and FIG. 2 is a diagram of a transistor switch matrix in a wired switch circuit according to an embodiment of the present invention. FIG. 3 is a block diagram of a memory circuit in a wiring switch circuit according to an embodiment of the present invention, and FIG. 4 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention. 1: Semiconductor substrate, 2-5: Circuit module, 6: Wiring switch circuit, 7-10.71-73.81-83.91
~93, 101-103: Wiring, 11-14: Input/output line, 20: Transistor switch matrix, 30: Transistor, 31: Terminal. 40: Decoder circuit, 41: Signal from refresh control circuit, 42: PROMIJ-de signal, 43: Refresh control circuit, 44: FROM, 45: Write line, D: Electrode, D0~D,: Data line, R1~ R,t,
R. ~R,,,R,. ~R32,R4゜~R,,,
R. ~R,3,R,. 〜R,,,R,,〜R,,,R,. ~
R,,,R,. ~R92: Memory circuit, S: Gate electrode, 80~S,: Selection line, T trout ~ T mouth, T2°~T23. T. ~T, 2.
T. ~Ts3. T. ~T,,,T,,~T,,,Ts,~
T, , : Wiring cutoff transistor, T3. ”'T3z
,T. ~TGz: Transistor for wiring connection. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. In a wiring switch circuit that connects and disconnects wirings of a semiconductor integrated circuit, wirings connected to the first diffusion layer electrode of a MOS transistor and the M
A wiring connected to the second diffusion layer electrode of the OS transistor, a means connected to the gate electrode of the MOS transistor for storing wiring information, and a means connected to the wiring information storage means to supply the wiring information to the wiring information storage means. A wiring switch circuit comprising means for storing information and means for selecting the wiring information storage means. 2. The wiring information storage means is composed of a MOS transistor, one diffusion layer electrode of the MOS transistor is connected to the gate electrode of the MOS transistor, and the other diffusion layer electrode is connected to the readout circuit of the supply information storage means. 2. The wiring switch circuit according to claim 1, wherein the gate electrode is connected to the selection means.