JPH01126631A - Optical pll circuit - Google Patents

Abstract

PURPOSE:To obtain an optical PLL circuit of an extra-high speed which is not subjected to the speed limitation of an electrical circuit by inputting received signal light pulses and a part of outputted clock light pulses to said circuit and outputting the intensity correlation signal of the signal light pulses and the clock light pulse train. CONSTITUTION:A correlation signal generating part 103 is inputted with 2 systems of the light pulses; the signal light pulses of the pulses to be synchronized inputted from the outside and a part of the clock light pulses outputted from a clock light pulse generating part 105 and outputs the electric signal of the sufficiently low speed corresponding to the correlation signal of the light intensities of these two systems. A control circuit 104 calculates the repeating frequency difference of the signal light and the clock light from the output waveforms of a correlation signal generating part 103 and outputs the control signal corresponding to the frequency difference. The clock light pulse generating part 105 controls the repeating frequency of the clock light pulses by the control signal outputted from the control circuit 104 in such a manner as to have the repeating frequency equal to the clock frequency of the signal light pulses. The high-speed optical PLL circuit which is not subjected to the limitation of the operating speed of the electric circuit, etc., is thereby obtd.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention extracts and generates optical clock pulses for synchronization required in ultra-high-speed optical repeaters, optical terminal equipment, or other optical signal processing circuits. This invention relates to an optical PLL circuit.

[Conventional technology]

The basic configuration of a PLL circuit conventionally used in digital optical fiber transmission is shown in Fig. 2111. In Fig. 2, 201 is a signal light input section, 202 is a light receiving element,
203 is a narrow band filter, 204 is a phase comparator, 205
is a reduction filter, 206 is a voltage controlled oscillator (VCO)
, 207 are output terminals. That is, this PLL circuit is entirely composed of electric circuits, and when obtaining a clock with a repetition frequency equal to the clock frequency of the signal light pulse train, the signal light pulse received from the signal light input section 201 is converted into an electric signal by the light receiving element 202. , narrowband filter 203
, a phase comparator circuit 204, a reduction filter 205, and a voltage controlled oscillator 206, an electrical signal clock is obtained at an output terminal 207. Therefore.

If an optical clock is required, a light emitting element is connected to the output terminal 207 to convert the electrical clock into an optical clock. Alternatively, if it is necessary to electrically process the signal using the electric clock output from the output terminal 207 and convert it into an optical signal,
Similarly, the light emitting element converts an electrical signal into an optical signal.

[Problem that the invention seeks to solve]

Since all conventional PLL circuits are composed of electrical circuits, the operating speed of optical repeaters, optical signal processing circuits, etc. is limited by the operating speed of each light emitting element, light receiving element, and electrical circuit in the PLL circuit. Currently, at most 10
The upper limit is about Gb/s. Therefore, there has been a need for an ultra-high-speed optical PLL circuit that is not subject to speed limitations of the light-emitting light-receiving element that converts into electrical/optical signals and the electric circuit in the PLL circuit.

The present invention has been made in view of the above.

It has a simple configuration and operates at high speeds of several tens of Gb/s or more.

An object of the present invention is to provide an optical PLL circuit that can directly generate an optical clock.

[Means for solving problems]

The basic configuration of the optical PLL circuit of the present invention is as shown in FIG. a correlation signal generation section 103 that receives two series of optical pulses, including the clock light pulse train of the clock light pulse train of the section 102, and outputs a low-speed electrical signal corresponding to an intensity correlation signal of the signal light pulse train and the clock light pulse train; A control circuit 104 receives the intensity correlation signal outputted from the unit 103 and outputs a control signal, and generates and outputs a clock light pulse train whose repetition frequency changes so that the intensity correlation signal is maximized according to the control signal. terminal 10
It is characterized by comprising a clock light pulse generating section 105 outputting to the clock pulse generator 6.

[For production]

The correlation signal generation section 103 generates a signal light pulse of a synchronized pulse inputted from the outside and a clock light pulse generation section 10.
Two series of optical pulses of a part of the clock light pulses outputted from 5 are input, and a sufficiently low-speed electrical signal corresponding to a correlation signal of the light intensity of these two series is output. Items used to output the correlation signal in the correlation signal generation section 103 include two light receiving elements connected in series, an SHG crystal that generates second harmonic (SHG) light, or an optical card. (Karr) There is a medium. The control circuit 104 calculates the repetition frequency difference between the signal light and the clock light from the output waveform of the correlation signal generation section 103, and outputs a control signal corresponding to the frequency difference. The clock light pulse generator 105 adjusts the repetition frequency of the clock light pulse so that it has a repetition frequency equal to the clock frequency of the signal light pulse using the control signal output from the control circuit 104. The clock light pulse generator 105 includes a voltage controlled oscillator (V
It is possible to use a semiconductor laser driven by CO (CO) that generates optical pulses by gain switching, or a passive mode-locked semiconductor laser including a saturable optical absorber whose external cavity length can be changed by a precision motor.

A conventional PLL circuit does not use a light receiving element to convert a high-speed optical signal into a 5-carrier electrical signal.

The difference is that the structure does not require high-speed electrical circuits,
Therefore, an extremely high-speed optical PLL operation of 10 Gb/s or more is possible with a simple configuration, without being limited by the operating speed of light-receiving/emitting elements, electric circuits, etc.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a diagram showing the first embodiment of the present invention, 301
is a signal light input section, 302 is a clock light input section, 303 is a correlation signal generation section, 304 is a power supply terminal, 305 is a load resistor, 306 and 307 are photodiodes, 308 is a control circuit, 309 is a clock light pulse generation section, 310 is VCO
1311 is an amplifier, 312 is a capacitor, 313 is a DC bias current source, 314 is a semiconductor laser, 315 is a delay circuit control motor, 316 is a variable optical delay circuit, and 317 is an output optical terminal.

The operation of this circuit will be explained with reference to the time chart shown in FIG. FIG. 4A is a time chart of clock light pulses input from the clock light input section 302 to the correlation signal generation section 3.3, a variable delay, that is, a variable phase difference is given by the variable optical delay circuit 316, and the amount of delay is increases from the left end to the right end of the time chart, resulting in a phase change of about -1 time slot. B, D
.

F is a time chart of signal light pulses input to the signal light input section 301, where the repetition frequency is equal to the clock light pulse frequency, D is greater than the clock light pulse frequency, and F is greater than the clock light pulse frequency. C2F and G represent the correlation outputs of A and B, and A and F, respectively.

Optical pulse of clock optical input section 302 and signal optical input section 30
By inputting one signal light pulse to the correlation signal generating section 303, a correlation output signal proportional to the temporal overlap of the two input pulses can be obtained. That is, the correlation output waveform when both clock frequencies are equal has the maximum output when there is no phase difference between the two optical pulses as shown in C. When the frequency of the signal light pulse is higher than the clock light pulse frequency, the range of the phase difference that produces the correlation output narrows as shown in E, and at the same time the pulse interval narrows, so that the peak of the correlation output has a small phase difference. On the other hand, when the frequency of the signal light pulse is smaller, the range of the phase difference that generates the correlation output becomes wider, and at the same time the pulse interval widens.
The peak moves to the right side of the time chart. The 51st fi shows this situation. 501 shows a time waveform of the delay amount (phase difference) provided by the variable optical delay circuit 316, and 502 is a graph in which the horizontal axis represents the delay amount and the vertical axis represents the correlation output.

In the graph, C, G, and E respectively correspond to the waveforms shown in 4!14.0 If the delay amount at which the correlation signal takes the maximum value when there is no phase shift is τ1, then the frequency of the signal light pulse is When the frequency is lower than the clock frequency, the delay amount at which the correlation signal takes a maximum value moves to τ, which is larger than τ2, and on the other hand, when the frequency of the signal light pulse is higher, it moves to τ, which is smaller than τ3.

The control circuit 308 detects the delay amount t that always takes the maximum value,
Input the time change Δt.

Output v=g·Δt as a control signal. However, 1g is the control circuit 308
is the gain.

The control signal V output from the control circuit 308 is input to the VCO 310 of the clock light pulse generator 309 . V
In the CO 310, the oscillation frequency f changes according to the control signal V as follows.

f=f, +V@f□ However, f8 is a frequency that changes depending on the unit control voltage. The output of the VCO 310 is amplified by an amplifier 311 as necessary, superimposed on a DC current by a DC bias current source 313, and applied to a semiconductor laser 314. The semiconductor laser 314 generates an optical pulse train with a repetition frequency f and a width of several tens of ps using a gain switch, and outputs a clock optical pulse.

In the configuration shown in FIG. 3, a high-speed optical signal is directly converted into a correlation signal with optical pulses, so a wide-band electric circuit is not required, and optical PLL operation can be expected at speeds of several tens of GHz or more.

FIG. 6 is a diagram showing a second embodiment of the present invention.

601 is a signal light input section, 602 is a clock light input section, 6
03 is a correlation signal generator, 604 is a lens, and 605 is a SH
G crystal, 606 is a light receiving element, 607 is a control circuit, 608
609 is a clock light pulse generator, and 609 is a voltage controlled oscillation m.
(VC:O), 610 is an amplifier, 611 is a capacitor, 612 is a DC bias current source, 613 is a semiconductor laser, 614 is a delay circuit control motor, 615 is an optical delay circuit, and 616 is an output optical terminal.

The difference between this embodiment and the embodiment shown in FIG. 3 (Embodiment 1) is that in FIG.
The other circuits are the same in that they are composed of a generating optical crystal 605. In the SHG connection, in the correlation signal generation unit 603 using the vI 605, the signal light pulse and the clock light pulse are made to enter the SHG crystal 605 so that their optical paths overlap.

Sum frequency light having an optical frequency that is the sum of the optical frequency of signal light and the optical frequency of clock light is effectively generated.

At this time, the intensity of the sum frequency light is proportional to the correlation of the intensity of the signal light pulse. By converting this sum frequency light into an electrical signal using the light receiving element 606, a PLL circuit similar to that of the first embodiment can be constructed.

FIG. 7 is an example showing a third embodiment of the present invention.

701 is a signal light input section, 702 is a clock light input section, 7
03 is a correlation signal generator, 704 is an optical car shutter, 70
5 is a polarization beam splitter or analyzer, 706 is a light receiving element, 707 is a control circuit, 708 is a clock light pulse generator, 709 is a voltage controlled oscillation 11, 710 is an amplifier, 7
11 is a capacitor.

715 is an optical delay circuit, and 716 is an output optical terminal.

In this embodiment, an optical shutter including an optical Kerr medium is used in the correlation signal generating section 703.

An optical Kerr medium is a substance that changes the refractive index of the medium in proportion to the intensity of the medium, and the polarization dependence of the refractive index change (
Birefringence) changes the polarization state of input light. Therefore, by arranging the polarization beam splitter or analyzer 705 after the Kerr medium, the output light intensity can be changed in accordance with the change in the input light intensity. When the intensity of the clock light pulse is sufficiently large compared to the signal light pulse, the refractive index change of the Kerr medium is mainly induced by the clock light pulse, so the transmitted light intensity of the signal light pulse is equal to the signal light pulse intensity and the clock light pulse. It corresponds to a correlation signal of optical pulse intensity. This transmitted light intensity may be converted into an electrical signal by the light receiving element 706 and input to the control circuit 707.
The other configurations are the same as in the first embodiment.

FIG. 8 shows a fourth embodiment of the present invention, in which 801
802 is a signal light input section, 802 is a clock light input section, 803 is a correlation signal generation section, 804 is a control circuit, 805 is a clock light pulse generation section, 806 is a motor, 807 is an external mirror, 808 is a saturable absorber, 809 is a semiconductor laser (LD
), 810 is a delay circuit control motor, 811 is an optical delay circuit, and 812 is an output optical terminal.

In this embodiment, the clock light pulse generator 805 includes a voltage controlled oscillator (VCO) and a semiconductor laser (LD
), instead, a passive mode-locking method of an external resonator-added LD is used. In the passive mode-locking method, an external resonator is configured by an external mirror 807 and an LD 809 whose end face facing the main mirror is coated with anti-reflection coating, and when the intensity of incident light between the resonators increases, the absorption coefficient decreases. A saturable absorber 808, which is an absorber, is inserted. At this time, a DC bias current is applied to the LD 809, and it acts as an optical amplification medium.

Due to the action of the saturable absorber 808, strong light among the light passing through the resonator is amplified with little absorption, and weak light is amplified with high absorption, so the output light becomes pulsed, and the pulse interval is equal to the end face of the LD 809. It is equal to the time it takes to go back and forth to the external mirror. Therefore, the 6 repetition frequency of the clock light pulse is determined only by the resonator length LO of the external resonator as follows.

f = c / 2 Lo (c is a constant) Therefore, by installing a precision movable motor 706 behind the external mirror and controlling Lo, the clock light frequency can be controlled. In this case, unlike the embodiment shown above, CO is not required.

It is possible to generate faster optical pulses with a simpler configuration. For example, if L = 5 mm.

The repetition frequency is 30 GHz.

FIG. 9 shows a fifth embodiment of the present invention.

901 and 903 are signal light input sections, 902 and 904 are clock light input sections, and 905 and 906 are half mirrors 1907
, 908 is a correlation signal generation section, 9o9.910 is a low-pass filter, 911 is a differential amplifier, 912 is a clock light pulse generation section, and 913 is an output optical terminal.

For the correlation signal generating sections 907 and 908 and the clock light generating section 912 in this embodiment, any of the configurations shown in the first to fourth embodiments may be selected.

A time chart showing the operation of FIG. 9 is shown in FIG. 10.
In the figure, H is a black, ivy light pulse waveform, J is a signal light pulse waveform input to the signal light input section 903, K is an output waveform of the correlation signal generation section 907, L is an output waveform of the low-pass filter 909, and M is an output waveform of the low-pass filter 909. N is the output waveform of the correlation signal generator 908, P is the output waveform of the reduction filter 910, and Q is the output waveform of the differential amplifier 911. In addition, the area marked ■ indicates a case where there is no phase change between the clock and the signal, the area marked ■ indicates a case where the phase of the signal pulse begins to lag, and the area marked ■ indicates the case where the phase of the signal pulse begins to advance.

In the embodiment shown in FIG. 9, the signal light pulse and the clock light pulse are each sent to a half mirror 9 instead of the optical delay circuit.
It is configured to branch into two streams at 05 and 906, and determine the advance and lag of the phase shift of the signal light pulse by taking the respective correlation signals. That is, in the correlation signal generating section 907, the clock light pulse is input later than the signal light pulse as shown in FIG. is advanced and made incident.

Therefore, if a phase lead occurs in the signal light pulse,
As shown in the area (■) in FIG. 10, the other correlation signal generator 9
On the contrary, when a phase delay occurs in the signal light pulse, the output of 08 increases and the output of the negative correlation signal generating section 907 decreases.

As shown in the area (■) in FIG. 10, the other correlation signal generator 9
08 decreases, and the output of one correlation signal generator 907 increases. Average S2 of the output of one correlation signal generation section 907 and average S2 of the output of the other correlation signal generation section 908
By inputting the difference v=g·(S, -5Z) as a control signal to the clock light generation section 912, it is possible to generate a clock light pulse train that follows the change in the repetition frequency of the signal light pulse. The subsequent operations may be performed in the same manner as in the previous embodiment.

〔Effect of the invention〕

As explained above, according to the present invention, there is no need to convert a high-speed optical signal into an electrical signal using a light-receiving element. PLL operation of signals becomes possible with a simpler configuration. This optical PLL circuit can be applied to optical signal processing, typified by high-speed optical sampling, high-speed optical gates, high-speed optical clock generation, etc., high-speed optical transmission, etc., such as gold-optical repeaters, and the like.

[Brief explanation of the drawing]

Fig. 1 shows the basic configuration of the present invention, and Fig. 2 shows the conventional P
3 is a block diagram showing the first embodiment of the present invention, FIGS. 4 and 5 are time charts for explaining the operation of the embodiment of FIG. 3, and 6114 is a diagram showing the LL circuit. FIG. 7 is a block diagram showing a second embodiment of the invention, FIG. 7 is a block diagram showing a third embodiment of the invention, and FIG. 8 is a block diagram showing a fourth embodiment of the invention.
FIG. 9 is a block diagram showing a fifth embodiment of the present invention, and FIG. 9 is a block diagram showing a fifth embodiment of the invention. i is a time chart for explaining the operation of the embodiment shown in FIG. 101... Signal light input section, 102... Clock light input section, 103... Correlation signal generation section, 104... Control circuit, 105... Clock light pulse generation section, 106...
Output optical terminal.

Claims (6)

[Claims] (1) An optical PLL circuit that receives a signal light pulse and generates a clock light pulse having a repetition frequency equal to the clock frequency of the signal light pulse, wherein the received signal light pulse and the output clock light pulse are synchronized. a correlation signal generation section which receives the signal light pulse and the clock light pulse train as input and outputs an intensity correlation signal of the signal light pulse and the clock light pulse train; It is characterized by comprising a control section that sends out a control signal, and a clock light pulse generation section that makes the repetition frequency variable based on the control signal and generates a clock light pulse having a phase that matches the phase of the signal light pulse. Optical PLL circuit. (2) The correlation signal generating section receives two series of light pulses, a signal light pulse and a clock light pulse, and is connected in series so that the output electric signal becomes an intensity correlation signal of the two series of light pulses. 2. The optical PLL circuit according to claim 1, wherein the optical PLL circuit includes two light receiving elements. (3) The correlation signal generating section includes an SHG crystal that generates light having a sum frequency of an optical frequency of a signal optical pulse and an optical frequency of a clock optical pulse.
Optical PLL circuit described in section. (4) The correlation signal generating section has a refractive index that changes depending on the intensity of the clock light pulse, the intensity of the signal light pulse, or the intensity of the sum of two series of light pulses, the signal light pulse and the clock light pulse. 2. The optical PLL circuit according to claim 1, wherein the optical PLL circuit includes an optical Kerr medium that outputs a signal corresponding to a correlation signal of the two series of optical pulse intensities. (5) The clock light pulse generator is driven by a gain switch method and includes a semiconductor laser that generates short optical pulses and a drive signal source for the semiconductor laser, and receives the correlation signal output from the correlation signal generator as input. , and a voltage controlled oscillator whose oscillation frequency changes according to the correlation signal. (6) The clock light pulse generation section includes an optical resonator that includes a semiconductor laser light amplification medium and a saturable light absorption medium, and according to the correlation signal output from the correlation signal generation section,
2. The optical PLL circuit according to claim 1, further comprising a mechanism that can vary the clock frequency by controlling the resonator length of the optical resonator.