JPH01126191A - Brushless dc motor - Google Patents

Abstract

PURPOSE:To simplify the composition of a device economically, by reading out a driving waveform stored in a memory, with the detected output of a driving main magnetic field, and address signal formed based on the pulse of a frequency higher than that of the detected output, to drive a motor. CONSTITUTION:A brushless DC motor is provided with a rotor 1 and a stator 2, and a magnet consisting of a plurality of magnetized permanent magnet poles is set. To the rotor side of the stator 2, winding blocks C1, C2 are series- connected, and are formed to be a first stator coil 3, and are composed in the same manner and are formed to be a second-a third stator coils 4-5. The first-the third stator coils 3-5 are confronted with the magnet of the rotor 1, and are arranged at positions different from each other by 120 deg. multiplied by an odd number at an electrical angle. Besides, as the detecting elements of the rotor 1, three Hall elements 6-8 are arranged. Also, means 21-23 for generating the pulse of high frequency with the output of the elements 6-8, and memory 24 are arranged, and the motor is driven.

Description

[Detailed description of the invention] The invention will be explained in the following order.

A. Field of industrial application B. Overview of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) Figure 1) Circuit configuration and operation of G2 (Figure 2) Overall circuit operation of G3 (Figures 3 and 4) Effects of the invention A Industrial application field This invention is applicable to record players, etc., for example. The present invention relates to a brushless DC motor that is suitable for use.

B. Summary of the Invention This invention provides a method for generating a predetermined driving waveform stored in a memory in advance using a detection output of a detection element that detects the main magnetic field for driving and an address signal formed by a pulse generator with a higher frequency than this detection output. By reading out and driving the motor, a frequency generator (FG) or a pulse generator (PG) can be activated.
) to simplify the circuit configuration and reduce costs.

C. Conventional technology Conventionally, a rotor magnet magnetized so that the magnetic field is sinusoidal, two-phase stator coils arranged at positions that differ from each other by an odd multiple of 90 degrees in electrical angle, and one phase of the rotor.
It has a signal generator that obtains a signal with a constant number of repetitions per rotation and whose frequency changes depending on the rotational speed of the rotor, and a memory circuit in which sine waveform information is stored. The sine waveform information is read in synchronization with the magnetic field applied to the stator coil from the rotor magnet, and a drive current based on the read sine waveform information is supplied to the stator coil. The sum information of accurate sine waveform information and correction waveform information according to the difference between this accurate sine waveform information and the magnetizing magnetic field of the rotor magnet is formed as waveform information, and the drive current is determined based on this sum information. A brushless DC motor has been proposed (Japanese Unexamined Patent Publication No. 117485/1985) in which a brushless DC motor is supplied to a stator coil. Problems to be Solved by the Invention However, in the case of the conventional brushless DC motor described above, A signal generator that generates a signal that has a constant number of repetitions per rotation of the rotor and whose frequency changes depending on the rotational speed of the rotor, that is, a signal generator that generates a signal that reads out sine wave information stored in memory.The rotor shaft A PC is used as a detection element to detect the position of a permanent magnet by emitting magnetic flux from a permanent magnet attached to a specific position on the outer peripheral surface of the rotor. This has disadvantages such as a complicated configuration and high cost.

This invention was made in view of these points, and FG and P
To provide a brushless direct current motor that is simple in configuration and inexpensive and can drive a motor by reading a driving waveform from a memory without using C.

E. Means for Solving the Problems The brushless DC motor according to the present invention includes a detection element (6 to 8) that detects the main magnetic field for driving, and a pulse generator that generates a pulse with a higher frequency than the detection output of this detection element. Means (2
1 to 23) and a memory in which predetermined driving waveforms are stored.
(24), and is configured to read out the drive waveform of the memory using an address signal formed based on the detection output and the pulse, and drive the motor.

G' The main magnetic field for driving is detected by the action detection elements (6 to 8). Further, the pulse generating means (21 to 23) generates a pulse having a higher frequency in response to the detection output of the detection element. That is, a plurality of pulses are substantially interpolated at intervals between zero crossing points of the outputs of a plurality of detection elements. and,
An address signal is formed based on this pulse and the detection output, and a predetermined drive waveform stored in the memory (24) is read out using this address signal to drive the motor. This eliminates the need for FC and PC, and the configuration is simple.
Becomes inexpensive.

G. Example Hereinafter, an example of the present invention will be described in detail based on FIGS. 1 to 4.

Circuit configuration of the entire G1 FIG. 1 shows the circuit configuration of this embodiment. (1) and (2) are the rotor and stator that constitute the brushless DC motor, and the stator (2) of the rotor (1) ) is provided with a magnet (not shown) consisting of a permanent magnet magnetized with multiple poles. On the side of the stator (2) facing the rotor (1), winding blocks C1 and C2 are connected in series, and are arranged at positions that are in phase with each other with respect to the magnetic field from the magnet of the rotor (1). 1 stator coil (3) is formed, and similarly the rotor (1
) winding blocks C3 and 04, which are arranged at positions that are in phase with each other with respect to the magnetic field from the magnets, are connected in series to form a second stator coil (4), and similarly to the rotor (1). The winding blocks C5 are arranged in positions that are in phase with each other with respect to the magnetic field from the magnets.
and C6 are connected in series to form the third stator coil (5).
is formed. And these, number 1. The second and third stator coils (31, +41 and (5) are connected to the rotor (1
) are arranged to face the magnets, and are arranged at positions that differ from each other by an odd multiple of 120 degrees in electrical angle.

In addition, three stator coils (31, (41 and (5)
Three Hall elements (61, (71 and ()) are used as detection elements to detect the magnetic field of the magnet of the rotor (1) corresponding to
8) is provided. That is, the Hall element (6) is located at a position where it is in phase with the stator coil (3) in electrical angle, the Hall element (7) is located at a position where it is in phase with the stator coil (4) in electrical angle, and the Hall element (8) is located at a position where it is in phase with the stator coil (4) in terms of electrical angle. The three Hall elements (61, (71 and (8) are located in the rotor (1)
The magnetic flux from the magnet is detected at the position where the magnetic flux from the magnet is detected, and at positions that differ from each other by 120 degrees in electrical angle.

(9) is an output terminal to which the stator coils (31, (41 and (5)) are connected, and one end of the starter coils f31, (4) and (5) are outputted through this output terminal (9), respectively. Amplifiers (18), (19) and (20
) is connected to each output terminal W, U, and V of the terminal. Hall element +61. The output signals of +7) and (8) are respectively amplified by Hall element amplifiers (10), (11) and (12) and supplied to a conversion logic circuit (13), where the energization period (on period) is 180 It is converted from ゜ to 120°. Each output signal from the conversion logic circuit (13) is sent to the switches (15) to (17) of the switch circuit (14), respectively.
) through the contact a side of the output amplifier (18) to (20)
It is supplied to stator coils (3) to (5) as motor coils, where it is amplified. This (10)
The portions (20) to (20) are used specifically to start the motor, and operate in a manner similar to conventional switching drive.

(21) is a zero cross detector that detects the zero cross points of each output signal of the amplifiers (10) to (12) and generates pulse signals at predetermined intervals; A clock generator (23) generates a predetermined number, for example, N pulse signals per cycle in response to a pulse signal, and (23) is a counter that counts pulse signals from the clock generator (22). ) is supplied to the waveform memory (24) as part of the address signal. This waveform memo IJ (24) stores a driving waveform that reduces noise and torque ripple, such as a sine waveform obtained by dividing an electrical angle of 60° into N. In addition, the waveform memory (24) also includes amplifiers (10) to
Each output signal of (12) is supplied as part of the address signal. The output signal of the counter (23) and the amplifier (10)
) to (12), the driving waveform stored in the waveform memory (24) is read out using an address signal formed based on each output signal from (12). The output signal from the waveform memory (24) is D/A converted by the D/A conversion circuit (25), and then passed through the contact side of the switches (15) to (I7) to the output amplifiers (18) to (20). It is supplied to the stator coils (3) to (5).

(26) is a rotation speed detector provided on the output side of the zero cross detector (21), and at the time of startup, the zero cross detector (21)
During each period of the pulse signal from 1), there is a carry from the first counter (30) (Fig. 2) of the clock generator (22) as described later, so a low level signal is generated, but this carry When it disappears, a high level signal will be generated. The output signal of the rotation speed detector (26) is used as a switching signal for the switch circuit (14), and the switches (15) to (17) of the switch circuit (14) are activated when the output signal of the rotation speed detector (26) is low. When it is at level, it is connected to the contact a side, and when it is high level, it is connected to the contact side.

That is, the brushless DC motor is driven by the output signal from the conversion logic circuit (13) in the starting state, and is driven by the signal based on the driving waveform from the waveform memo 'J (24) in the steady state.

Circuit configuration and operation of main parts of G2 Figure 2 shows an example of a specific circuit configuration of the clock generator (22). In the figure, (30) is the first counter, and (31) is the latch circuit. , (32) is a second counter, (33) is a clock generator that generates a clock signal having a predetermined frequency, for example, 10 MHz, (3
4) is a frequency divider, (35) is an OR circuit, and the frequency divider (
The frequency division ratio of 34) is, for example, 1/10.

A signal S4 is supplied from the zero cross detector (21) to the reset terminal R of the counter (30), and the contents of the counter (30) are reset each time this signal S4 is applied.

The counter (30) is generated from the clock generation 5 (33) from the time it is reset, and is divided into 1/10 by the frequency divider (34).
The count value is latched in the latch circuit (31) when the next signal S4 is applied to the load terminal of the U-nochi circuit (31),
Furthermore, it is preset in a counter (32). When the contents of the latch circuit (31) are preset to the counter (32), they are inverted, that is, subtracted and preset to 0. For example, if the latched value is (1010), that is, 10, it is inverted. As a result, the value becomes (0101), that is, 5, and this value is preset in the counter (32).

A counter (32) sequentially counts clock signals from a clock generator (33) based on a preset value, and generates a carry, that is, a signal S5 when an overflow occurs. This signal S5 is supplied to the counter (23) (Fig. 1) and is also supplied to the counter (23) via the OR circuit (35).
32), and at this point the contents of the latch circuit (31) are again inverted and preset.

The counter (30) repeats the operation of counting a predetermined number of clock signals as described above when the signal S4 is supplied at a constant period Tm as in a steady state, but the counter (30) repeats the operation of counting a predetermined number of clock signals as described above. When the period of S4 becomes longer,
When more clock signals than a predetermined number are counted, an overflow occurs and a carry occurs. The presence or absence of this carry serves as a guideline for switching the level of the output signal S1s of the rotation speed detector (26) (FIG. 1). Also, as long as the counter (30) outputs a carry, the latch circuit (30)
1) cannot launch the contents of the counter (30), and therefore the counter (32) does not output the signal S5.

Overall circuit operation of G3 Next, the circuit operation of FIG. 1 will be explained with reference to FIGS. 3 and 4.

At startup, signals 81 to S3 as shown in FIGS. 3A to 3C are output to the output sides of the amplifiers (10) to (12), respectively. These signals S1 to S3 are supplied to a zero cross detector (2nd type), and a signal S4 as shown in the third diagram is obtained at the output side of the zero cross detector (2nd type) at the zero cross point.

The period of this signal S4 gradually decreases as the rotational speed of the motor gradually increases in the starting state, and becomes constant in a steady state. Therefore, in the initial stage of the startup state, the period of the signal S4 is longer than that in the steady state, so the first counter (30) of the clock generator (22) (Fig. 2)
overflows and generates a carry, and while this carry is occurring, the output signal StS of the rotation speed detector (26) is at the third
As shown in FIG. 1, it is at a low level.

Since the output signal SI6 of the rotation speed detector (26) is at a low level, the switches ((9 to ()) of the switch circuit (14)
17) are both connected to the contact a side, and the amplifiers (10) to (
12) output signals 81 to S3 are output from the conversion logic circuit (13).
) and the switch circuit (14) to the output amplifier (18).
) to (20), and the output amplifiers (18) to (20
) output terminals W, U and ■ are shown in Figure 3 H.

Signals 5141S12 and SIJ as shown in F and G are obtained. These signals are respectively stator coil (3) ~
(5), which drives the motor.

At the final stage of the start-up state, no carry from the first counter (30) of the clock generator (22) is generated during the period of the signal S4, so that the rotation speed detector (26)
The output signal S+s changes from low level to high level as shown in FIG. 3 (■). The high level of this output signal S1s causes the switches (15) to (
17) both switch to the contact side.

When the carry from the first counter (30) is exhausted, the clock generator (22) performs the normal operation as described above, and the clock generator (22) outputs a pulse signal S5 as shown in FIG. 3E. is generated. Clock generator (22)
measures the current period of the signal S4, and measures the predetermined number N in the next period.
It works to generate a pulse signal. For example, if the number N of pulse signals S5 generated by the clock generator HE (22) in one period of the signal S4 is 10, then in the third diagram and E, the period Tm-2 was measured, so the next period Tm, de1
I want to generate 0 pulse signals S5, but the next period Tm-t
is 1/2 or less time than the previous cycle Tm-2, so it is 5.
It is possible to generate only pulse signal S5 with period T
m, was measured, so the next period Tm is 10 (I want to generate a fixed pulse signal SS, but the next period Tm is the same as the previous period Tm-
Since there is less time than 1/2 from 1, 5 pulse signals S
Only 5 can occur. However, since the period]゛m has been measured, the next period Tm is 10 (I want to generate a fixed pulse signal, but the next period Tm+1 is the same length in time as the previous period Tm, so this time I will generate a fixed pulse signal. Number N, that is, 10 pulse signals S5 can be generated.

When a steady state is achieved in this manner, a predetermined number N of pulse signals S5 can be generated without fail in one cycle of the signal S4.

Then, the output signal S5 generated by the clock generator (22) is counted by the next stage counter (23), and the count value is used as part of the address signal in the waveform memory (
24), and the output signals 81 to S3 of the amplifiers (10) to (12) are supplied to the waveform memory (24) as part of the address signal, and the output signals 81 to S3 of the amplifiers (10) to (12) are supplied to the waveform memory (24) as part of the address signal. The drive waveform stored in the waveform memory (24) is read out by the address signal formed by the waveform memory (24). The drive waveform signal read out from the waveform memory (24) is D/A converted by the D/A conversion circuit (25), passes through the contact sides of the switches (15) to (17), and is sent to the output amplifier (18). ) to (20). As a result, the output terminals W, U, and ■ are supplied with signals 314. as shown in FIG. 3, H, F, and G. S12 and S13 are obtained.

In Fig. 3 H, F, and G, the broken line portion is originally the signal S4.
A predetermined number N, that is, 10 pulse signals S5 are generated in one period, and the corresponding driving waveforms are stored in the waveform memory (2
4) Since only half of the five pulse signals S5 were generated in the part that should have been read out, the broken line indicates the part of the driving waveform that should have been read out with the remaining five pulse signals S5 that were not generated. This is shown in the following.

Now, Fig. 4 shows the waveforms of each part in a steady state. In a steady state, output signals 81 to S3 as shown in Fig. 4 A to C are obtained on the output side of the amplifiers (10) to (12). It will be done. In addition, a fourth
A signal S4 with a constant period Tm as shown in the figure is obtained.

This signal S4 with a constant period Tm is sent to the clock generator (22).
and is also supplied to the rotation speed detector (26).

The clock generator (22) sequentially generates a predetermined number N, that is, 10 pulse signals S5 during one cycle TmO, as shown in FIG. 4. At this time, the first clock generator (22)
Since no carry is output from the counter (30), the output signal 31s of the rotation speed detector (26) is at a high level, so that the switches (15) to (17) are both connected to the contact side.

The signal S5 from the clock generator (22) is sent to the counter (2
3) and is counted, and the count value is supplied to the waveform memory (24) as part of the address signal. Further, signals St to S3 are supplied to the waveform memory (24) as part of the address signal.

Address signals based on signals 81 to S3 are stored in the waveform memory (
The driving waveform (sine wave waveform) stored in 24) is roughly divided, and the divided sections are specified more precisely by an address signal based on the count value of the signal Ss. For example, the third period Tm of the signal S4 in the fourth diagram
Then, the signal S and 82 specify the section from 30" to 90" of the driving waveform (corresponding to the signal Sfi in FIG. 4F, for example), and the section between them is sequentially specified by the pulse signal S5 in FIG. 4E. As specified.

In this way, the drive waveform signal read out from the waveform memory (24) using the count value of the signal S5 and the address signal based on the signals 81 to S3 is D/A converted by the D/A conversion circuit (25). , switch (16) , (
Signals 36 to s8 as shown in FIG. 4 FH are obtained at the contact sides of 17) and 15, respectively.

These signals 36 to S8 are output amplifiers (19), respectively.

After being amplified by (20) and (18), the stator coil (
4), (5) and (3), thereby driving the motor to rotate.

In addition, in this steady state, the switches (16) and (17
) and (15), signals 89-Ss1 as shown in FIG. 4--K appear, respectively.

H Effects of the Invention As described above, according to the present invention, the driving waveform stored in the memory is generated based on the detection output of the detection element that detects the main magnetic field for driving and the address signal formed based on the pulse of a higher frequency. Since the motor is driven by reading the FG, the FG and PG that were conventionally used are no longer required.
The configuration is simple and inexpensive. Furthermore, since the Hall element originally used for driving is also used for reading out the driving waveform of the memory, the configuration is simpler and less expensive.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing an example of the essential parts of the invention, and FIGS. 3 and 4 are used to explain the operation of FIG. 1. FIG. (1) is a rotor, (2) is a stator, (3) to (5) are stator coils, (6) to (8) are Hall elements, (13
) is a conversion logic circuit, (14) is a switch circuit, (2
1) is a zero cross detector, (22) is a clock generator, (
23) is a counter, (24) is a waveform memory, and (26) is a rotation speed detector.

Claims (1)

[Claims] A detection element that detects a main magnetic field for driving, a pulse generating means that generates a pulse with a higher frequency than the detection output of the detection element, and a memory that stores a predetermined driving waveform, A brushless DC motor, characterized in that the motor is driven by reading out a drive waveform from the memory using an address signal formed based on the detection output and pulses.