JPH01125965A - Device for connecting inter-substrate signal - Google Patents
Device for connecting inter-substrate signalInfo
- Publication number
- JPH01125965A JPH01125965A JP28327087A JP28327087A JPH01125965A JP H01125965 A JPH01125965 A JP H01125965A JP 28327087 A JP28327087 A JP 28327087A JP 28327087 A JP28327087 A JP 28327087A JP H01125965 A JPH01125965 A JP H01125965A
- Authority
- JP
- Japan
- Prior art keywords
- pin
- power supply
- board
- conductor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 11
- 239000004020 conductor Substances 0.000 claims abstract description 17
- 229910000679 solder Inorganic materials 0.000 claims abstract description 11
- 238000002844 melting Methods 0.000 abstract description 4
- 230000008018 melting Effects 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 abstract 1
- 239000011810 insulating material Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000004907 flux Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001209 Low-carbon steel Inorganic materials 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910052863 mullite Inorganic materials 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/032—Organic insulating material consisting of one material
- H05K1/0326—Organic insulating material consisting of one material containing O
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/306—Lead-in-hole components, e.g. affixing or retention before soldering, spacing means
Landscapes
- Multi-Conductor Connections (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は高密度な基板実装技術に係り、特に大型計算機
等に使用される大面積基板上に形成された電極を確実に
接続するのに好適な基板間信号接続装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to high-density board mounting technology, and is particularly applicable to securely connecting electrodes formed on large-area boards used in large-scale computers, etc. The present invention relates to a suitable inter-board signal connection device.
大型計算機等においては性能向上のために、高速に動作
する消費電力の大きな集積回路を高密度に実装すること
が行なわれている。このような基板の総消費電力は数百
ワ゛ットにも及び、将来さらに増加するものと予想され
る。In order to improve performance in large-scale computers, integrated circuits that operate at high speed and consume large amounts of power are mounted in high density. The total power consumption of such boards is in the hundreds of watts, and is expected to increase further in the future.
このような消費電力密度の大きな実装基板を実現するた
めに、特開昭６０−２４７９９２に記載されているよう
な方式が提案されている。第２図は上記提案の一実施例
を示す断面図である。集積回路を搭載する基板は信号配
線基板１０１および電源供給基板１０２からなる。信号
配線基板１０１の表面に、複数の集積回路チップ１をは
んだバンプ２ａを介して搭載し、また信号配線基板１０
１と電源供給基板１０２をはんだバンプ２ｂを用いて接
続する。ここで、はんだバンプ２ｂの代わりに、信号配
線基板１０１の下部にピン（ピンは図示せず）を取り付
け、これを電源供給基板１０２のスルーホール内に挿入
することで基板間の接続を行なってもよいということも
提案しである。In order to realize such a mounting board with high power consumption density, a method as described in Japanese Patent Laid-Open No. 60-247992 has been proposed. FIG. 2 is a sectional view showing an embodiment of the above proposal. The board on which the integrated circuit is mounted includes a signal wiring board 101 and a power supply board 102. A plurality of integrated circuit chips 1 are mounted on the surface of the signal wiring board 101 via solder bumps 2a, and the signal wiring board 10
1 and the power supply board 102 are connected using solder bumps 2b. Here, instead of the solder bump 2b, a pin (pin not shown) is attached to the bottom of the signal wiring board 101, and this is inserted into the through hole of the power supply board 102 to connect the boards. I also suggest that it is good.
集積回路チップ１の入出力信号は、はんだバンプ２ａお
よび信号配線基板１０１内の配線（図示せず）により相
互接続されている。またチップの消費電力は、電源供給
基板１０２内の厚い電源層４から、スルーホール５およ
びはんだバンプ２ｂ。Input and output signals of the integrated circuit chip 1 are interconnected by solder bumps 2a and wiring (not shown) within the signal wiring board 101. The power consumption of the chip is determined by the power consumption from the thick power supply layer 4 in the power supply board 102 to the through holes 5 and solder bumps 2b.
２ａを介して集積回路チップ１内部に供給される。It is supplied to the inside of the integrated circuit chip 1 via 2a.
このような１Ｎ！源供給方式を用いることにより電源供
給基板１０２から集積回路チップ１までの給電経路の抵
抗を小さくできるので、電源電圧のドロップ、ばらつき
を低く抑えることが出来る。1N like this! By using the power supply method, the resistance of the power supply path from the power supply board 102 to the integrated circuit chip 1 can be reduced, so that drops and variations in the power supply voltage can be suppressed.
上記従来技術では、電源供給基板内の電源層４に厚い金
属板を使用するため、信号配線基板１０１と電源供給基
板１０２の熱膨張係数の差が増大し、両者を接続するは
んだバンプ２ｂあるいはピンに大きな熱歪が生ずる。こ
の熱歪を吸収し、かつ計算機運用期間中断線しない長期
の熱疲労寿命を確保するためには、十分な長さの接続ピ
ンが必要になる。しかし一方、集積回路チップ１内部で
はある確率で多数の論理ゲートが同時に切り替わるため
、それに伴い接続ピンにも急激な電流変化が生じ、ピン
長を長くするほど大きなノイズが発生するという問題が
ある。In the above conventional technology, since a thick metal plate is used for the power supply layer 4 in the power supply board, the difference in thermal expansion coefficient between the signal wiring board 101 and the power supply board 102 increases, and the solder bumps 2b or pins connecting the two increase. Large thermal strain occurs. In order to absorb this thermal strain and ensure a long thermal fatigue life without interruption during computer operation, connection pins of sufficient length are required. However, on the other hand, since a large number of logic gates are switched at the same time within the integrated circuit chip 1 with a certain probability, a sudden change in current occurs in the connection pins accordingly, and there is a problem in that the longer the pin length is, the more noise is generated.
本発明の目的は、上記接続ピンの熱疲労寿命を十分確保
し、かつピン部分に発生するノイズを低減できる基板間
信号接続構造を提供することにある。An object of the present invention is to provide an inter-board signal connection structure that can ensure a sufficient thermal fatigue life of the connection pin and reduce noise generated in the pin portion.
上記目的は、接続ピンを同軸状に取り囲みがっ接続ピン
と絶縁された導体を設け、信号配線基板および電源供給
基板上に露出したグランド端子と上記導体とを電気的に
接続することによって達成される。The above object is achieved by providing a conductor coaxially surrounding the connection pin and insulated from the connection pin, and electrically connecting the conductor to the ground terminal exposed on the signal wiring board and the power supply board. .
上記手段により、接続ピンの電流が急激に変化しても、
グランド端子に接続された同軸状の導体にリターン電流
が流れることで磁束の変化が打ち消されるので、ノイズ
の発生が抑えられる。これにより、ピン長を長くしても
ノイズは増大せず、一方接続ピンに加わる熱歪は低減さ
れ、熱疲労寿命を伸ばすことができる。With the above means, even if the current of the connection pin changes suddenly,
A return current flows through the coaxial conductor connected to the ground terminal, canceling out changes in magnetic flux, thereby suppressing noise generation. As a result, noise does not increase even if the pin length is increased, and on the other hand, the thermal strain applied to the connection pin is reduced, and the thermal fatigue life can be extended.
以下、本発明を図に従って詳細に説明する。第１図は本
発明の実施例を示す断面図である。集積回路チップ１を
搭載する信号配線基板１０１は例えばムライトセラミッ
ク（熱膨張係数３．０×１０−’／℃）を用いて形成す
る。信号配線基板内には電源用スルーホール５ａ、およ
びグランド用スルーホール５ｂが形成されており、信号
配線基板上の電源端子６ａ、およびグランド端子６ｂと
それぞれ接続されている０次に信号配線基板の下部に１
円筒形の台座を有する円柱状のピン７と、これを同軸状
に囲む導体８、および両者の絶縁を保つ絶縁材９１以上
を一体化した接続ピンを１例えば金−ゲルマニウム等の
接合材を用いて接続する。このとき電源端子６ａとピン
７、グランド端子６ｂと同軸状導体８をそれぞれ接続す
る。一方、電源供給基板１０２は、厚さ数ｍｍの銅板（
熱膨張係数１７ Ｘ １０−６／’Ｃ）を絶縁材３を介
して複数枚積層したものである。電源供給基板１０２に
は貫通スルーホール１０を設けておき、接続ピンを挿入
後低融点はんだ（例えば融点１１７℃のインジウム−ス
ズ）を用いて電源層４ａとピン７を電気的に接続する。Hereinafter, the present invention will be explained in detail with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention. The signal wiring board 101 on which the integrated circuit chip 1 is mounted is formed using, for example, mullite ceramic (thermal expansion coefficient: 3.0 x 10-'/°C). A power supply through hole 5a and a ground through hole 5b are formed in the signal wiring board, and the zero-order signal wiring board is connected to the power supply terminal 6a and ground terminal 6b on the signal wiring board, respectively. 1 at the bottom
A connecting pin is made by integrating a cylindrical pin 7 having a cylindrical base, a conductor 8 coaxially surrounding the pin, and an insulating material 91 that maintains insulation between the two using a bonding material such as gold-germanium. Connect. At this time, the power terminal 6a and the pin 7, and the ground terminal 6b and the coaxial conductor 8 are connected, respectively. On the other hand, the power supply board 102 is a copper plate (
A plurality of sheets having a thermal expansion coefficient of 17 x 10-6/'C) are laminated with an insulating material 3 interposed therebetween. A through hole 10 is provided in the power supply board 102, and after a connecting pin is inserted, the power supply layer 4a and the pin 7 are electrically connected using a low melting point solder (for example, indium-tin with a melting point of 117° C.).
このとき同時に、同軸状導体８とブラング層４ｂも低融
点はんだを用いて接続する。At the same time, the coaxial conductor 8 and the blunt layer 4b are also connected using low melting point solder.
ピン７および同軸状導体８は軟鋼のような軟らかくかつ
電気抵抗の小さな材料を用いる。あらかじめ円筒形状に
加工成型し台座部分を設けた同軸状導体８および絶縁材
９に、ピン７を挿入することで同軸状ピンを形成する。The pin 7 and the coaxial conductor 8 are made of a soft material with low electrical resistance, such as mild steel. A coaxial pin is formed by inserting a pin 7 into a coaxial conductor 8 and an insulating material 9 that have been previously formed into a cylindrical shape and provided with a pedestal portion.
本実施例においては、計算機運用中の温度サイクルに伴
い発生する基板間の相対変位は約０．１４１１Ｉｌとな
る。ここで接続ピン（同軸状導体８を含めて）の直径を
約１ｍｍとすると、計算機運用期間約１０年間の熱疲労
寿命を保つためにはピンの長さが数ｍｍ必要となる。一
方集積回路チツブ１内部ではある確率で多数の論理ゲー
トが同時に切り替わるため、それに伴い接続ピンの電流
も急激に変動する。このときピン７が従来のように露出
していると、ピン７の両端に大きなノイズ電圧が発生し
、集積回路チップ１内部の論理ゲートを誤動作させてし
まうという問題がある。しかし本実施例ではピン７の電
流が急激に変動しても、同時に同軸状導体８にリターン
電流が流れるので磁束の変化が打ち消され、ノイズの発
生は抑えられる。従ってピンを長くしてもノイズ量は増
えることはない。In this embodiment, the relative displacement between the substrates that occurs due to temperature cycles during computer operation is approximately 0.1411Il. Assuming that the diameter of the connecting pin (including the coaxial conductor 8) is approximately 1 mm, the length of the pin must be several mm in order to maintain a thermal fatigue life of approximately 10 years during computer operation. On the other hand, since a large number of logic gates are simultaneously switched with a certain probability inside the integrated circuit chip 1, the current at the connection pin also fluctuates rapidly. If the pin 7 is exposed at this time as in the conventional case, there is a problem in that a large noise voltage is generated across the pin 7, causing the logic gate inside the integrated circuit chip 1 to malfunction. However, in this embodiment, even if the current in the pin 7 changes suddenly, a return current flows through the coaxial conductor 8 at the same time, so the change in magnetic flux is canceled out, and the generation of noise can be suppressed. Therefore, even if the pin is lengthened, the amount of noise will not increase.
以上の作用により熱疲労寿命を確保するためにピン長を
伸ばすことが可能となる。The above effects make it possible to increase the pin length in order to ensure thermal fatigue life.
以上のごとく本発明によれば、交流ノイズの増加を抑え
ながら、かつ熱疲労寿命の長い接続が可能になるので、
集積回路チップの高速化および基板実装技術の信頼性向
上に効果がある。As described above, according to the present invention, a connection with a long thermal fatigue life is possible while suppressing an increase in AC noise.
It is effective in increasing the speed of integrated circuit chips and improving the reliability of board mounting technology.
第１図は本発明の実施例の断面図である。第２図は従来
例を示す断面図である。
１・・・集積回路チップ、２・・・はんだバンプ、３・
・・絶縁材、４・・・電源層、５・・・スルーホール、
６ａ・・・電源端子、６ｂ・・・グランド端子、７・・
・ピン、８・・・同軸状導体、９・・・絶縁材、１０・
・・貫通スルーホール、１０１・・・信号配線基板、１
０２・・・電源供給基板。
第 ７１１
／
第 ２ 図
５ スルーホールFIG. 1 is a sectional view of an embodiment of the invention. FIG. 2 is a sectional view showing a conventional example. 1. Integrated circuit chip, 2. Solder bump, 3.
...Insulating material, 4...Power layer, 5...Through hole,
6a...Power terminal, 6b...Ground terminal, 7...
・Pin, 8... Coaxial conductor, 9... Insulating material, 10.
... Penetration through hole, 101 ... Signal wiring board, 1
02...Power supply board. No. 711 / No. 2 Figure 5 Through hole
Claims (1)
上記ピンと第二の基板の入出力端子を電気的に接続する
基板間信号接続装置において、上記ピンを同軸状に取り
囲みかつピンと絶縁された導体を設け、第一の基板のグ
ランド端子および第二の基板のグランド端子と上記導体
とを電気的に接続したことを特徴とする基板間信号接続
装置。 ２、上記第一または第二の基板の入出力端子をそれぞれ
の基板スルーホール内部に設け、上記第一または第二の
基板のスルーホールにピンを挿入し、はんだ固着したこ
とを特徴とする特許請求の範囲第１項記載の基板間信号
接続装置。[Claims] 1. Electrically connecting input/output terminals and pins of the first board,
In an inter-board signal connection device that electrically connects the pin to the input/output terminal of a second board, a conductor coaxially surrounds the pin and is insulated from the pin, and connects the ground terminal of the first board and the second board. An inter-board signal connection device characterized in that a ground terminal of a board and the conductor are electrically connected. 2. A patent characterized in that the input/output terminals of the first or second substrate are provided inside through holes of the respective substrates, and pins are inserted into the through holes of the first or second substrate and fixed with solder. An inter-board signal connection device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28327087A JPH01125965A (en) | 1987-11-11 | 1987-11-11 | Device for connecting inter-substrate signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28327087A JPH01125965A (en) | 1987-11-11 | 1987-11-11 | Device for connecting inter-substrate signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01125965A true JPH01125965A (en) | 1989-05-18 |
Family
ID=17663282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28327087A Pending JPH01125965A (en) | 1987-11-11 | 1987-11-11 | Device for connecting inter-substrate signal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01125965A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5337219A (en) * | 1991-06-24 | 1994-08-09 | International Business Machines Corporation | Electronic package |
-
1987
- 1987-11-11 JP JP28327087A patent/JPH01125965A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5337219A (en) * | 1991-06-24 | 1994-08-09 | International Business Machines Corporation | Electronic package |
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