JPH01125800A - Erasable programmable read only memory - Google Patents

Abstract

PURPOSE:To reduce dedicated areas for power source wiring and ground wiring by setting a write control circuit so that respective write control signal at the time of a write test operation can be set in an active state being shifted by a prescribed time, respectively. CONSTITUTION:The write control circuit 4 which sets one of the plural write control signals for an address signal at the active state in an ordinary write operation and sets all of the write control signals at the active states in the write test operation, and write circuits 5a-5d which transfer data from an input/output data bus to a prescribed digit line selected by respective column selection circuit when a corresponding write control signal is set at the active state are provided. In such a case, the write control circuit 4 is constituted so that the write control signals ZW0-ZW3 can be set at the active states sequentially being shifted by the prescribed time, respectively in the write test operation. In such a way, since the write current of each byte can be distributed, it is possible to suppress the maximum value of the write current in total at a low level, therefore, to reduce the dedicated areas for the power source wiring and the ground wiring.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a write-only memory that is capable of writing and erasing data, and particularly to a write-in memory that controls write operations during normal check operations and write test operations. The present invention relates to a writable and erasable read-only memory equipped with a control circuit.

[Conventional technology]

In recent years, writeable and erasable continuous-only memory (hereinafter referred to as gP)
In microcomputers and EliFROM embedded devices, the gF
ROM capacity is increasing. Therefore, these gPl(
1-chip microcomputer with built-in 0M and WP)LO
M embedded devices.

In order to shorten the test time when performing a write test of an EP ROM cell, a plurality of write circuits are provided to write multiple bytes of one byte of data into a gPkLOM cell at four times.

In this case, for example, if we assume that it takes 8 minutes to test 8 bytes of gPl (OM) by 1 byte normally, then an EFR with a 4-byte honor circuit will
In OM, the test time can be Fii/402 minutes.

FIG. 4 is a block diagram showing a general example of a conventional gFROM.

In FIG. 4, l is a memory cell array of 8 and 1,
2 is a row selection circuit for selecting a row of memory cell array 1; 3;
4b is a column selection circuit that selects a column of memory cell array 1;
5a to 5dFi are each 1-byte write circuit, 6rim output control circuit, 7 is a readout circuit,
An input/output data bus that handles 5rii bytes of data is shown.

Next, the convolution operation of the klROM and the operation of the write control circuit will be explained.

Normally, when testing a write operation for a memory cell array l of HPkLOM, address signals AD, ~ADs for selecting a predetermined memory cell, a write strobe signal WR for executing a write operation, a write voltage VPP, and input/output data are used. Writing is performed by applying write data from bus 8.

This write operation will be explained with reference to circuit diagrams of each part.

FIG. 5 shows an example of the row selection circuit 2.

This row selection circuit includes a decoder 21 that inputs an address signal AI), and a NAND circuit Oat that manually inputs the output of the decoder 21.
~G3n and inverters I21~G2o.

This row selection circuit 2 selects one of the row lines XO to X255 in response to an externally applied address signal AD1.

FIG. 6 shows an example of a circuit for one bit of the column selection circuit 301 bytes.

This column selection circuit 3 includes a decoder 31 that inputs an address signal AD, and a NAND circuit G3 that manually inputs the output of this decoder 31.
1%G3ff, and inverter I! It is composed of transistors L to I3m and column selection transistors Q s 1 to (hm).

This column selection circuit 3 sets one of the inverters ist to inverter 3rn to a high level in response to an externally applied address signal AD, and causes one byte worth of transistors Q! 1~Q
sm is turned on to transmit data from write circuits 5a to 5d to memory cell array 1.

FIG. 7 shows an example of a conventional write control circuit 4b.

This write control circuit 4b receives an externally applied address signal AD3 and is a NAND circuit G4. %G, 4 and inverter Lt
, Ia (hereinafter referred to as a write circuit selection gate), a write strobe signal WR, and a test mode signal MWR for writing 4 bytes to the memory cell array 1 at the same time to shorten the programming time. It is constituted by a NAND circuit 04s-Go (hereinafter referred to as a write circuit drive gate) which distinguishes between writing and drives the write circuits 58 to 5d.

In the normal mode (when the test mode signal MWR is at a low level), the W write control circuit 4b controls the write circuit selection gate NAND circuit G4. %G4. Set one of them to a low level to set the NA of the write circuit drive gate.
ND circuit G circuit-4S~on, that is, write control signal ZW
Write circuit 5 by setting one of o to ZW3 to a special level.
Select one from 3-5d.

In addition, in the test mode (when the test mode signal MWR is at a high level), the output of the NAND circuit G411 is at a low level, so the NAND circuit 04s of the write circuit rotation gate is
-, ,04, output (write control signals 2WO to 2W3)
If all are at high level, all write circuits 5a to 5d are selected.

In normal mode and test mode, write circuit 5a
FIG. 8 shows the power supply current characteristics (hereinafter referred to as write current characteristics) supplied to the memory cell array 1 from 5d to 5d.

This characteristic is that immediately after a write voltage and write data are applied to a memory cell with a low threshold voltage before writing, as the threshold voltage of the memory cell increases, the current flowing through the memory cell decreases. It shows that it will go.

The write current characteristics indicate that the maximum current flows immediately after writing, and as the writing operation progresses, the current decreases.

[Problem that the invention seeks to solve]

The above-mentioned conventional write/erase CTL-enabled memory is configured to write 4 bytes at the same time in the test mode, so the write current flows four times as much as in the normal mode of writing 1 byte. , Therefore, in order to make the current density of the metal wiring (% source wiring, ground wiring) that supplies power to each part including the memory cell array l formed on the semiconductor substrate equal to that during 1-byte writing, K is the power supply wiring of these wirings. It is necessary to quadruple the geometric dimensions of the power supply wiring and ground wiring, which increases the area occupied by the power supply wiring and ground wiring on the semiconductor substrate.
The drawback is that the current drive capability of the PROM writer, etc. must be increased.

An object of the present invention is to be able to reduce the maximum write current in the test mode, thereby reducing the area occupied by power supply wiring and grounding wiring, so that it can be used without increasing the current drive capacity of LSI testers, PROM writers, etc. It is an object of the present invention to provide a writable and erasable IVC calculation memory.

[Means for solving problems]

The present invention provides (1) a write control circuit that activates one of a plurality of write control signals corresponding to an address signal during a normal write operation, and activates all of the plurality of write control signals during a write test operation; and a write circuit for transmitting data from the input/output data bus to a predetermined digit line selected by a respective column select circuit when the corresponding write control signal is active. In the memory, the write control circuit has a configuration in which each of the write control signals during a write test operation is sequentially activated with a predetermined time lag.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 (at, [blIri, respectively, the first
FIG. 2 is a block diagram showing an embodiment of the present invention and a circuit diagram of a control circuit.

This embodiment is similar to the conventional writing system shown in FIGS. 4 to 7.
The difference from an erasable read-only memory is that the write control circuit 4 is activated so that during a write test operation (test mode), the program control signals ZWO to ZW3 are sequentially activated after a predetermined time interval. It is in the point that I made it.

This write control circuit 4 has an NA of a write circuit drive gate.
ND circuit G4. %G4. The output of the NkND circuit G41 that distinguishes between normal mode and test mode is sequentially delayed and inputted to one input terminal of 1 by delay circuits D41 to D4m, and the write control signals 2WO to ZW3 are delayed by a predetermined time in the test mode. It is designed to become active in sequence.

Next, the operation of this write control circuit 4 will be explained.

Since the normal mode is the same as the conventional example, the test mode will be explained.

When the externally applied master mode signal MWR and write strobe signal W become high level.

While the output of the NAND circuit G49 remains at a low level, the output of the NAND circuit a4m of the write circuit drive gate, that is, the write control signal ZWQ becomes increasingly active at a high level.

The output of the NAND circuit G49 is also input to the delay circuit D41, and after a predetermined time d1 has elapsed, the output of the NAND circuit G49 is input to the delay circuit D41. , that is, the write control signal ZWI becomes active.

Similarly, after a further time d2 has elapsed by the delay circuit D4□, the output of NANI)@U path OSS, that is, the write control signal Z
W2 becomes active, and then the delay circuit D43 activates the NAND circuit G4. , that is, the write control signal ZW3 becomes active.

Therefore, the write current flowing from each write circuit 5a to 5d to the memory cell array 1 is distributed (individually) as shown in FIG. can do.

FIG. 3 is a circuit diagram of a write control circuit showing a second embodiment of the present invention.

In this embodiment, all delay circuits D44 to D46 are connected directly to NA.
It is connected to the output terminal of the ND circuit Gll, and its output is inputted to the NAND circuit 047 e Ga4 # Ga5, respectively.

The write control signals ZWo to zW3 are sequentially activated by changing the delay amounts of these delay circuits D44 to D4g, and there is an advantage that the drive timing can be determined only by the delay amounts of each of the delay circuits D44 to D46.

〔Effect of the invention〕

As explained above, in the present invention, when writing multiple bytes during a write test operation, each byte is sequentially shifted by a predetermined time and written, so that the write current for each byte is distributed. The maximum value of the overall write current can be lowered, and therefore the area occupied by power supply wiring and wiring can be reduced, and the power supply driving capacity of LSI testers, PROM writers, etc. does not need to be increased. There are also effects that can be used.

[Brief explanation of the drawing]

Figure M1 (a) and [bl are a program diagram and a circuit diagram of a write control circuit, respectively, showing the first embodiment of the present invention. FIG. 2 is a write current characteristic diagram of the embodiment shown in the first factor,
FIG. 3 is a circuit diagram of a 611 circuit showing a second embodiment of the present invention, FIG. 4 is a program diagram showing an example of a conventional writable/erasable read-only memory, and FIGS. FIG. 7 is a circuit diagram showing a read-only memory c row selection circuit, a column selection circuit, and a write control circuit shown in FIG. 4, respectively. Figure 8 Iri! Writing of the programmable and erasable read-only memory shown in FIG. 4-ii! It is a cfAt characteristic diagram. 1...Memory cell array, 2...Row selection circuit. 3... Column selection circuit, 4, 4a, 4b...
r-iLF included control circuit, 5a to 5d... commitment circuit, 6... d output control circuit, 7...
・Readout circuit, 8... Input/output data bus, 21
．． 31...Decoder, D41-D46...
...Delay amount Wb, G! 1~o, 1Gst~G3-.
G41 to G49...NAND circuit, I21,
1 unit, 31~I'mI41""'I4m...
Inverter* Qst-Qsm, old...transistor. Agent: Susumu Uchihara, Patent Attorney) Figure 1 Figure 2 Figure 3 Hand Figure 4 Cow S Concave ζ

Claims (1)

[Claims] a write control circuit that activates one of the plurality of write control signals corresponding to the address signal during a normal write operation, and activates all of the plurality of write control signals during a write test operation; When the write control signal is active, the write/erasable read-only memory has a write circuit that transmits data from an input/output data bus to a predetermined digit line selected by a column selection circuit, respectively. A writable and erasable read-only memory, characterized in that the control circuit is configured such that each of the write control signals during a write test operation becomes active sequentially with a predetermined time lag.