JPH01125798A - Redundancy roll call method for dynamic memory - Google Patents

Abstract

PURPOSE:To detect the address of a substituted decoder without receiving the fluctuation of a process by controlling the output of a redundancy detection circuit by one of external row addresses of a row decoder at the time of performing the counter checking of a refresh address counter in a dynamic memory. CONSTITUTION:The information of an external address terminal XA is fetched at the time of access by counter check, and a fetched information level and an output level detected by the redundancy detection circuit 1 are received and outputted to the external terminal XA only at the time of access by the counter check. Thereby, no influence is given on ordinary access, and no influence is given on the access by the counter check by controlling the information level of the external terminal XA. In such a way, it is possible to detect the address of the substituted decoder without receiving the fluctuation of the process with high reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a redundancy roll call method for a dynamic memory, and particularly to a redundancy roll call method for a dynamic memory having a counter check function.

[Conventional technology]

2. Description of the Related Art In recent years, the capacity of semiconductor memories has increased and memory cell arrays have become smaller and smaller, and the incidence of failures during the manufacturing of memory cell arrays has also increased. Therefore, a method is currently being used to remedy the failure by adding a redundancy circuit. This circuit prepares a plurality of extra sets of word lines used when accessing memory cells and row decoders that select them, and bit lines and column decoders that select them. If there is a line failure, the memory cell array is saved by replacing it with a redundancy circuit.

However, replacement with a redundancy circuit is usually performed at the wafer test stage. Once the product is assembled into a package and manufactured, it is not easy to know which row decoder or column decoder has been replaced. Therefore, a method of knowing the address of the replaced decoder, ie, a redundancy roll call method, has been developed.

FIG. 3 is a circuit diagram used in the conventional redundancy roll call method. The circuit and its operation in FIG.
) and column decoder address CAi (i=11~l
transistor Qi (i=11~in) inputting n)
The circuit is configured in series with the series circuit and the series circuit. For example, if the column decoder selected by the column decoder address CAl2 has a failure, the fuse F12 is blown in order to replace the column decoder with a redundancy circuit. Therefore, the node that is precharged by the P-channel transistor Q10 to which the precharge signal φP is input will not be discharged even if the column decoder address CAl2 changes from the ground potential (hereinafter referred to as GND) to the power supply potential (hereinafter referred to as cc). Therefore, the output φas of the redundancy detection circuit 1 remains at VCC. When not replaced with a redundancy circuit, the output φas changes from VtffC to GN
Changes to D.

On the other hand, when the redundancy circuit is replaced, the fuse F20 of the redundancy determination circuit 2 is blown. Therefore, when the fuse F12 is blown and the column decoder address CAl2 is specified, the output φR8 of the redundancy detection circuit 1 is Vcc, and the counter check signal φ used when checking the refresh counter is output.
When R12 becomes VCC, the output of ANDl, which takes the AND of the output φRs and the counter check signal φR12, becomes VCC.
becomes. Therefore, the output N of N-channel transistor Q21
The potential of 21 is a potential ■ lower than GND and Vcc by the threshold voltage of Q21 (hereinafter referred to as V↑). . -V
It becomes t. Therefore, the potential of N22 can be increased from the previous potential by capacitor C2. For example, if the potential of the external terminal DO2, which also serves as an output terminal, is Vcc + 2V T for determination, then N23 is VCC
+VT, and by boosting N22 above VCC+VT, current can flow from N23 to the internal power supply through N-channel transistor Q24. If the column decoder selected by column decoder address CAl2 has not been replaced, the output φ of redundancy detection circuit 1
By setting R5 to GND, N21 remains GND and N
22 is not boosted. Therefore, even if the potential of external terminal DO2 is raised to raise the level of N23, no current will flow to the internal power supply through N-channel transistor Q24.

In the conventional roll call method, the decoder being replaced is known based on the presence or absence of a current value flowing from an external terminal to a power supply inside the memory, using the circuit and operation described above.

[Problem that the invention seeks to solve]

In the conventional redundancy roll call method described above, the determination is made based on the presence or absence of current from the external terminal to the internal power supply, so measurement that is susceptible to process fluctuations such as Vt is required, and replacement is not required. , otherwise the fuse F20 is not blown, which has the disadvantage that leakage current easily flows from the output terminal DO2 to the internal power supply. Furthermore, when replacing, the fuse is blown, which has the disadvantage of lowering reliability.

An object of the present invention is to set the output of the redundancy detection circuit to one of the external row addresses of the row decoder when checking the refresh address counter of the dynamic memory.
It is an object of the present invention to provide a redundancy roll call method that does not require the use of a fuse for replacement display in a redundancy determination circuit and does not require measurement of the magnitude of internal current by controlling by one.

[Means for solving problems]

The redundancy roll call method of the present invention has a counter circuit that internally generates a refresh address, a counter check function that accesses a memory cell based on the address, and a redundancy circuit that replaces a faulty element. In dynamic memory,
The AND output of the level of the information on the external row address terminal taken in at the time of access by the counter check function and the output level of the circuit for detecting the column address that selected the redundancy circuit is outputted to the external terminal at the time of access by the counter check function. It is configured by using the control input as follows.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of the present invention, and FIG. 2 is a timing diagram of various input clock signals and internal nodes in FIG. Further, in FIG. 1, the same reference numerals as in FIG. 3 represent the same things, and in this example, the determination terminal also serves as one of the output terminals.

The address switching circuit 3 selects one external row address and one output of the internal refresh address counter 31 by a selector 32 to which a switching control signal φ8□1 is input, and outputs a row decoder address RAI. This output RAI is used to select the row decoder that drives the word line. The redundancy detection circuit 1 is the same as the conventional circuit shown in FIG.
If the column decoder selected by Al2 is out of order, the fuse F12 is blown and the output φR5 remains at Vcc. The redundancy determination circuit 4 receives the external row address, the redundancy detection signal φλS, and the counter check signal φR12, and outputs GND to the output terminal DO1.

Next, the operation in FIG. 1 will be explained with reference to FIG. 2. FIG. 2 is a timing diagram when fuse F12 in FIG. 1 is blown, and FIG. A write operation to a cell is shown, and FIG. 2(b) shows a write operation at the time of counter check. Figure 2(a)
Since the switching control signal φR11 is GND, the row decoder address RAI for selecting the row decoder is connected to the external row address terminal XA and the address inverter control signal φA.
It becomes the level of the node Nil determined by the positive and negative logical product NAND1 with ll. That is, in FIG. 2(a), since XA is "1", RAl is GND. On the other hand, ``Column decoder address CAL for selecting the failed column decoder, 2
becomes VCC, but since the fuse is blown, the node charged by the precharge signal φP is not discharged,
The output φR5 of the redundancy detection circuit 1 is VCC.

Counter check signal φ3. which is generated with a time difference from switching control signal φλ11 when checking the counter.
2 is GND, the output N12 of the AND2 is GND, and the N-channel transistor Q41 is not turned on, so the output terminal Dot is in a high impedance state. Note that even in the read operation from the memory cell, the counter check signal φRI2 is at GND, so the N-channel transistor Q41 is not turned on, so the read operation is not hindered. Furthermore, even if none of the fuses are blown, the output φR5 becomes GND, so the N-channel transistor Q41 is not turned on and does not interfere with the operation of the output terminal Dot in write and read operations.

In FIG. 2(b), the switching control signal φR11 becomes VCC for counter check, and the row decoder is selected by the address by the refresh address counter 31. At this time, by taking the time difference from φR11 and setting the address inverter signal φAll to VCC, "1" is taken from the external row address terminal XA and N11 is set to GND. Therefore, as described above, the column decoder address CAL2 is set to VCC. Then, since the fuse F12 is blown, the output φR8 becomes VCQ.Therefore, the counter check signal φR12, which is generated with a time difference from the switching control signal φR11 at the time of counter check, becomes VCC, so that N12 becomes VCC and the N channel The transistor Q41 turns on and the output terminal DOI becomes GND.

In addition, when reading when checking the counter, by taking in "'O゛'" from the external row address terminal XA,
N12 can be set to GND, turning off the N-channel transistor Q41, without interfering with the operation of the output terminal DOI. Furthermore, even if none of the fuses are blown, the output φR5 becomes GND, so the N-channel transistor Q41 is not turned on, and the operation of the output terminal D01 is not hindered in the read operation.

〔Effect of the invention〕

As explained above, the present invention captures information on an external address terminal when accessing by counter check, receives the level of this captured information and the output level detected by the dundancy detection circuit, and then uses the external address terminal only when accessing by counter check. Output to the terminal. Therefore, normal access is not affected, and access by counter check is not affected because the information level of the external address terminal is controlled. Therefore, there is an effect that the address of the replaced decoder can be detected with high reliability without being subject to process variations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a timing diagram showing the operation of the circuit shown in FIG. 3, and FIG. 3 is a block diagram of a conventional redundancy roll call method. 1... Redundancy detection circuit, 2.4... Redundancy determination circuit, 3... Address switching circuit, QIO...
・P channel transistor, Qll~Qln, Q21~
Q25. Q41...N channel transistor, Nil
, N12. N21~N23...Node, Fl 1~F
1 n, F20- Fuse, C21- Capacitor, CAII to CA1n Column decoder address, XA External row address terminal, φP Precharge signal, φAll Inverter control signal, φR
11...Switching control signal, φR12...Counter check signal, RAI...Row decoder address.

Claims (1)

[Claims] In a dynamic memory that has a counter circuit that internally generates a refresh address, a counter check function that accesses a memory cell based on the address, and a redundancy circuit that replaces a faulty element, the counter check function The AND output of the level of the information of the external row address terminal taken in at the time of access and the output level of the circuit for detecting the column address that selected the redundancy circuit is used as the control input of the external terminal at the time of access by the counter check function. A dynamic memory redundancy roll call method characterized by: