JPH01125624A - Information retrieving device - Google Patents

Abstract

PURPOSE:To increase information retrieving speed by using a memory part which stores the data showing the information having the key words corresponding to each area, an arithmetic part which performs the logical operation of data, and a clock control part. CONSTITUTION:An AND operation is carried out between both data on 1st and 6th areas of a RAM part 11 in response to a high frequency clock signal received from a clock control part 14. The result of this AND operation is temporarily stored in a 1st buffer circuit 24. Then a CPU 12 delivers a base address to reset an address counter part 18 and produces successively the offset addresses equivalent to one and two addresses to give them to the part 11 via a 3rd multiplexer 17. Thus the result of the AND operation is stored in a processing area of the RAM 11. The data on the RAM 11 is read out every 8 bits in accordance with the base and offset addresses and applied to a gate circuit 25. As a result, the CPU 12 can detect a specific register number of the retrieved information.

Description

DETAILED DESCRIPTION OF THE INVENTION 0) Industrial Application Field The present invention relates to an information retrieval device for searching a large amount of image information stored in a mass storage medium using keywords.

- As one of the conventional technical information retrieval devices, an information file is configured to register information using search data in a large-capacity storage medium such as an optical disk, and to search desired information from the registered information based on the search data. The device is already known, as seen in Japanese Patent Application Laid-Open No. 57-150885.

In such an information file device, when information is registered, information such as documents and drawings is stored in a storage medium such as an optical disk, while keywords input from a keyboard or multi-item input device include the storage location of the information in the storage medium. is stored in the search data storage section. In addition, when searching for registered information, keywords related to the desired information and A N '1
:Search, OR test search isometric search conditions By inputting a search from the keyboard or multi-item input device, the keywords in the storage unit where the keywords are stored are compared based on the search conditions, and the matching keywords are searched. are displayed on the field as a search result list. Desired information is read from the storage medium by selecting a desired keyword from the search result list and instructing reading of the information.

(c) Problems to be Solved by the Invention In such information retrieval devices, high-speed retrieval processing is required. However, conventionally, such search processing (i.e.,
The clock signal used for operations (AND search, OR search, etc.) has limitations in increasing the speed of search processing since the same signal is used to control the entire device.

B.) Means for Solving the Problems The present invention provides an information retrieval device that registers information using nine keywords set in advance in a storage medium and searches desired information from the registered information based on the keywords. a storage unit having nine storage areas associated with each of the keywords, each area storing data indicating information having the keyword associated with each area; and data in at least two areas within the storage unit. and a clock control section that generates a high-frequency clock signal that controls the input/output of data in the storage section and the operation of the operation section.

B) Function According to the present invention, a dedicated clock control unit for keyword search is provided, and keyword search is performed in response to a high frequency clock signal generated from the clock control unit.

(F) Embodiment FIG. 1 is a block diagram showing the configuration of an information file device as an embodiment of the present invention.

(1) is a scanner that reads information such as documents and drawings, (2) is a keyboard that inputs instruction signals such as keywords and information registration and search related to the information input from scanner (1), and (3) ) is an optical disk that stores information input from the scanner (1), (4) is a search section that performs keyword searches, and (5) is a system control section that controls the operations of each of the above sections.

Nao, the keywords entered from the keyboard (2) are:
A plurality of keywords are set in advance, and the keywords are selected from among these keywords and input. Also,
The system control unit (5) generates serial numbers (hereinafter referred to as registration numbers) in the order in which information is registered, and associates each of these serial numbers with each information storage address on the optical disc (3). I remember that.

FIG. 2 is a block diagram showing details of search a (41).

fiD is a RAM unit that stores the correspondence between the registered information and the keyword input from the keyboard (21). Regarding the storage format of the storage area that stores the above correspondence in such RAM ff1sfill, the keyword A to keyword Figure 3 shows an example of registering 24 pieces of information using 6 keywords in 7t.) (The AM part αυ corresponds to each of the 6 keywords from keyword A to keyword F. 1st area (a
) to the sixth area (f).

Each area (IL) to (f) has a size corresponding to three addresses. The content of one address consists of eight bits of information, and one piece of information is associated with one bit of information in each address in order of registration number.

Therefore, if the keywords A, B, and Dd (information of the third registered information record number 3) are associated with the keywords A, B, and Dd, the first
The first address 100 of area (a), the first address 105 of the second area (b), and the first 11 of the fourth area ((1)
°1 is set in the third bit from the top of each address 5. Also, keyword B is the 12th registered information (information with registration number 12).

1 in the second area (b) if D and F are associated with each other.
4th bit from the top of address 06 (i.e., second area c
'b), the 12th bit from the beginning of address 105), the 4th bit from the top of address 116 of the fourth area (+1) (i.e., the 12th bit from the beginning of address 1°15 of the fourth area (1) ) and the fourth bit from the top of the 126th address of the sixth area (f) (that is, the 12th bit from the top of the 125th address of the sixth area (f)) are set with °1.

In this way, the correspondence between information and keywords is stored in the RAM section fiυ. Note that in the storage format in the RAM section aυ, the number of areas is determined according to the number of keywords, and the size of the area is also set according to the number of information to be registered.

Furthermore, in addition to the above-mentioned areas, the RAM section an also has the functions of AND search, O
It has a processing area (X) starting from address 200 and having a size equivalent to the size of at least one area used for the R search.

Again in Figure 2, the opv that sends various control commands from α3 company
Sa3I is an I10 port that receives various signals from OPU (L) and outputs various control signals, and fill has a frequency 2 to 3 times higher than the basic clock signal OK of about 5MH1, which controls the entire device. high frequency clock signal 0
The clock control unit aS that outputs Kil outputs the basic clock signal OK and the high frequency clock signal 0Kil as I10.
a first multiplexer that appropriately switches and outputs to the RAM section al according to a link a switch signal from the boat section r13;
11e is a second multiplexer that switches the start address (hereinafter referred to as pace address) of each area and processing area of the storage area in the RAM 15 (lυ) and outputs the RAM 1lS (11)K, and the fin is an offset address that is incremented sequentially from 1. The sum of the pace address and the offset address given from the second multiplexer αe and the third multiplexer (17) is output to the RAM section a.
This indicates the predetermined address of the file. For example, if the start address 110 of the sixth area (CI) is output from the second multiplexer (161) as a pace address, and address 1 from the fifth multiplexer is output as an offset address, then address 111 of RAM1iSQn (
The second address in the sixth area (6) remains as specified. Also, from the above state, if the pace address output from the second multiplexer (1e) is changed to address 120 (the first address of the fifth area (e)) (the offset address remains at address 1 and does not change), 1 .RAM
Address 121 of (11) becomes the designated one. 2 is an address counter that supplies an offset address to the third multiplexer riD under the control of the clock control unit f141, al is a RAM unit, (1) is a first latch circuit that latches 8-bit data read from 1υ, The 8-bit data latched in the first output circuit l and the 2
After that, RAM5 (AND gate, !21 that performs an AND operation with the 8-bit data read out from lυ) combines the 8-bit data latched in the first latch circuit (19) with the 8-bit data read out from RAM1lS (lυ). 8 read from
OP gate e which performs ooR operation with bit data p, (2
Calculation contents by 3tiAND gate ■ and OR game) (
21, a fourth multiplexer selectively outputs the calculation contents of the fourth multiplexer; @ is a second latch circuit that latches the data t output from the fourth multiplexer with the clock signal OKm from the lock control unit I; @ is the second latch circuit; 2. The first buffer circuit (if) controls the timing of sending data output from the latch circuit @ to the RAM section aυ; (iff) is the RAM section fi;
A gate circuit that monitors the 8-bit data content output from D and outputs a detection signal to op17α and the clock control unit I if the content is not all °01, (to) R
AM section fllK When storing new data, RAM section a
This is a second buffer circuit that connects V and the data bus.

According to the information retrieval device having such a configuration, the retrieval unit (4) during the information retrieval operation is controlled by the high-frequency clock signal OKB provided exclusively for the retrieval operation or output from the a-tock control unit a4.
Because this is done by , high-speed processing can be performed.

First, to explain the search operation in this embodiment, the registration of information will be briefly explained using the scanner (1).
The information input from the optical disc (3) is stored on the optical disc (3). At this time, the system control unit (5) generates a registration number for the input hole information, for example, a registration number 23, and stores this registration number 23 in association with the storage address of the information on the optical disc (3). On the other hand, a keyword selected from a plurality of preset keywords, for example, keyword A
is input from the keyboard (2), the bit corresponding to the registration number 23 of the information input from the scanner (11) in the first area (a) of the RAM 1'lSQυ in the search unit (4), that is, the first "11" is set in the seventh bit from the top of address 102 in area (a).In this way, the information with registration number 25 is registered with keyword A.

Next, regarding the operation of this embodiment, A
An example of performing an ND search (see FIG. 3) will be explained.

First, a clock switching signal is applied to the first multiplexer (151) via the OPU (t21h I10h) section fi3t-, and the clock control section a4 is activated.

In this state, apvttz outputs the pace address (address 100) of the first area (a) corresponding to the keyword AK. This pace address (address 100) is given to the second multiplexer ae via the I10 port section (13'i), and then to the gCRAM section fiυ.Thereby, the pace address (address 100) is stored at address 100 in the first area (IL). There are 8
Bit data is also read out from the RAM section al and stored in the first latch circuit a9.

Next, when the OPU (1m is the pace address (address 125) of the 6th area (・) corresponding to the keyword F) is outputted, this pace address (address 125) is sent to the second multiplexer a through the port section a3t-.・Given to
Furthermore, the RAM section (lnK) is given.As a result, the 8-bit data stored at address 125 in the sixth area (f) is read out from the RAM section aυ and given to the AND gate (2).At this time, the first latch The 8-bit data at address 100 of the first area (a) stored in the circuit a9 is also given to the AND gate ■.Therefore, the first area (a)
100 and 125 of Area 6 (f).
AND operation of bit data is performed by AND gate (2G1C
The result is output to the fourth multiplexer 123.

Since the fourth multiplexer is set to output the data from the AND gate ■, the operation result data of the AND gate ■ passes through the fourth multiplexer 123 feet, is latched to the second latch circuit, and then is transferred to the first buffer. When the 8-bit data at address 125 of the 6th area 7(f) 17) is read from the RAM 15(If), the 2nd multiplexer t1e becomes 1 again.
The pace address of address 00 is given to the RAM 11S (113).Furthermore, under the control of the clock control section fi-, the offset address of address 1 generated in the address counter (II) is sent to the RAM section a via the third multiplexer ant.
applied to υ. As a result, the RAM section (from 11 to 1st
The 8-bit data at address 101 in area (IL) is read out, and this data is temporarily held in the first latch circuit a9.

Next, the second multiplexer a11 gives the pace address of address 125 to the i'lAM section (ill. At this time, the third multiplexer aη gives the offset address of the 1st address to the RAM MISflnK. Therefore, the sixth area ( 8-bit data at address 126 of f) is read out.

In this way, the 8-bit data at addresses 101 and 126 read from the FIAM section α1) are
Similar to the case of the data at addresses 00 and 125, the data is subjected to an AND operation by the AND gate (2) and then stored in the first buffer circuit (24).

After that, the second multiplexer ae is again connected to address 100 and 1.
The pace address with address 25 is sequentially stored in the RAM section (IIIK
give. 9. The address counter side generates an offset address for the 2nd address, and this offset address is used as the 3rd address.
The 8-bit data at address 102 of the first area (SL) and address 127 of the sixth area (f) are sequentially read from the RAM section aD by the 0 given to the RAM section αυ by the multiplexer aη. AND
After being subjected to an AND operation by gate (2), O is stored in the first buffer circuit 1241. Thus, in response to the high frequency clock signal CKM from the clock control section (ri), the first area (SL
) and the sixth area (f), and the results are temporarily stored in the first buffer circuit (24).

After sono, opvttz RAMWfill! Set to data writing state, pace address (200) of processing area (X)
address) is output. Subsequently, after resetting the address counter fi seconds to -H, the address counter a generates offset addresses for the 1st address and the 2nd address in order under the control of the clock controller fi-, and these offset addresses are sequentially sent to the 3 multiplexers. RAM section tl via aη
DK is given. As a result, the first buffer circuit 124
The AND operation result (see Figure 3) stored in RA
Processing area from address 200 to address 202 of M section on (
X).

In this way, AND with keyword A and keyword F
When the operation is completed, the data stored in the processing area (X) of the RAM section aυ is read out in 8-bit units in sequence according to the pace address and offset address given by the second multiplexer αe and the fifth multiplexer (11), and The ◇Goo 4 circuit ■ that is applied to the circuit (c) monitors the contents of the applied data bit by bit, and checks which bit from the uppermost bit is set to ``1.''.

When the gate circuit (c) detects the content of °1, it outputs a detection signal to the CPU side. This results in
The CPU (15) can detect which registration number information has been retrieved. In this embodiment, as is clear from FIG. This is what was searched for.

In this way, when the registration number is detected at 0PU (13),
This registration number is sent to the system control section (5).

Therefore, the system control unit (5) selects the optical disc (3) based on the storage address associated with the registration number.
) can read information.

In addition, in this example, when performing an OR search,
According to the present invention, when a large amount of information is searched by keyword, AND search and OR search can be performed at high speed, thereby speeding up the search.

[Brief explanation of the drawing]

1 to 4 relate to one embodiment of the present invention, FIG. 1 is a block diagram, FIG. 2 is a detailed block diagram of the search section, FIG. 3 is an internal form diagram of the RAM section, and FIG. 4 is a block diagram of the search section. It is a schematic diagram explaining AND operation. (111'-RAM part, [3・ap tr, (
f4)/ay control unit, Cl)/AND gate, 1211-OR gate.

Claims (1)

[Claims] (1) In an information search device that registers information using keywords set in advance in a storage medium and searches desired information from the registered information based on the keywords, a storage area is associated with each of the keywords. a storage unit that stores, in each area, data indicating information having a keyword associated with each area; and an arithmetic unit that performs a logical operation on data in at least two areas within the storage unit; An information retrieval device comprising: a clock control section that generates a high frequency clock signal for controlling data input/output in the storage section and operation of the arithmetic section.