JPH01124192A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To easily discriminate whether a memory cell itself has a problem or malfunction takes place depending on the pulse width of a pulse output by selecting the pulse output or the output of a buffer circuit according to a logic level of a mode selection signal so as to use the result as a control signal. CONSTITUTION:A timing generator 4 includes a buffer circuit receiving a clock signal CLK and giving an output and a selection circuit selecting either a pulse output or the output of the buffer circuit depending on the logic level of a mode selection signal TES and using the result as a control signal. Thus, based on the pulse output of a predetermined pulse width, a semiconductor memory device writes or reads the data and when a malfunction takes place, the selection signal TES controls the timing generation circuit 4 to output a clock signal in place of the pulse output via the buffer circuit and whether malfunction takes place in relation to the pulse width of the pulse output or the memory cell itself has a problem is easily discriminated by varying the pulse width of the clock signal optionally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device that operates in synchronization with a clock signal.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional semiconductor memory device, and FIG. 5 is a circuit diagram showing details of the timing generator 14 in FIG. 4.

The timing generator 14 outputs the clock signal CLK and the lead/
A write signal R/W is input, a decoder enable signal DEos, a sense amplifier enable signal SEo, and a data in enable signal QDIE.

Output.

The row address decoder 2 and the column address decoder 5 each receive a row address and a column address, and decode the input row address and column address when the decoder enable signal DEo is active. The data input section 3 reads and outputs the write data of which the data in enable signal DIEo is active. memory 1
When the read/write signal R/W is at a high level (hereinafter referred to as H), it is instructed by the decode outputs of the row address decoder 2 and column address decoder 5 to output the data of the I memory hill, and output the read/write signal. R/W
When is at a low level (described hereafter), the data output from the data input section 3 is stored in the memory cell designated by the decoded outputs of the row address decoder 2 and column address decoder 5. The sense amplifier 7 uses the data output from the memory cell as a sense amplifier enable signal SE.
When o is active, it is amplified and output. The data output section 8 synchronizes with the rising edge of the clock signal QCLK.
The output of the sense amplifier 7 is input and output as output data.

Next, details of the timing generator 14 will be explained with reference to FIG.

The delay element 41 inputs the clock signal CLK, delays it by a predetermined time To, and outputs it. The exclusive OR circuit 40 performs an exclusive OR operation on the clock signal CLK and the output of the delay element 41, and outputs a one-shot pulse with a pulse width To as the decoder enable signal DEo. The AND circuit 44 receives the read/write signal R/
Take an AND between W and the decoder enable signal DEo,
It is output as a sense amplifier enable signal SEo. Inverter 45 inverts the logic level of the output of exclusive OR circuit 40. Exclusive Noah circuit 46
takes the exclusive NOR of the read/write signal R/W and the output of the inverter 45 and outputs it as the data-in enable signal DIEo.

Therefore, the decoder enable signal DEo, the sense amplifier enable signal SEo, and the data-in enable signal DIEo are all active for a period of 11 from the up edge of the clock signal CLK until the delay time T defined by the delay element 41 has elapsed. fixed between. In this semiconductor memory device, if writing and reading are not completed within the one-shot pulse generation period of the exclusive OR circuit 40, the information being written and the information being read will be destroyed. If the operation is delayed, there is a problem that a complete malfunction may occur. In that case, it is very difficult to clarify whether the cause of the malfunction is a problem with the memory cell itself or a delay in write or read operations.

(Problems to be Solved by the Invention) The conventional semiconductor memory device described above has a clock signal CLK.
A one-shot pulse is generated that rises in synchronization with the up edge of , and has a fixed pulse width of delay time To by the delay element 41, and write and read operations are performed based on the generated one-shot pulse. If a malfunction occurs because the high J3 and successive operations cannot be completed within the shot pulse period, it is very important to clarify whether the cause of the malfunction is a problem with the memory cell itself or a delay in write and read operations. The drawback is that it is difficult to perform and requires a large amount of time for circuit evaluation.

[Means for solving problems]

The semiconductor memory device of the present invention includes a buffer circuit that inputs and outputs a clock signal, and a selection circuit that selects a pulse output or an output of a balance circuit according to the logic level of a mode selection signal and uses it as a control signal. , the Jf-conductor memory device is caused to input or read data based on a pulse output with a preset pulse width, and if a malfunction occurs, the timing generation circuit is controlled by a selection signal and the pulse Did the malfunction occur in relation to the pulse width of the pulse output by outputting a clock signal through a buffer circuit instead of the output and arbitrarily changing the pulse width of the clock signal?
You can easily determine whether there is a problem with the memory cell itself.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the semiconductor memory device of the present invention, FIG. 2 is a circuit diagram showing details of the timing generator 4 of FIG. 1, and FIGS. 3(a) and 3(b) are timing diagrams. Generator 4
FIG. 2 is a waveform diagram showing the operation of FIG.

This embodiment differs from the conventional example shown in FIG. 4 in the timing generator 4 and NOR circuit 6.

The timing generator 4 receives the clock signal CLK and the clock signal CLK.
Input the write signal R/W and the mode selection signal TES, send the decode enable signal JADE to the row address decoder 2 and column address decoder 5, send the sense amplifier enable signal SE to the sense amplifier 7, and send the data in enable signal DIE to the data. The signals are output to the input section 3, respectively.

The NOR circuit 6 performs a NOR operation on the clock signal CLK, the mode selection signal, and TES, and outputs the result to the data output section 8.

Next, details of the timing generator 4 will be explained with reference to FIG.

The delay collector 41 inputs the clock signal CLK and determines the time To.
output with a delay. Exclusive Noah circuit 4
2 takes an exclusive NOR between the clock signal CLK and the output of the delay element 41.

Inverter 43 inverts the logic level of clock signal CLK. The selector 50 includes inverters 51, 52, 53 and MOS transistors 54, 55, . ~.

61, and inverts the logic level of the outputs of inverters 51 and 52. P-type MOS transistor 5
4, the gate inputs the mode selection signal QTES, and one end of the channel is connected to the power supply. The P-type MOS transistor 55 has a gate connected to the output end of the exclusive NOR circuit 42, one end of the channel connected to the other end of the channel of the P-type MO8t-transistor 54, and the other end of the channel connected to the node. . The gate and one end of the channel of the N-type MOS transistor 56 are respectively connected to the gate and the other end of the channel of the P-type MOS transistor 55, so that the N-type MOS transistor 56 forms a CMOS inverter with the P-type MO8 transistor 55. The N-type MOS transistor 57 has a gate connected to the output terminal of the inverter 51 and one end of the channel connected to the N-type MOS transistor 57.
The other end of the channel of the OS transistor 56 is connected to ground. The P-type MOS transistor 58 has its gate connected to the output end of the inverter 52, and one end of its channel connected to the power supply. P
! ! ! The MOS transistor 59 has a gate connected to the output terminal of the inverter 43, one end of the channel connected to the other end of the channel of the P-type MOS transistor 58, and the other end of the channel connected to the node A.
are connected to each. In N-type MO8)-Randistaro 0, one end of the gate and channel are each P-type MOS.
It is connected to the other end of the gate and channel of the transistor 59, and forms a CMOS inverter with the P-type MOS transistor 59. N-type MO8) - Ranjistaro 1 has its gate connected to the output end of the inverter 53, and one end of the channel connected to the N-type MO
The other ends of the channels of type MO3t-Ranistero0 are each connected to ground. The AND circuit 44 outputs the decoder enable signal DE, which is the output from the selector 50 to the node A, and the read/write signal R/W.
AND is performed and output as a sense amplifier enable signal SE. Inverter 45 inverts the logic level of decoder enable signal DE. The exclusive NOR circuit 46 takes an exclusive NOR between the output of the inverter 45 and the read/write signal R/W, and outputs it as a data-in enable signal DIE.

Next, the operation of the timing generator 4 is shown in FIG. 3(a).
, (b).

(1) When the mode selection signal TES is L (Fig. 3 (
a)).

Since the MOS l-transistor 54.57 is on and the MOS transistor 58.61 is off, the output of the exclusive NOR circuit 42 has its logic level inverted and is connected to the node A.
Since the output terminal of the inverter 43 is separated from the node A, the timing generation circuit 14 of FIG.
is equivalent to Therefore, the decoder enable signal D
E is output as a pulse with a pulse width To.

(2) When the mode selection signal TES is H (Fig. 3 (
b)).

Since the MOS t-transistors 54 and 57 are off and the MOS transistors 58 and 61 are on, the output terminal of the exclusive NOR circuit 42 is disconnected from the node, and the output of the inverter 43 has its logic level inverted and is connected to the node. Output to A. Therefore, since it will be output as the real signal DE, if the pulse width To of the clock signal MCLK is changed to the pulse width T1, T2, T3, the decoder enable signal @DE and the sense up enable signal QS
E.

The active time of the data-in enable signal DIE is also the time T1. It can be set to T2 or T3.

〔Effect of the invention〕

As explained above, the present invention causes a semiconductor memory device to write or read data based on a pulse output with a preset pulse width, and when a malfunction occurs, controls a timing generation circuit using a selection signal. By outputting a clock signal through a buffer circuit instead of the pulse output, the pulse width of the clock signal can be arbitrarily changed, and the time width in which writing or reading can be performed by the semiconductor memory device can be arbitrarily changed, thereby preventing malfunctions. This has the effect of making it easy to determine whether the problem is related to the pulse width of the pulse output or whether there is a problem with the memory cell itself.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the semiconductor memory device of the present invention, FIG. 2 is a circuit diagram showing details of the timing generator 4 of FIG. 1, and FIGS. 3(a) and 3(b) are timing diagrams. Generator 4
4 is a block diagram showing a conventional semiconductor memory device, and FIG. 5 is a circuit diagram showing details of the timing generator 14 shown in FIG. 4. DESCRIPTION OF SYMBOLS 1... Memory, 2... Row address decoder, 3... Data input section, 4... Timing generator, 5... Column address decoder, 6... NOR circuit, 7... Sense Amplifier, 8...Data output section, 41
...Delay element, 42.46...Exclusive NOR circuit, 43.4
5.51, 52.53... Inverter, 44... AND circuit, 50... Selector. (b) Figure 3 -

Claims (1)

[Claims] A timing generator that outputs a pulse output with a preset pulse width in synchronization with an input clock signal,
In a semiconductor memory device that writes data to or reads data from a memory cell while the pulse output is being output using the pulse output as a control signal, the buffer circuit inputs and outputs the clock signal; . The semiconductor memory device, wherein the timing generator includes a selection circuit that selects the pulse output or the output of the buffer circuit according to the logic level of a mode selection signal and uses the selection circuit as the control signal.