JPH01124192A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPH01124192A
JPH01124192A JP62281452A JP28145287A JPH01124192A JP H01124192 A JPH01124192 A JP H01124192A JP 62281452 A JP62281452 A JP 62281452A JP 28145287 A JP28145287 A JP 28145287A JP H01124192 A JPH01124192 A JP H01124192A
Authority
JP
Japan
Prior art keywords
output
pulse
buffer circuit
pulse width
pulse output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62281452A
Inventor
Yasumasa Yamada
Original Assignee
Nec Ic Microcomput Syst Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Ic Microcomput Syst Ltd filed Critical Nec Ic Microcomput Syst Ltd
Priority to JP62281452A priority Critical patent/JPH01124192A/en
Publication of JPH01124192A publication Critical patent/JPH01124192A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To easily discriminate whether a memory cell itself has a problem or malfunction takes place depending on the pulse width of a pulse output by selecting the pulse output or the output of a buffer circuit according to a logic level of a mode selection signal so as to use the result as a control signal.
CONSTITUTION: A timing generator 4 includes a buffer circuit receiving a clock signal CLK and giving an output and a selection circuit selecting either a pulse output or the output of the buffer circuit depending on the logic level of a mode selection signal TES and using the result as a control signal. Thus, based on the pulse output of a predetermined pulse width, a semiconductor memory device writes or reads the data and when a malfunction takes place, the selection signal TES controls the timing generation circuit 4 to output a clock signal in place of the pulse output via the buffer circuit and whether malfunction takes place in relation to the pulse width of the pulse output or the memory cell itself has a problem is easily discriminated by varying the pulse width of the clock signal optionally.
COPYRIGHT: (C)1989,JPO&Japio
JP62281452A 1987-11-06 1987-11-06 Semiconductor memory device Pending JPH01124192A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62281452A JPH01124192A (en) 1987-11-06 1987-11-06 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62281452A JPH01124192A (en) 1987-11-06 1987-11-06 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPH01124192A true JPH01124192A (en) 1989-05-17

Family

ID=17639376

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62281452A Pending JPH01124192A (en) 1987-11-06 1987-11-06 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPH01124192A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6287469B1 (en) * 1997-10-17 2001-09-11 Ashco-A-Corporation Home wastewater treatment plant

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6287469B1 (en) * 1997-10-17 2001-09-11 Ashco-A-Corporation Home wastewater treatment plant

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