JPH01122155A - Semiconductor storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the lowering of a read signal level, and to increase working speed by forming a read (a second MOS type) transistor operated by a write signal and shaping a diode connected in series with a drain region in the transistor. CONSTITUTION:A gate electrode for a write transistor 41 having n-type MOS structure is connected to a write word line 40 for information and a source electrode for the transistor 41 to a bit line 42 in a circuit, and a drain electrode for the transistor 41 is connected to a gate electrode as a capacitance section in a read transistor 43 having P-type MOS structure. The drain electrode is connected to the bit line 42 through a protective diode 44 for preventing the operation of the transistor 43 at the time of write in series, and a source electrode for the transistor 43 is connected to a read word line 45 for information. An N<+> type diffusion layer 25 is shaped as a gate electrode, an N<-> type polysilicon layer 30 as a channel section, and P<+> type polysilicon layers 32 as a source electrode and a drain electrode in the read transistor 43 at that time. Accordingly, the lowering of a read signal level is obviated, and working speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS type dynamic semiconductor memory device and a manufacturing method thereof.

[Conventional technology]

A conventional MOS type dynamic semiconductor memory device of this type will be explained with reference to FIGS. 11 to 15.

Furthermore, Fig. 11 is a circuit diagram of the memory cell, Fig. 12 is a cross-sectional view thereof, Fig. 13 is an explanatory diagram of the same operation, Fig. 14 is a read signal level-capacitance characteristic diagram, and Fig. 15 is a read signal level. - It is a time characteristic diagram.

That is, as shown in FIG. 11, in this memory cell, the P- electrode of transistor 2 is connected to word -I, and the source electrode of transistor 2 is connected to bit line 3. The capacitor 4 is connected to the drain electrode of the transistor 2, and its electrode (cell rate) 5 is set to an arbitrary voltage (cell rate potential).

Next, as shown in FIG. 12, this memory cell will be described in terms of its cross-sectional structure. The transistor 2 includes an N-type diffusion layer 7 formed on the surface of a P-type silicon substrate 6, an r-to insulating film 8, and an r-
) It is a MOS type field effect transistor consisting of an electrode 9, r-) The electrode 9 also serves as a word line l. Further, the gear/quarter shifter 4 is composed of an N-type diffusion layer 7, a dielectric material 1o, and a cell rate electrode 5, and the bit line 3 is composed of a metal wiring layer 12.
The transistor 2 is connected to the transistor 2 through a contact hole 13. Note that 14 and 15 are interlayer insulating films, and 16
1 is an insulating film for element isolation, and 17 is a P+ diffusion layer. Usually, the P-) electrode 9 is made of N-type polysilicon and a silicon metal compound, the cell rate electrode 5 is made of N-type polysilicon, the metal wiring layer 12 is made of M alloy, and the r-) insulating film 8 is thermally oxidized. The film or CVD oxide film and the dielectric 1o include:
A thermal oxide film, a CVD nitride film, or the like is used.

Second, as shown in FIG. 13, when this memory cell is inactive, the word line 1 is at the "0" level and the bit line 3 is at the "10" level.
First, after writing to the bit line 3 and shifting the voltage to the signal level, the word line 1 is set to the "1" level for a predetermined period of time to operate the transistor 2 and record the signal in the capacitor 4. . When reading, bit line 3 is
- When the word line 1 is set to the 11'' level after the bit line 3 is disconnected from the outside, the potential of the bit 1fiA3 becomes 01'' or high due to the discharge from the capacitor 4.
When the signal approaches the "0" level and exceeds the sensitivity of the sense amplifier, reading is performed.

[Problem that the invention seeks to solve]

However, in the conventional semiconductor memory device described above,
As shown in FIG. 14, since the charge stored in the capacitor 4 itself becomes a signal, the area of the memory cell 4 is reduced due to the improvement in element integration. As the amount of charge decreases, the signal level during reading becomes smaller, and as shown in FIG. 15, even if a 1" level is written to the capacitor 4 due to various leakage currents, the signal level becomes smaller as time passes. Become,
There was a problem in that the reliability of the device decreased. Furthermore, since the signals written during the read operation are destroyed, the signals must be rewritten after the read operation, resulting in a problem that the operation time becomes longer.

An object of the present invention is to provide a semiconductor memory device and a method for manufacturing the same that can improve reliability and operating speed.

[Means for solving problems]

In order to achieve the above-mentioned object, the present invention includes a step of forming a polycrystalline or amorphous semiconductor layer on a first conductivity type semiconductor substrate, and a second conductivity type semiconductor layer on the surface of the first conductivity type semiconductor substrate excluding the semiconductor layer. a step of forming a type diffusion layer, and after forming a glabellar insulating film on the second conductivity type diffusion layer and the semiconductor layer, forming a first conductivity type diffusion layer on a region under the semiconductor layer that is not a diffusion layer; This method includes the step of diffusing the other portion into the second conductivity type diffusion layer.

[Effect]

In the present invention, a readout (second MOS type) transistor operated by a written signal is stacked directly above the charge storage region, and a diode connected in series to the drain region of the readout transistor is formed. does not work when writing.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on FIGS. 1 to 5.

In addition, FIG. 1 is a sectional view of the memory cell, FIG. 2 is a turn diagram thereof, FIG. 3 is a circuit diagram thereof, FIG. 4 is an explanatory diagram of the same operation, and FIG. 5 is a diagram of the manufacturing process.

That is, as shown in FIGS. 1 and 2, this memory cell has a thermal oxide film 21 on a non-active region of a P-type silicon substrate 20 (hereinafter referred to as "substrate"), and a P+ type diffusion layer below this thermal oxide film 21. A layer 22 is formed, and an r-) insulating film 23 is formed on the active region of the substrate 20 by thermal oxidation. Furthermore,
A polysilicon layer 24 is formed on the r-type insulating film 23 and the thermal oxide film 21, and an N''ffl diffusion layer 25 is formed on the surface of the substrate 20 other than the p-type insulating film 23 and the thermal oxide film 21. There is a P+ type diffusion layer 22 in the N+ type diffused layer 25 portion between the polysilicon layers 24 and below the thermal oxide film 21.
is formed. Then, on the polysilicon layer 24,
At the same time as the glabellar insulating film 27 is formed, a P−) insulating film 28 is formed on the N+ffi+ diffused layer 25, and the thermal oxide film 2
A contact hole 29 is opened above the polysilicon layer 24 . Also, on the dirt insulating film 28, N
In addition to forming the base polysilicon layer 30, a P+ type polysilicon 2 layer 32 is formed on the interlayer insulating film 27 including the contact hole 29. Then, an intermediate insulating film 34 is formed covering the entire surface of the N- type polysilicon layer 30 and the P+ type polysilicon layer 32, and a contact connecting the N'''' type polysilicon layer 30 and the N medium-sized diffusion layer 25. A hole 35 is opened. Bit line 3 connected to N medium-sized diffusion layer 25 through this contact hole 35
6 is formed on the intermediate insulating film 34.

Note that the channel portion 30a of the N'''' type polysilicon layer 30 is wired in the same direction as the word i (polysilicon layer 24), and is supplied with a back bias potential. It resonates with the cell rate potential.

Next, as shown in FIG. 3, in the memory cell circuit, the r-) electrode of the n-type MOS write transistor 41 is connected to the information write word line 40, and the bit lIi
! The source electrode of the write transistor 41 is connected to 42 . The drain electrode of the write transistor 41 is connected to the read transistor 4 having a pmMOS structure.
The gate electrode (records the written signal) serving as a cap part of the capacitor 3 is connected to K, and the drain electrode of this read transistor 43 is connected to the protective diode 4 to prevent the read transistor 43 from operating when writing information.
4 in series to the bit line 42. A source electrode of the read transistor 43 is connected to an information read word line 45. In this case, in the read transistor 43, the N medium diffusion layer 25
is formed as a gate electrode, an N-type polysilicon layer 30t-channel part and a P+ type polysilicon 7 layer 32 as a source electrode and a drain electrode, and a P+ type polysilicon 2 layer 32
A source electrode is connected to the read word line 45 through a contact hole 29. Furthermore, the protection diode 44 is a junction diode formed by the drain electrode formed by the P+ type polysilicon 7 layer 32 and the N'''' polysilicon layer 30 connected to the bit line 42 via the contact hole 35. Note that the polarities of the write/read transistors 41 and 43 may be the same as long as the protection diode 44 can be formed.

Next, the operation of such a memory cell will be described based on FIG. First, at the time of writing, after the voltage is completely shifted to the level of the signal 42t-write, the write transistor 41 is operated by setting the write word line 40 to the "1" level for a predetermined period of time. In this case, the read word line 45 is at the 10'' level.Furthermore, during reading, the write word line 40 is at the 10'' level.
By fixing the read word line 45 to the "1" level, the transistor 41.4 is connected to the bit line 42.
Due to the difference in polarity of 3, a signal having a phase opposite to that of the write signal is generated. In this case, when "1 level" is written to the read word line 45 by the protection diode 44 connected in series with the read transistor 43, the N+ type scattering layer 2
5 Electrification from bit +R42 until the potential stabilizes (
(dotted line in the figure) is prevented. Furthermore, since fluctuations in the potential of the channel portion (N-type polysilicon layer 30) of the read transistor 43 can be prevented, the write state is stabilized, and 1
Erroneous signals (dotted chain line in the figure) when reading the 1'' level can also be prevented.

Next, a method for manufacturing a non-memory cell will be described based on FIG.

First, as shown in FIG. 5(a), the impurity concentration is 1×10
1's"=2 X 10"3-" (D board 20
(D) A thermal oxide film 21 with a thickness of 3000 to 6000λ is formed on the non-active region, and a substrate 2 is formed under this thermal oxide film 21.
An element isolation region is formed by a P+ type diffusion layer 22 having an impurity concentration of about the same level to three times that of the P+ type diffusion layer 22.

Next, as shown in FIG. 2(b), a 100 to 500 mm thick r-type insulating film 23 is grown on the active region of the substrate 2o by thermal oxidation, and then 2000 to 400 mm thick is grown by LPCVD.
00λ thick polysilicon is grown. After ion implantation of B0 or BF,10, the impurity concentration is lXl0''
A polysilicon layer 24 is formed on the dirt insulating film 23 and the thermal oxide film 21 by patterning the polysilicon of ~7×10203-3. After that, A8+
Or the impurity concentration is 2X by P+ ion implantation.
1015 to I x 10"cm-" (D After forming the N+ type diffused layer 25, a P+ type diffusion layer 26 is formed by B+ ion implantation under the N+ pear-shaped diffusion layer 250 between the polysilicon layers 24.

Subsequently, as shown in FIG. 2(e), a glabellar insulating film 27 with a thickness of 500 to 1000λ is formed on the polysilicon layer 24 by thermal oxidation, and on the N0 type diffusion layer 25,
The r-) insulating film 28 of the read transistor 43 is formed to have a thickness of 100 to 5 ooA. Thereafter, a contact hole 291jc to a bit line 36, which will be described later, is opened on the polysilicon layer 24 on the thermal oxide film 21.

Then, as shown in the same figure (d), the LPCVD method and A
lXl0'' ~ 2x with s0 or P+ ion implantation
N-type polysilicon layer 30 with 1011cIR″″3 concentration
After forming to a thickness of 2000 to 5000^, the region to be left as N- type is protected with a resist layer 31, and a P+ type polysilicon layer a with a concentration of IX10" to 7X1020 is formed by ion implantation of B10 or BF7. 2 tz IJ Formed on a region under the silicon layer 24 that is not a diffusion layer.

After that, as shown in the same figure (e), the polysilicon layer 3
At the same time as patterning 0.32, a contact region 33t- of the N+ type scattering layer 25 is formed.

After that, as shown in FIG. 3(f), the intermediate insulating film 34 is
A contact hole 35 to the N-type polysilicon layer 30 and the N-medium diffusion layer 25 is opened by the PCVD method by 4,000 to 7,000 layers. Thereafter, P+ ions are implanted to increase the surface concentration of the contact hole 35, and an M alloy is deposited by the spouting method, which is then turned into a bit line 36.

Thereafter, the surface of this bit line 36 is covered with a protective film to complete the process.

Next, another embodiment will be described based on FIGS. 6 to 8.

However, the explanation of the same components as those of the first embodiment will be omitted.

6 is a sectional view of the memory cell, FIG. 7 is a pattern diagram of the same, and FIG. 8 is a process diagram of the same manufacturing method.

That is, as shown in FIGS. 6 and 7, in this memory cell, the dirt electrode of the read transistor 43 of the ON+ type diffusion layer 25 in the substrate 20 in the first embodiment is replaced with an N-shaped polysilicon layer 37, and the write transistor is A read transistor 43 is formed on the N+
The type polysilicon layer 37 and the N++ diffusion layer 25 are connected through a contact hole 38. By moving the read transistor 43 above the write transistor 41 in this manner, the memory cell area is further reduced.

Next, a method for manufacturing such a memory cell will be described based on FIG. The difference from the first embodiment is that after the write transistor 41 is formed (FIG. 1b), the interlayer P! After growing the edge film 27 to a thickness of 2000 to 5000λ, a contact hole 38 is formed in the interlayer insulating film 27 between the polysilicon layers 24 on the N0-type diffusion layer 25 (FIG.
), this contact hole 38t- is filled with polysilicon with a thickness of 2000 to 4000^ by LPCVD method, and the impurity concentration I x 102° to 7 x IQ"cm- is filled by poczs doping or P+ ion implantation.
A 3ON+ type polysilicon layer 37 is formed.

After patterning this, there is a step of growing the r-to-insulating film 28 of the read transistor 43 to a thickness of 200 to 500 mm by depositing silicon oxide using thermal oxidation or sputtering (see d in the figure). .

〔Effect of the invention〕

As explained above, according to the present invention, since the write signal operates the readout (second MOS type) transistor, even if the amount of accumulated charge decreases, the readout signal level - capacitance shown in Fig. 9 As shown in the characteristic diagram, a drop in the read signal level can be prevented, and as shown in the read signal level-time characteristic diagram of FIG. 10, time dependence of the read signal level can be prevented. Furthermore, since there is no need to rewrite after reading, the element size can be reduced.
The above-mentioned problems can be solved by unique effects such as improved reliability and increased operating speed.

[Brief explanation of the drawing]

1 to 5 show an embodiment according to the present invention, in which FIG. 1 is a cross-sectional view of a memory cell, FIG. 2 is a diagram of the same pattern, FIG. 3 is a circuit diagram of the same, and FIG. 4 is a diagram of the same pattern. 5 is a process diagram of the same manufacturing method, and FIGS. 6 to 8 show other embodiments of the present invention. FIG. 6 is a sectional view of the memory cell, and FIG.
The figure is a diagram of the same pattern, FIG. 8 is a process diagram of the same manufacturing method, and FIG. 9 is a diagram of the read signal level - capacitance it! ! ! Figure 10 is a readout signal level-time characteristic diagram.
11 to 15 show a conventional example, in which FIG. 11 is a circuit diagram of a memory cell, FIG. 12 is a sectional view of the same, FIG. 13 is an explanatory diagram of the same operation, and FIG. 14 is a read signal level - FIG. 15 is a capacitance characteristic diagram, and FIG. 15 is a read signal level-time characteristic diagram. 20...P-type silicon substrate, 21...thermal oxide film, 2
2... P+ type diffusion layer, 23... P- type insulating film, 24
...Polysilicon layer, 25...N medium-sized diffusion layer, 26
... P0 is a diffusion layer, 27 ... interlayer insulating film, 28 ...
・r-t insulating film, 29... contact hole, 30・
...N'''' polysilicon layer, 31...Resost, 3
2... P+ type polysilicon layer, 33... Contact region, 34... Intermediate insulating film, 35... Contact hole, 36... Bit line. 20: p-type silicon substrate 21, thermal oxide film 22: P+ type diffusion layer 23; gate insulating film 26: P+ type diffusion layer 27: interlayer insulating film 28: gate insulating film 29: contact hole 30: N- type polysilicon layer 35: Contact hole 36 Two-bit line Cross-sectional view of the memory cell of the invention FIG. 1 Pattern diagram of the memory cell of the invention FIG. 2 4o: Write word line 41: Write transistor 42: Bit line 43; Read transistor 44: Protection diode 45 : Read word line Circuit diagram of the memory cell of the present invention FIG. 3 20: P type silicon substrate 21: Thermal oxide film 22: P+ type diffusion layer 23: Gate insulating film 24: Polysilicon layer 25: N+ type scattering layer 6 :P+ type diffusion layer 29: Contact hole 34: Intermediate insulating film 35: Contact 1-hole 36: Bit line Fig. 6 Fig. 7 Process diagram of separate manufacturing method of the present invention Fig. 8 20: P type silicon substrate 21 : Thermal oxide film 22 : P" type diffusion layer 29 : Contact hole Figure 8 Capacitance read signal level - Capacitance characteristic diagram Figure 9 O Time Read signal level - Time characteristic diagram Figure 10 1 : Word line 2 : Transistor 3 : Bit line 4 : Capacitor 5 : Cell plate electrode Circuit diagram of conventional memory cell FIG. Figure 12 NEET I-Ryo Oki Nagisa Seiji Female D Ri

Claims (2)

[Claims] (1) A first MOS type transistor formed on a semiconductor substrate, a second MOS type transistor having a gate electrode connected to the drain region of the first MOS type transistor, and the second MOS type transistor. A diode connected in series to the drain region of the transistor, a bit line connected to the source region of the first MOS transistor and the diode, and a first bit line connected to the gate electrode of the first MOS transistor. A semiconductor memory device comprising: a word line; and a second word line connected to a source region of the second MOS transistor. (2) forming a polycrystalline or amorphous semiconductor layer on a first conductivity type semiconductor substrate; and forming a second conductivity type diffusion layer on the surface of the first conductivity type semiconductor substrate excluding the semiconductor layer. , after forming an interlayer insulating film on the second conductivity type diffusion layer and the semiconductor layer, a region under the semiconductor layer that is not a diffusion layer is made into a first conductivity type diffusion layer, and the other part is made into a second conductivity type diffusion layer. 1. A method of manufacturing a semiconductor memory device, comprising the step of diffusing into a diffusion layer.