JPH01120201U - - Google Patents
Info
- Publication number
- JPH01120201U JPH01120201U JP1351588U JP1351588U JPH01120201U JP H01120201 U JPH01120201 U JP H01120201U JP 1351588 U JP1351588 U JP 1351588U JP 1351588 U JP1351588 U JP 1351588U JP H01120201 U JPH01120201 U JP H01120201U
- Authority
- JP
- Japan
- Prior art keywords
- input system
- status
- interval time
- abnormality
- contents
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005856 abnormality Effects 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 claims 1
- 238000005259 measurement Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案に係るシーケンス制御装置をプ
レス装置に接続した際の概略構成図、第２図は、
本考案に係るシーケンス制御装置において基準デ
ータを取込む際のフローチヤート、第３図は、本
考案に係るシーケンス制御装置を自動運転した際
のフローチヤート、第４図は、従来例に係るシー
ケンス制御装置をプレス装置に接続した際の概略
構成図、第５図は、従来例に係るシーケンス制御
装置の動作フローチヤート、第６図は、プレス装
置のシーケンス動作を表すタイムチヤート、第７
図は、本考案と従来例とのシーケンス制御装置に
共通して格納されているラダーシーケンス回路で
ある。
１０…ＰＣ（シーケンス制御装置）、１１…Ｃ
ＰＵ（計測手段、補正手段）、１３…入力部、１
４…出力部、１５…プログラミング装置、２０…
第１メモリ部、２１…第２メモリ部（記憶手段）
、ＬＳ１〜ＬＳ６…リミツトスイツチ、ＳＶ１〜
ＳＶ３…ソレノイドバルブ。
Figure 1 is a schematic configuration diagram when the sequence control device according to the present invention is connected to a press machine, and Figure 2 is a
A flowchart for importing reference data in the sequence control device according to the present invention, Fig. 3 is a flowchart for automatically operating the sequence control device according to the present invention, and Fig. 4 is a sequence control according to the conventional example. A schematic configuration diagram when the device is connected to a press device, FIG. 5 is an operation flow chart of a conventional sequence control device, FIG. 6 is a time chart showing the sequence operation of the press device, and FIG.
The figure shows a ladder sequence circuit stored in common in the sequence control devices of the present invention and the conventional example. 10...PC (sequence control device), 11...C
PU (measuring means, correction means), 13...input section, 1
4... Output unit, 15... Programming device, 20...
First memory section, 21...second memory section (storage means)
, LS1~LS6...Limit switch, SV1~
SV3...Solenoid valve.
Claims (1)
どの入力系に関するデータに基づいてサイクリツ
クにシーケンス演算を実行し、該演算結果をソレ
ノイドバルブなどの出力系に出力することにより
、製造ライン等のシーケンス動作を制御するシー
ケンス制御装置において、 入力系のオンオフ状況を入力して該オンオフ間
隔時間を計測する計測手段と、 ラインが正常稼働時における、前記オンオフ間
隔時間に対応するオンオフ状況を基準テーブルと
して記憶する記憶手段と、 当該記憶手段に記憶されている前記基準テーブ
ル内容、並びに前記計測手段よりの現在の入力系
のオンオフ状況及びオンオフ間隔時間を参照する
ことにより、入力系における異常の有無を判断す
る一方、当該判断の結果、入力系に異常が有ると
判断された場合には、前記基準テーブル内容にし
たがい入力系のオンオフ状況を補正する補正手段
とを有することを特徴とするシーケンス制御装置
。[Scope of Claim for Utility Model Registration] By cyclically performing sequence calculations based on data related to input systems such as internal coils, relay contacts, and limit switches, and outputting the calculation results to output systems such as solenoid valves, manufacturing lines can be improved. In a sequence control device that controls sequence operations such as, a measuring means for inputting the on/off status of an input system and measuring the on/off interval time, and a reference to the on/off status corresponding to the on/off interval time when the line is in normal operation. The presence or absence of an abnormality in the input system is determined by referring to a storage means for storing it as a table, the contents of the reference table stored in the storage means, and the current on/off status and on/off interval time of the input system from the measurement means. and a correction means for correcting the on/off status of the input system according to the contents of the reference table when it is determined that there is an abnormality in the input system as a result of the judgment. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988013515U JPH082723Y2 (en) | 1988-02-05 | 1988-02-05 | Sequence controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988013515U JPH082723Y2 (en) | 1988-02-05 | 1988-02-05 | Sequence controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01120201U true JPH01120201U (en) | 1989-08-15 |
| JPH082723Y2 JPH082723Y2 (en) | 1996-01-29 |
Family
ID=31223884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988013515U Expired - Lifetime JPH082723Y2 (en) | 1988-02-05 | 1988-02-05 | Sequence controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH082723Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57189213A (en) * | 1981-05-18 | 1982-11-20 | Hitachi Ltd | Monitoring method of process state |
| JPS5835603A (en) * | 1981-08-27 | 1983-03-02 | Matsushita Electric Ind Co Ltd | Input circuit |
-
1988
- 1988-02-05 JP JP1988013515U patent/JPH082723Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57189213A (en) * | 1981-05-18 | 1982-11-20 | Hitachi Ltd | Monitoring method of process state |
| JPS5835603A (en) * | 1981-08-27 | 1983-03-02 | Matsushita Electric Ind Co Ltd | Input circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH082723Y2 (en) | 1996-01-29 |
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