JPH01120073A - Mes transistor - Google Patents
Mes transistorInfo
- Publication number
- JPH01120073A JPH01120073A JP27891587A JP27891587A JPH01120073A JP H01120073 A JPH01120073 A JP H01120073A JP 27891587 A JP27891587 A JP 27891587A JP 27891587 A JP27891587 A JP 27891587A JP H01120073 A JPH01120073 A JP H01120073A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- shaped gate
- silicon oxide
- oxide film
- active layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000001681 protective effect Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明のMES)−ランジスタに関し、特にGaAs電
界効果形のMES)ランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to an MES transistor, in particular to a GaAs field effect MES transistor.
トランジスタの普及に伴い、その信頼性向上に対する要
望も強くなってきた。As transistors become more widespread, demands for improved reliability have also become stronger.
従来、GaAsを基板としなMES形電界効果トランジ
スタの断面が丁字形構造のゲート電極(以下丁字形ゲー
ト電極という)の表面保護膜には、シリコン酸化膜また
はシリコン窒化膜等のいずれか一種類が用いられていた
。Conventionally, a surface protective film of a gate electrode having a T-shaped cross section (hereinafter referred to as a T-shaped gate electrode) of an MES field effect transistor using GaAs as a substrate has been made of either a silicon oxide film or a silicon nitride film. It was used.
上述した従来のMESトランジスタは、丁字形ゲートの
表面保護膜として一種類のみを用いる場合に、それぞれ
長所及び雉所があった。The above-mentioned conventional MES transistors each have their own advantages and disadvantages when only one type is used as a surface protective film for the T-shaped gate.
すなわち、シリコン窒化膜のみを保護膜に使用した場合
は、GaAsとシリコン窒化膜界面の界面準位がGaA
sとシリコン酸化膜界面に比べて安定であるという利点
がある。In other words, when only a silicon nitride film is used as a protective film, the interface level at the interface between GaAs and silicon nitride film is GaAs.
It has the advantage of being more stable than the interface between s and silicon oxide film.
しかしながら、シリコン窒化膜の誘電率はシリコン酸化
膜よりも大きいため、丁字形ゲートの庇部直下の側壁膜
に起因するゲート・ドレイン電極間容FikCgdは、
シリコン酸化膜の場合より太きくなり、高周波利得が低
下するという問題があった。However, since the dielectric constant of the silicon nitride film is larger than that of the silicon oxide film, the gate-drain electrode capacitance FikCgd due to the sidewall film directly under the eaves of the T-shaped gate is
The problem is that it is thicker than in the case of a silicon oxide film, resulting in a reduction in high frequency gain.
本発明の目的は、表面が安定で高周波利得の大きいME
Sトランジスタを提供することにある。The purpose of the present invention is to provide an ME with a stable surface and a large high frequency gain.
An object of the present invention is to provide an S transistor.
本発明のMESトランジスタは、GaAs基板の一主面
の活性層の表面に設けられた丁字形のゲート電極と該丁
字形のゲート電極を挟んで前記活性層の表面に設けられ
たドレイン及びソース電極と、前記丁字形ゲート電極の
庇部直下の両側壁部を覆うシリコン酸化膜と、該シリコ
ン酸化膜を含めて前記丁字形ゲート電極及び前記ドレイ
ン及びソース電極間の前記活性層表面を覆うシリコン窒
化膜とを含んで構成されている。The MES transistor of the present invention includes a T-shaped gate electrode provided on the surface of an active layer on one main surface of a GaAs substrate, and drain and source electrodes provided on the surface of the active layer with the T-shaped gate electrode sandwiched therebetween. a silicon oxide film covering both side walls directly under the eaves of the T-shaped gate electrode; and a silicon nitride film covering the active layer surface between the T-shaped gate electrode and the drain and source electrodes, including the silicon oxide film. It is composed of a membrane.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
MESトランジスタは、絶縁性GaAs基板1の上層に
形成された活性層2の表面に形成された庇部5 uを含
む丁字形ゲート電f!5と、庇部5 。The MES transistor has a T-shaped gate electrode f! that includes an eaves portion 5u formed on the surface of an active layer 2 formed on an upper layer of an insulating GaAs substrate 1. 5 and eaves 5.
直下の側壁を覆うシリコン酸化膜6と、シリコン酸化M
6も含めた丁字形ゲート電極5及びドレイン及びソース
電極3及び4間の活性M2の表面を覆いシリコン窒化膜
を有している。A silicon oxide film 6 covering the side wall directly below and a silicon oxide film M
A silicon nitride film covers the surface of the active M2 between the T-shaped gate electrode 5 including the gate electrode 6 and the drain and source electrodes 3 and 4.
シリコン窒化膜7により表面は安定で、かつシリコン酸
化1i6によりゲート・ドレイン電極間の容量Cgdは
小さい。The surface is stable due to the silicon nitride film 7, and the capacitance Cgd between the gate and drain electrodes is small due to the silicon oxide 1i6.
以上説明したように本発明は、丁字形ゲートの庇部の直
下の側壁保護膜をシリコン酸化膜にすることにより膜圧
を厚くしゲート・ドレイン電極間界icgdを低減させ
、ゲート電極表面をシリコン窒化膜で安定にすることに
より、安定で高周波利得の大きいMES)−ランジスタ
が得られるという効果がある。As explained above, the present invention makes the sidewall protection film directly under the eaves of the T-shaped gate a silicon oxide film to increase the film thickness and reduce the gate-drain electrode interface ICGD, and the gate electrode surface is made of silicon oxide. By stabilizing it with a nitride film, there is an effect that a stable MES transistor with a large high frequency gain can be obtained.
第1図は本発明の一実施例の断面図である。
1・・・絶縁性GaAs基板、2・・・活性層、3・・
・ドレイン電極、4・・・ゲート電極、5・・・丁字形
ゲート電極、5H・・・庇部、6・・・シリコン酸化膜
、7・・・シリコン窒化膜。FIG. 1 is a sectional view of an embodiment of the present invention. 1... Insulating GaAs substrate, 2... Active layer, 3...
- Drain electrode, 4... Gate electrode, 5... T-shaped gate electrode, 5H... Eaves, 6... Silicon oxide film, 7... Silicon nitride film.
Claims (1)
字形のゲート電極と該T字形のゲート電極を挟んで前記
活性層の表面に設けられたドレイン及びソース電極と、
前記T字形ゲート電極の庇部直下の両側壁部を覆うシリ
コン酸化膜と、該シリコン酸化膜を含めて前記T字形ゲ
ート電極及び前記ドレイン及びソース電極間の前記活性
層表面を覆うシリコン窒化膜とを含むことを特徴とする
MESトランジスタ。T provided on the surface of the active layer on one main surface of the GaAs substrate
a drain and source electrode provided on the surface of the active layer with the T-shaped gate electrode sandwiched therebetween;
a silicon oxide film covering both side wall portions directly under the eaves of the T-shaped gate electrode; and a silicon nitride film covering the active layer surface between the T-shaped gate electrode and the drain and source electrodes, including the silicon oxide film. An MES transistor characterized by comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27891587A JPH01120073A (en) | 1987-11-02 | 1987-11-02 | Mes transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27891587A JPH01120073A (en) | 1987-11-02 | 1987-11-02 | Mes transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01120073A true JPH01120073A (en) | 1989-05-12 |
Family
ID=17603861
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27891587A Pending JPH01120073A (en) | 1987-11-02 | 1987-11-02 | Mes transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01120073A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102420115A (en) * | 2011-03-30 | 2012-04-18 | 上海华力微电子有限公司 | Method for reducing overlap capacitance in semiconductor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56100480A (en) * | 1980-01-11 | 1981-08-12 | Nec Corp | Electric field effect transistor |
JPS61251080A (en) * | 1985-04-27 | 1986-11-08 | Fujitsu Ltd | Manufacture of field effect transistor |
JPS6257256A (en) * | 1985-09-06 | 1987-03-12 | Fujitsu Ltd | Manufacture of field effect type semiconductor device |
-
1987
- 1987-11-02 JP JP27891587A patent/JPH01120073A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56100480A (en) * | 1980-01-11 | 1981-08-12 | Nec Corp | Electric field effect transistor |
JPS61251080A (en) * | 1985-04-27 | 1986-11-08 | Fujitsu Ltd | Manufacture of field effect transistor |
JPS6257256A (en) * | 1985-09-06 | 1987-03-12 | Fujitsu Ltd | Manufacture of field effect type semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102420115A (en) * | 2011-03-30 | 2012-04-18 | 上海华力微电子有限公司 | Method for reducing overlap capacitance in semiconductor device |
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