JPH01119878A - Processing control device for picture memory data - Google Patents

Abstract

PURPOSE:To attain high-speed picture memory access by constituting the picture memory with plural block memories, providing plural straight line interpolation computing elements, providing pixel registers corresponding to the respective block memories, and selectively controlling them. CONSTITUTION:When address data are successively generated from straight line interpolation computing elements (DDA) 41-4k at the time of writing picture element data, timing control circuits 31-3m generate control signals based on an x-y-coordinate value. Further, only a pixel register 21-2m corresponding to the generated address data is selected. Picture element unit color information data generated by DDAs 41a-4ka to function in synchronization with the DDA 41-4k are supplied to the module corresponding to the selected pixel register. In addition, when the supply reaches a limit, all color information data are collectively written into a frame memory 1. During the above period, the color information continuously outputted from the DDAs 41a-4ka can be supplied to the other pixel register.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to an image memory data processing control device, and more specifically, to high-speed image processing using a linear interpolation calculator (hereinafter referred to as 1) (abbreviated as D△). The object of the present invention is to provide a new image memory data processing control device that can perform memory access and achieve a high-speed bit block transfer function (hereinafter abbreviated as bitblt). It is said that

<Prior Art> Conventionally, raster scan type graphic display devices have not only been basically required to have faster image display speed and lower price of the device 6 as a whole, but also to have multiple functions. It's starting to look like this. In particular, there is a strong demand for a function that allows multi-window display.

Conventionally, the methods for realizing multi-window display are as follows: ■ In addition to providing multiple frame buffers, a control circuit is also provided to control these frame buffers, and a state in which the interaction is taken into account is used. This is a so-called hardware method in which the screen to be displayed is divided in advance and stored in a frame buffer, and multi-window display is performed by sequentially switching the address of the display data according to the display timing. , and ■ The image data for multi-window display held in the memory is read out in bytes, performs raster operations, and then writes to the frame buffer, thereby transferring the window area of the memory to the frame buffer. Multi-window display can be performed by setting the transfer order according to multi-window display, so-called b.
The itblt method is provided.

In addition, in the above hardware method, when displaying, it is only necessary to combine the display screens of multi-windows, and there is no need for memory transfer processing, so the speed is high regardless of the size of the displayed window. Multi-window display can be achieved.

On the other hand, in the old TBLT method, a desired number of windows can be displayed at any location on the screen, and the degree of freedom in multi-window display can be significantly increased. In this case, it is possible to adopt a configuration in which the memory and frame buffer are shared.

<Problems to be Solved by the Invention> In the above hardware system, the number of windows that can be displayed in multiple windows is determined based on the number of divisions of the display screen, so the maximum number of windows is specified at the time of system design. There is a problem that the number of windows cannot be increased freely, and even if only a small number of multi-window displays are performed, the circuit configuration for displaying a predetermined number of divided windows is difficult. However, there is a problem in that the efficiency of using the hardware as a whole decreases. In addition, as the resolution of the display screen increases, it becomes necessary to use devices that can operate at high speeds for the circuits used to display both sides of the composite image, resulting in higher costs due to idle time. .

The above bitblt7) formula has a problem in that the speed when displaying a composite screen cannot be increased much. That is, in the bitblt method,
It is necessary to transfer the pixel data corresponding to the window display area while considering the priority order, so if the window area becomes wider, the transfer processing load to the memory will increase and the window composition will be completed. The time it takes to do so becomes longer.

To explain in more detail, in the P1 to MAP display devices, when performing bttblt processing,
A mode is adopted in which a plurality of consecutive pixel data are accessed in the direction of the scan line in one memory access, and for example, as shown in 6th row in FIG. (See FIG. 10C), use a barrel shifter (not shown) to perform shift 1~processing to match the processing start pixel position with the processing start pixel position on the destination area side (see FIG. 10C). After performing raster calculation in the state, mask processing is performed in correspondence with the processing start pixel position and written in the destination area, thereby completing the bitblt processing.

Frame buffer access in this case = 10
- Generally, three types of access modes are provided: a clear mode, a plain mode, and a fill-in mode. Specifically, in the Bicrel mode described above, data for one pixel corresponding to each plane of the frame buffer can be accessed at the same time, and in the plane mode described above, data for one pixel of each plane of the frame buffer can be accessed simultaneously. It is possible to access the data of pixel valves at the same time, and in the fill-in mode described above, for each plane of the frame buffer, data set in advance is It allows access based on color data.

In addition, in a 3D graphic display, when displaying a figure that has been subjected to shading processing, 3D hidden surface processing, etc., it is generally the case that each pixel is given a color or a depth ratio (hereinafter referred to as , Z value) are different, so basically the pixel mode is selected, and only one pixel can be drawn per memory cycle, so for example, if the frame buffer memory cycle is 4 Q
Q If it is n5ec, the pixel drawing speed is maximum 2.
This is 5M pixels/sec, and if overhead is taken into account, it is converted to an arbitrary short vector of 40 pixels per line, which is approximately 5M pixels/sec.
0,000 polygons/second, which is approximately 5,000 polygons/second when converted to a square with an arbitrary inclination angle of 20 pixels on each side, making the drawing speed insufficient.

In consideration of these points, raster scan type graphic display devices are equipped with pixel buffers that can temporarily hold data for multiple pixel valves, and are capable of processing multiple pixel valves in one memory cycle. It is possible to write data in batches, and in order to achieve even higher speeds, it has become quite common to provide a pair of pixel buffers.This pixel buffer method is It can be said that this is somewhat similar to the fill-in mode that occurs in bitmap eye display devices. In contrast, in the pixel buffer 1 method,
The two are significantly different since it is not possible to employ a configuration that provides a common value for all pixels within a word boundary with FOR.

However, in the above pixel buffer method, since the number of data lines in the frame buffer 7 memory is set equal to the product of the number of planes and the number of bits in one word, all FORs in the pixel buffer have the same number of data lines. Fill-in mode is easiest to implement by storing the value and overriding the pixel specified by FOR only in the corresponding pixel portion in correspondence with the mask data.

On the other hand, if you try to realize other modes, there are many data lines (for example, 16M colors and 8 lines per word).
In the case of bits, there are 192 data lines), so it becomes necessary to add an extremely large number of multiplexers and selectors, resulting in a problem that the configuration becomes clumsy and complicated. That is, since the data line selection directions are different between the pixel mode and the plane mode, a significantly large number of full diverters and selectors are required to select both modes.

As is clear from the above explanation, it is almost impossible to achieve both the bitbltfi function of a bitmap display and the high-speed drawing function of a raster scan type three-dimensional graphic display; However, if a configuration was adopted that fully demonstrated the other functions, the other function would remain insufficient, and the demand for multifunctionality could not be fully satisfied.

In particular, when it is necessary to fill a polygon, even if linear interpolation calculations using one DA are performed continuously without stopping, a significantly large amount of pixel data will be generated. As a result, there is a problem in that an insufficient processing speed can be achieved for both the high-speed drawing function and the old TBLT function.

<Object of the invention> This invention was made in view of the above problems,
An object of the present invention is to provide an image memory data processing control device that can perform high-speed drawing processing using DDA and high-speed bitblt processing even when coloring processing is involved. It is said that

<Means for Solving the Problems> In order to achieve the above object, the image memory data processing control device of the present invention includes a plurality of block memories constituting the image memory, a pixel register, and a timing control means. , a plurality of DDAs for coloring, a write decoder, a read decoder such as a delay means, a pixel data temporary holding means, a shift means, and a selection calculation means.

The pixel register is provided corresponding to each block memory and holds a predetermined number of pixel data continuous in the scan line direction. The write decoder receives the access address data outputted from the DDA as input and generates a selection signal for selecting the block memory and pixel register. It generates a signal for selecting modules for a predetermined number of pixels among the number of pixel registers, and the above-mentioned "extending means"
The readout decoder delays the access address data outputted from the DDA for a predetermined period of time, and the readout decoder inputs the address data output from the delay means and selects a predetermined pixel out of a predetermined number of pixel registers. It generates a signal that selects the module for a few minutes,
The pixel data temporary holding means has addresses sequentially changed in synchronization with the DDA, and continuously stores data selected by the reading decoder and output from the IC module along a linear interpolation trajectory, and also writes data. The above-mentioned shift means 1 to 1 supply the coordinate values in the direction perpendicular to the scan line in the source region and the coordinate values in the direction perpendicular to the scan line in the destination region. A shift amount is set based on the pixel data temporary holding means, and the pixel data read from the pixel data temporary holding means is reshifted by the set amount. The pixel data read out from the pixel data temporary holding means is selectively supplied to the module, and raster operations are performed on the condition that the pixel data read out from the pixel data temporary holding means is selected.

However, a plurality of block memories are allocated to correspond to one linear interpolation calculator, and the timing control means sequentially supplies pixel data generated by one linear interpolation calculator to the block memories. It is preferable that the state in which the image is drawn is selectively selected.

Further, as the delay means, an FIF that delays the read address data output from DD△ by a predetermined time is used.
There may be an O memory e, or a DDA that generates read address data at a timing delayed by a predetermined time.
Deat-(Moyoi.

The pixel data temporary holding means may be composed of a static random access memory and an up counter that sequentially increases address data, or may be a FIFO memory.

Moreover, it is preferable that the shift means 1 to 1 be a barrel bath shifter.

Furthermore, the timing control means decodes the lower digits of the coordinate data in the scan direction to generate a control signal for switching the pixel register,
It is preferable to generate a control signal for selecting a pixel register by decoding the lower digits of the coordinate data in a direction perpendicular to the scan direction, and to generate the control signal at the timing when the lower predetermined digits of the coordinate data change. It is preferable that it generates. In the latter case, the timing control means controls Ig! in the scanning direction. For standard data, a control signal is generated at the timing when the lower predetermined digit corresponding to 1 changes in the content of the pixel register,
For coordinate data in the direction perpendicular to the scan direction, M
It is more preferable that the control signal be generated at the timing when the least significant digit changes.

Furthermore, it is preferred that the image memory is a dual port dynamic random access memory.

<Operation> If the image memory data processing control device has the above configuration,
The image memory is composed of a plurality of block memories, and also includes a plurality of DDAs, and a selection signal for selecting a pixel register, a block memory, and a pixel register is generated in correspondence with each block memory. A write decoder and a read decoder that generate a signal for selecting a module for a predetermined number of pixels out of a predetermined number of pixel registers, and a plurality of pixels corresponding to each DDA. Since it is equipped with a data/time holding means, a shift means, and a selection calculation means, when simply drawing, it is possible to draw data along the scan line at very short time intervals from multiple DDAs that perform high-speed calculation operations. A large number of pixel data are generated sequentially and simultaneously. Then, the fill pixel data is supplied to the corresponding pixel register based on a control signal generated from the timing control means, and the pixel data for at least one pixel held in each pixel register is collectively stored in the corresponding block memory. written.

Therefore, the time required to generate data per pixel and the time required to write data are reduced (less than the time required to generate data by DDA), improving the overall drawing speed and realizing real-time display of filled figures. can be achieved.

In addition, when bitblt processing is performed, each OD
A sequentially and simultaneously generates address data along different scan lines in the source area, and supplies it to the image memory as a read address. ,
Then, under the control of the timing control means, the pixel data is sequentially supplied to the temporary holding means through the pixel register, and is temporarily held. Next, the DDA sequentially generates address data along different scan lines in the destination area, and the data read from the destination area and the pixel data temporary holding means are sequentially generated, and the address data is sequentially generated along different scan lines in the destination area. A raster operation is performed by supplying the data shifted in the direction perpendicular to the scan line to the selection operation means. Then, by writing the data obtained by performing the raster operation to the datenation area through the pixel register module selected based on the output data from the write decoder, the datenation of the source area data is performed. Transfers can be made to the area.

Thereafter, data transfer for multi-window display, etc. can be performed by performing the above series of operations for all scan lines.

As is clear from the above explanation, when performing bitblt processing, DDA is used to read source area data.
It is necessary to perform arithmetic operations using the DD, and also to write to the destination area.
Since it is necessary to perform arithmetic processing using A, the overall processing speed can be improved to more than half the filling processing speed using DDA.

A plurality of block memories are allocated to correspond to one linear interpolation calculator, and the timing control means sequentially transfers the pixel data generated by one linear interpolation calculator to the block memory. In this case, even if it takes a long time to write data to the block memory, the data writing speed per pixel can be gracefully improved.

Further, the delay means delays the read address data output from the DDA for a predetermined period of time.
○DDA that generates read address data at a timing that is delayed by a predetermined time even when it is a memory
In this case, the same effects as those described above can be achieved.

= 22- Furthermore, even when the pixel data temporary holding means is composed of a metadic random access memory and an up counter that sequentially increases address data, or when it is an FFO memory, , the same effect as above can be achieved.

In addition, if the timing control means generates a control signal for decoding the lower digits of the coordinate data in the direction perpendicular to the scanning direction to select the pixel register, the source data that is continuous in the skimming direction is generated. , in a state where bitbltIP is executed based on the destination data, the lower digits of the coordinate data in the direction perpendicular to the scanning direction are decoded to select the pixel register, so the same pixel register is selected next time. It becomes possible to write data to the destination area or read data from the source area until it is selected, and it is possible to improve the image memory data processing control speed as a whole.

Furthermore, if the timing control means generates a control signal at the timing when a lower predetermined digit of the coordinate data changes, it is possible to accurately hold the read source data in a predetermined pixel register. , and the same effect as above can be achieved.

Furthermore, the timing control means generates a control signal at a timing when a predetermined upper digit corresponding to the capacity of the pixel register changes for the coordinate data in the scanning direction, and for the coordinate data in the direction perpendicular to the skimming direction,
If the control signal is generated at the timing when the least significant digit changes, the pixel register can be selected based on the generated control data, and the same effect as above can be achieved. can.

Furthermore, the image memory is dual port DRAM.
In this case, it is possible to greatly reduce the prohibition time for data writing associated with reading data from the image memory, and it is also possible to achieve the same effect as described above.

<Example> Embodiments will be described in detail below with reference to the accompanying drawings showing examples.

FIG. 1A shows the image memory data processing fee of the present invention.
It is a block diagram showing one embodiment of the device, in which a frame memory (1) is divided into a plurality of block memories (11), (12),
...(1m), and each block memory (
11)(12)...(1m), respectively, pixel registers (21)(22)...(2m) and timing control circuits (31)(32)...(3m)
) is provided so that pixel data can be exchanged between any pixel register and the block memory based on control signals output from each timing control circuit. In addition, each pixel register mentioned above is
Each has n modules in the scan line direction.

Then, by being supplied with the address data of the end points of the filled line segments in the scan line direction, a plurality of DDAs (41) (42) perform linear interpolation calculations to sequentially generate address data on the frame memory.・(4
k) and D D A (41) (42)...(4k)
DD A (41a) (42a) - (4ka) that performs linear interpolation calculations in synchronization with the
), and the above DDA(41)(42)...(4k
) The address data output from the timing control circuit is rezo-coded to generate a control signal, and the write decoders (51a), (52a) and (
5ka) to generate a write selection signal corresponding to each of the mxn modules as a whole, and conversely, the FIFO memory (61b) (62b)...
・Read decoder (61a1G2) through (6kb)
a)-(6ka), and a read selection signal corresponding to each of mxn modules in total is generated.

Also, block memory (11) (12)... (1m)
From pixel register (21) (22)...(2m)
The pixel-by-pixel color information data read out to the data bus (
21a) (22a)...(2ma) and a buffer (not shown) to a static random access memory (hereinafter referred to as S) as a temporary storage means for pixel data.
(abbreviated as RAM) (71), (72)... (7k). And the above S RAM
The supply of address data for (hH72)...(7k) is DDA (41042)...(4k)
Up counters (71a) (72a) whose contents are incremented in synchronization with the generation of address data by
- (7ka), so the read data is stored in SRAM (71) (72) in the order of reading.
)...(7k), and the stored data can be stored without being read out to the storage. Above SRΔ
The data read from M (71) (72)...(7k) is caused by barrel bus jitter (71b) (72b)...
(7 kb), and is the number of bits corresponding to the scan line shift between the source data and the destination data.

Furthermore, the above DDΔHa><'tr2a)・(4ka)
The color information data generated by and the color information data output from the barrel bus shifters (7111) (72b)...(7kb) are sent to the selectors (81) (82)...(
8k) and selectors (81) (82)...(
The data selected by the pixel registers (21) (22) (2m) are controlled by the timing control circuits (31) (32) (3m).
) is supplied to J: (see Figure 1B).

FIG. 2 is a diagram explaining in detail the configuration of the module that makes up the pixel register. The operation result data output from the processor (92) which receives read data from the processor (92) is supplied to the frame memory (1) constituted by a DRAM through a bidirectional buffer (93). Then, the data read from the frame memory (1) is supplied to the read register (94) through the bidirectional buffer (93), and the data held in the read register (94) is also supplied to the arithmetic unit (92). By supplying the data, raster operations can be performed.

Further, the data held in the readout register (94) passes through an output buffer (95) and is sent to the data bus (2a). Note that the arithmetic unit (92) has functions such as a selector, and also has a raster arithmetic function.

Therefore, by switching the mode of the arithmetic unit (92), it is possible to selectively include simply pixel-by-pixel color information data or write the result of raster operation.

The operation of the image memory data processing control device having the above configuration is as follows.

When simply writing pixel data, - write decoders (51a) (52a) - (5ka) and read decoders (61a) (62a)... (6k
a) is prohibited and together with Teok, D D A (4
1a) (42a) to (4ka) by switching the reflectors (81), (82), . . . (8k) ().

Ko (7) In state: J5 IT, Dr) A (4
1) Once address data is generated sequentially from (42) and (4k), the timing control circuit (
31)(32)...(3m) generates a control signal and selects only the pixel register corresponding to the generated address data, so DDA(41)(42)...
・Dr)A (41a) (4k) that operates in synchronization with (4k)
The pixel-by-pixel color information data generated by 2a)...(4ka) can be supplied to the corresponding module of the selected pixel register.

When the data supply to the corresponding pixel register reaches its limit, or when the y-coordinate value changes, all the color information data held in the pixel register is collectively stored in the frame memory ( 1) Writing speed per pixel can be improved. Note that while data is being written from the corresponding pixel register to the frame memory (1), the DDA (41a) (42a)
...(4ka) can supply the pixel-by-pixel color information data that continues to be output to the other pixel register.

However, Ste, D D A (41) (42)・(4kH
Linear compensation fff by 41aH42a)...(4ka)
Frame dry (1
), and the overall drawing speed can be increased by the calculation speed J: by DDA. In other words, if the number of DDA is increased, the number of pixel data generated simultaneously will increase.C1
The drawing speed can be increased accordingly.

When performing bitblt processing, the operation of write decoders (51aH52a)-(5ka) and read decoders (61a) (62a)...(6ka) is allowed, and SRAM (71) (72
)...(7k) may be selected by switching the selectors (81), (82)...(8k).

In this state, based on the end point address data of the line segment in the scan line direction in the source area,
If the address data on the source vector is generated sequentially from (4, 1) (42)...(4k), the timing control circuit (31) (32)...(3
m) generates a control signal and selects a block memory, so the corresponding pixel data of the selected block memory can be read out. And FIFO memory (61b) (
62b)...(6kb), the address data that has been extended by the required reading time is sent to the read decoder (61
a) (62a) and (6ka), and is supplied to the decoder (6ka).
1a) (62a)...(6ka), the source region,
Since a module selection signal corresponding to the type of bitblt processing is output, read data is held only in the selected module. After that, the held read data is transferred to the data bus (21aH22a)...(2m
a) and are temporarily held in SRAM (71), (72), . . . (7k) in the order of reading through a buffer (not shown). In this case, S RAM (
The address data of 71)(72)...(7k) is synchronized with the operation of DDA(41)(42)...(4k) by up counters (71a)(72a)(7ka). is incremented. Also, S.R.A.M.
Barrel bus shifter (71b) (72) that shifts data read from (71) (72)...(7k)
b)...(7kb) is the line segment y in the source region
The number of bits to be shifted 1 is set based on the difference between the coordinate value ys and the y coordinate value yd in the destination area.

After reading one line segment in the scan line direction in the source area as described above, the end point address data of the corresponding line segment in the scan line direction falling in the destination area is transferred to DDA(41)(42). ...(4
k) to sequentially generate address data on corresponding line segments in the scan line direction in the destination area. This address data is supplied to the timing control circuits (31) (32)...(3m) and the write decoders (51a) (52a)...(5ka), so it is Timing control circuits (31) (32)... (3m) generate control signals, select pixel registers and block memories, and write decoders (51a) (52).
a)...(5ka) outputs a module selection signal corresponding to the destination area and the type of bitblt processing, so write data is held only in the selected module.

Then, regarding the retained write data, the arithmetic unit (
Raster operation is performed by the bidirectional buffer (92).
3) is written to the corresponding block memory.

To explain in detail the operation in the module, as shown in FIG. 3, between time to and 11, pixel P
Color information data (xl, yl) is supplied to the writing double buffer (91), and read-modify-write (hereinafter abbreviated as RMW) is performed between the block memory and the subsequent time 11 to t2. At the same time, the color information data is output from the double buffer (91) and the color information data is output from the read register (94), and at the same time, the double buffer (91) is output.
1), color information data of pixel P (x2, y2) is supplied. After that, between time t2 and t3, the RMW for pixel P (x2. y2) and the color information data for pixel P (x 3. y 3) are supplied.

Therefore, by repeating the above series of operations, 1
If we focus on one DDA, it is about 1/2 of the calculation speed of DDA.
The old tblt processing can be performed at a processing speed of . In the case of the above embodiment, since the DDA is assigned an individual number and is made to perform parallel operations, the calculation speed of DI)Δ is approximately equal to /
bitblt processing can be performed at a processing speed of 2. As a result, for example, regarding the multi-window function, the degree of freedom in multi-window display can be significantly increased, the overall configuration can be simplified, and the multi-window function can be performed at high speed. can.

FIG. 4 is a schematic block diagram showing a specific example, in which k is set to 2 and ml, J: and n are both set to 8.

In this embodiment, two pixel data generation units for coloring (I'1) (1'2) are provided, and a barrel shifter (BS) is provided between both pixel data generation units for coloring (Fl) (F2). ), and in addition, even-numbered timing control circuits (31) (33) (35) (37
), pixel register (21) (23) (25) (21
), and block memories (11) (13) (15) (
17), odd-numbered timing control circuits (32) (34) (36) (38>, pixel registers (22) ( 24), (26), and (28), and the block menus (12), (14), (16), and (18) are made to correspond to each other.The pixel data generation section for each of the above-mentioned fill-in data is stored at the address shown in FIG. The configuration includes a DDA for data generation, a DDA for color information data generation, an SRAM for temporarily holding read data, an up counter for supplying address data to the SRAM, a path barrel shifter for shifting the y-coordinate, and a selector.

In the case of the above embodiment, the end point data of the line segment on the even-numbered scan line is generated by the filling pixel data generator (
"1), and the end point data of the line segment on the odd scan line is supplied to the pixel data generation section for filling ("2").
address data for coloring,
Generate Onibi color information data. Then, the generated address data is supplied to the corresponding timing control circuit, thereby generating a control signal for selecting the pixel register and block memory.

Therefore, when simply performing a drawing operation, it is sufficient to write color information data into the block memory in correspondence with the address data, and data is generated simultaneously by both filling pixel data generating sections.
Since data is written to the block memory through the corresponding pixel register, the drawing operation is performed at a higher speed per pixel than the linear interpolation calculation method using DI) A. can be set.

In addition, when performing bitblt processing, address data for reading is generated sequentially and simultaneously in correspondence with the line segments in the scan line direction in the source area, and is supplied to the corresponding block memory, so that the address data is passed through the pixel register. Color information data of pixels on the line segment can be read out sequentially and simultaneously. Then, the read color information data is supplied to the pixel register in synchronization with the generation of address data corresponding to the line segment in the scan line direction in the destination area, and raster calculation is performed in the module constituting the pixel register. is written to the datenation area. However, if the read color information data is in a state where the even and odd numbers of the scan line in the source area and the scan line in the cancellation area match each other, the color information data is used for coloring to which the read data is supplied. By outputting the pixel data as it is from the pixel data generation unit, bitblt processing can be performed without any inconvenience, but if the even and odd numbers do not match each other, each pixel data generation unit for filling The retained color information data is transferred to the barrel shifter (BS
), the even-numbered and odd-numbered pixels are exchanged, and in this state, the color information data held in each pixel data generation section for filling is output, thereby eliminating the misalignment of the scan line. bit in condition
blt processing can be performed. In this case, the color information data can be read out sequentially and simultaneously without stopping the linear interpolation calculation by DDA, and the color information data that has been successively read out can be written sequentially and simultaneously. Therefore, when converted to per pixel, b
The itblt processing speed can be made significantly faster than 1/2 of the bilinear interpolation calculation speed in DDA.

FIG. 5 is a diagram schematically explaining the relationship between the modules constituting the pixel register and the frame memory (1). ... (18) and eight pixel registers (21) (22)
...(28) are each composed of eight modules. That is, m1 and n are both set to 8.

A pixel-by-pixel color information data input bus (4ib), a pixel-by-pixel color information data output bus (2ia) are connected to each pixel register.

Therefore, by the write decoder (see Figure 1),
All modules (231) of pixel registers (23) (
232)...(238) is not selected and the decode signal is generated, the color information data sequentially supplied from the pixel unit color information data input bus (4b) is written into the block memory (13). Can be done.

Conversely, the readout decoder reads the pixel register (2
3) All modules (231) (232)...(2
38), the color information data read out from the block memory (13) can be taken out through the pixel unit color information data output bus (2a).

In the above, only the case where all the modules (231), (232), ... (238) of the pixel register (23) are selected is explained, but if only any module of any pixel register is selected. , it is possible to perform processing corresponding to the pixel mode in which block memory is accessed pixel by pixel, and by selecting only the necessary module from all the modules of any pixel register, the selected module It is possible to perform processing corresponding to the fill-in mode in which the block memory is accessed only for pixels corresponding to the block.

To summarize the above, when accessing the image memory, the image memory is divided into a plurality of block memories, and a C pixel register and a timing control circuit are installed for each block memory. Therefore, pixel data can be written into the image memory without stopping the linear interpolation calculation using each DDΔ, and a drawing operation can be performed at extremely high speed.

Also, when reading pixel data from image memory,
Pixel data on any line segment can be read without stopping the generation of read address data by each DD△, and raster operations are performed on the read pixel data.
Similarly to the above, writing to the image memory can be performed at high speed, so select the modules that make up the pixel register appropriately using the decode signal.
It becomes possible to perform processing similar to the function, and furthermore, the bitblt processing speed can be significantly improved.

However, when performing bitblt processing, memory accesses corresponding to line segments along the scan line are performed, so two pixel registers are set for each block memory (for example, one pixel register is By performing batch output processing of pixel data from the other pixel register while pixel data is being written to the register, the overall processing speed can be further improved. Although it is possible to use the pixel registers provided for each block memory for writing pixel data and for reading pixel data, it is possible to use a dedicated pixel register for writing pixel data, and for reading pixel data. A configuration in which a pixel register is provided may also be adopted.

Furthermore, when the above-mentioned bitblt processing is selected, if a texture mapping algorithm that projects pixel data on the source line segment onto the destination line segment is also used, enlargement processing, reduction processing, and rotation processing can also be performed in the cylinder. be able to.

Furthermore, in the above timing control circuit, DDΔ(4
1) The pixel register is switched or selected based on the change in the contents of a specific digit of the address data output from (4k). The change in content is as shown in Figure 6A.
The output data from △ (41) is sequentially transferred to the register (51) (
This can be easily done by adopting a pipeline configuration that supplies the data to 52).

That is, as shown in FIG. 6B, the register (51) (
52) as a D type Noritsubu flop (hereinafter referred to as D-
FF), and the first stage D-FF (abbreviated as FF) is used.
51), the j-th digit data output from the DDΔ adder (41) is supplied to the D input terminal of the first stage D -F F
The Q output signal of (51) is transferred to the second stage D-FF (52
), and furthermore, both D-FF (51
Adopting a configuration that supplies the DDA clock signal to the timing input terminal of the H52)
Q output signals a, f, bJ and 0 output signals AJ, b
, p are obtained. Then, the obtained signals bJ and a
In addition to supplying J to the AND gate (53), the signal a
J, and 6. f is supplied to the AND gate (54), and the output signals from both AND gates (53) and (54) are NORed.
By supplying the signal 1 to the game 1 (55), a detection flag for detecting a change in a specific digit can be generated.

Figure 7 shows the change in the least significant digit of the y coordinate, the predetermined number from the least significant digit of the x coordinate (the change in the most significant digit, and the end of line segment drawing)
This shows a circuit configuration that detects only when the lower digit of the y-coordinate is a predetermined value, and includes a DDΔ adder (56) for the x-coordinate.
, the output data from the DDA adder (57) for the 58)), which becomes high level when the contents of D
The output signal from the decoder (59), which becomes high level when the content of the lower digit becomes a value corresponding to a predetermined block memory, is input to the y-coordinate data output from the DA and is applied to the AND gate (60). ) is supplied to C. The output signal from the decoder (59) is supplied to all the AND gates 1 to 1, and the output signal from all the AND gates is supplied to the NOR gate (61).

Therefore, when the above configuration is adopted, when the output horn signal from the decoder (59) is at a high level, a change in the lowest digit of the y coordinate, a change in a predetermined digit of the X coordinate, and the end of line segment drawing In response to this, a negative logic pixel register switching timing detection flag can be output from the NOR gate (61).

In addition, the decoder shown in FIG. 7 and A N l) −0
R-INVERTER is easily PLD (Proa
ramable Logic Device).

FIG. 8 shows timing control of DRAM as a block memory and pixel register switching without stopping the DDA based on the pixel register switching timing detection flag generated by the circuit configuration illustrated in the above embodiment. It is a diagram showing the circuit configuration for eight D-F F (74) (72)...
78).

The above D-F F (71) is a horizontal synchronizing signal -HS ha rK-〇(
(See FIG. 9C) as the timing input, and the handshake signal H81 (see FIG. 9C) indicating whether read transfer or refresh has been accepted as the clear input signal. is a Q output signal Q1 indicating whether a refresh request is occurring or not.
(see Figure 9C), and this Q output signal Q1 is directly applied to the sampling strobe signal 5RG.
D -F with K (see diagram 9) as timing input
It is supplied to the D input terminal of F (72) and generates a tQ output signal Q2 (see FIG. 9M) indicating whether it is a write cycle, a read transfer, or a reflex cycle to the DRAM.

The above D-F F (73) and (74) hold the vixel register switching timing detection flag BOVF (see Figure 9C), and have the same operation except that they operate selectively. I am trying to do this. That is,
NAND with the ○ output signal of the above D-FF as control number 43
A pixel register switching timing detection flag BOVF is supplied to the D input terminal through a gate (79), and DD△pixel ST1]-B signals DD, ARCK (FIG. 9C ) is O
A negative logic handshake signal 1-18 is applied to the timing input terminal at F through gate (80) and indicates that the memory write cycle has been accepted.
2 (see FIG. 9N) is supplied to the clear input terminal through OR'7'-t- (81) and HAND gate (82). Then, the Q output signal output from D-FF (78) corresponds to one D-FF.
5ELA (see diagram 9), and 0 output signal 5Ei-
s (see Figure 9 N) are OR gates (80) (8
1), and corresponds to the other D-FF,
Q output signal 5E output from D-F F (78)
LA and O output signals 5ELB are supplied to OR gates (81) (80), respectively.

Therefore, of the Q output signal 5E1-Δ or (5 output signal SELB) supplied to the OR gate (80), the D-FF on the low level side is selected for data retention. , the pixel register switching timing detection flag 80VF is taken in at the rising timing of the DDA pixel strobe signal DDARCK.However, the pixel register switching timing detection flag BOVF is controlled by the NAND group 1- (79
), so the C signals BF1 and BF2
(See FIGS. 9I and J)) is supplied to the D input terminal at a timing when a pixel register full state is likely to occur, and at the same time is supplied to an OR gate 1-(83) to be described later, and is bolded as it is.

The above D-F F (75) generates a Q output signal Q3 corresponding to the next pixel register switching state, and supplies a 0 output signal to the D input terminal,
The negative logic handshake signal I7 is supplied to the timing input terminal.

The D-F F (76) and (77) described above generate the sampling strobe signal 5RCK synchronized with the R] cock without generating glitches, and are negative logic pulses that do not indicate two clocks before the end of the memory cycle. signal MB
F2 (see FIG. 9 N) is supplied to the timing input terminal of the D-FF (76), and a negative logic pulse signal CAS (for example, a DRAM column address strobe signal) is supplied to the timing input terminal of the D-FF (76). Figure 9 N
) is supplied to the preset input terminal. Then, the Q output signal Q1 of Juki D-FF (71) and the output signal from the NAND gate (79) corresponding to both -F F (73) (74) are passed through the OR gate (83) to the D-FF. (77), as well as the 0 output signal of D-FF (76) and (77), and the sampling clock signal SCK (see Figure 9N).
The output signal from the NAND gate (84) which receives as input is outputted as a pump dust strobe signal SRGK, and is also supplied to the timing input terminal of DFF (77).

Then, the negative logic pulse signal CAS is applied to D-FF (77
) is supplied to the clear input terminal. Also, D-F
The Q output signal of F (77) is used as a start signal (9th signal) indicating that the memory cycle starts at the rising timing.
(See Figure N).

The above-mentioned -FF (78) outputs the signals SFLΔ and 5ELB for pixel register switching as a Q output signal and a 0 output signal, respectively, and the above-mentioned D -FF (7
While the Q output signal of 5) is being supplied to the zero horn terminal, the → none printer strobe signal 5RCK is being supplied to the timing input terminal, and the above O
The output signal ACDM (see FIG. 9) from the R gate (83) is supplied to the G input terminal through an inverter (85).

Therefore, at the timing when the signal supplied to the G input terminal is at low level and the sampling strobe signal 5RCK rises, the Q output signal from the above r)-F F (75) is held, and the level of this Q output signal is Correspondingly, Q output signals 5EI-Δ, d3 and O output signal 5ELB, which have opposite levels to each other, are continuously output.

Furthermore, the negative logic initialization signal RESET (see FIG. 9N) is
...(78) are respectively supplied to the clear input terminals.

The operation of the circuit shown in FIG. 8 is as follows.

First, when the power is turned on or when processing is interrupted, the initialization signal R is
Perform the necessary initialization on ESET.

After that, the level of the Q output horn signal of the D-FF (75) changes alternately every time the negative logic handshake signal H82 is supplied to the timing input terminal, so a low level signal is supplied to the G input terminal. And at the timing when sampling strobe signal S RG K rises, o-F F
m (78) can hold the Q output signal and output a Q output signal 5ELA1 and a 0 output signal 5ELB corresponding to the level of the Q output signal. Therefore, one of the D-FFs (73) (74) is selected based on the levels of the Q output signal S[LΔ and the 0 output signal 5FLB. That is, the D-FF on the side to which the low level signal is supplied to the OR gate 1-(80) is selected.

Then, the D-FF on the selected side has a 0 output signal and a J
The pixel register switching timing detection flag BOVF is supplied as the D input signal through the NAND gate (79) controlled by
Since the pixel strobe signal DDARCK is supplied to the pixel strobe signal DDARCK, the pixel strobe signal DDARCK is supplied to the DD8.
At the rising edge of K, the pixel register switching timing detection flag BOVF is taken in and held as A. Furthermore, the pixel register switching timing detection flag BOVF is not taken out from the Q output terminal of D-FF, but is taken out as it is from the output J terminal of NAND goo 1-(79). It is supplied to ORG 1 to (83) at the timing when the pixel register is full, without the proximity of pixels, and D - F
By being supplied to the D input terminal of F (77),
From the Q output terminal, it is possible to output a start signal indicating the beginning of memory 1 noise U (1).

Then, every time the handshake signal 182 of negative logic is supplied to the timing input terminal, D-FF (73) (7
4) The above series of operations can be performed by changing the selection state of 1. FIG. 9 is a timing control circuit for explaining the operation of each part of the circuit of FIG. The reread transfer operation is performed one after another, and 2. During the period T3, image data is updated.

Therefore, by providing timing control circuits having the 1-configuration shown in FIGS. 7 and 8 in correspondence with each block memory, D D A (41) (42)...(4)
Image memory data processing control can be performed by reading data from and writing data to the frame memory (1) sequentially without stopping the arithmetic operation in step k). That is, in terms of per pixel, it is possible to perform the old tblt process of inputting t to the frame memory (1) in a time shorter than the calculation time required for D D A (, 11H42)...(4k). 3゜Also,
In the above embodiment, if a dual-port DRAM is used as the DRAM, the time required for reading data for display can be greatly reduced, and about 98% of the time can be allocated for data writing. Therefore, the overall time required to store data in the image memory can be reduced.

Note that the present invention is not limited to the above-mentioned embodiments. For example, it is possible to use an FIFO memory instead of an SRAM, and a delay r:IF
Instead of the O memory, it is possible to use a separate DDA that generates address data at a timing delayed by a predetermined time from the DDA, and further reduces the number of pixel registers, J: and timing control circuits. In addition to being able to change it, it is also possible to perform processing such as enlargement, reduction, rotation, etc., and it is also possible to make various other design changes without changing the gist of the invention. .

<Effects of the Invention> As described above, the present invention allows linear interpolation calculation operations by multiple DDAs to be performed at the same time without stopping when performing a normal drawing operation, thereby allowing 1B to be performed at high speed.
In addition to being able to perform one stroke, the data on the source line segment read from an arbitrary area of the memory is temporarily held in the pixel data temporary holding means whose address is sequentially increased; By writing the data onto the destination line segment via the pixel register that is controlled based on the pixel register module selection signal output from the decoder, the linear interpolation calculation operation by multiple DDAs can be written without stopping. The unique effect of performing simultaneous processing is that bttblt processing can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1A is a block diagram showing an embodiment of the image memory data processing control device of the present invention, FIG. 1B is a schematic diagram illustrating the operation of the barrel bus shifter, and FIG. 2 is a diagram of the modules constituting the pixel register. Figure 3 is a schematic diagram explaining the operation of the modules that make up the pixel register, Figure 4 is a schematic diagram showing a concrete example, and Figure 5 is a schematic diagram of the modules that make up the pixel register. Figure 6A is a schematic diagram showing the state in which DDΔ is pipelined; Figure 6B is a diagram that schematically explains the relationship between the data and the frame memory; Figure 6B is a diagram showing the state in which DDΔ is pipelined; 7 is a diagram showing the other side of the circuit configuration for detecting a change in the content of a specific digit of address data, and FIG. Figure 9 is a timing chart explaining the operation of the circuit diagram in Figure 8. Figure 10 is the principle of bitblt processing. Schematic diagram illustrating. (1) Frame memory, (5a) Writing decoder, (6a) Reading decoder, (6b)
...FIFO memory, (11) (12)... (1m
)...Block memory, (21)(22)...(2
m)...Pixel register, (31) (32)...
(3m)...timing control circuit, (41) (42)
・(4k)(41a)(42a)−(4ka) ・=
OD A. (71) (72)...(7k)...SRAM. (71a) (72a) - (7ka) -7 knob counter, (71b) (72b)... (7kb)... Barrel bus shifter, (81) (82)... (8k)... Selector , (92)...operating unit

Claims (1)

[Claims] 1. The image memory (1) is a plurality of block memories (11)
(12)...(1m), and multiple linear interpolation calculators for filling (41)(42)...
- Equipped with (4k) (41a) (42a)... (4ka), and also corresponds to each block memory,
Pixel registers (21) (22) (2m) that hold a predetermined number of pixel data continuous in the scan line direction
), the access address data output from the linear interpolation calculators (41) (42)...(4k) are input to the block memories (11) (12)...(1m), and the pixel register (21). (22)...(2m) Timing control means (31) that generates a selection signal for selecting (2m)
)(32)...(3m), and further inputs the access address data output from the linear interpolation calculators (41)(42)...(4k) to input the access address data of the predetermined pixel register. Of these, a write decoder (51a) (5) generates a signal for selecting modules for a predetermined number of pixels.
2a)...(5ka) and delay means (61b) (62b) for delaying the access address data output from the linear interpolation calculator by a predetermined time.
)...(6kb) and the address data output from the delay means as input, readout decoders (61a) (62a) generate signals for selecting modules for a predetermined number of pixels from a predetermined pixel register. ...(6ka
), and each linear interpolation calculator (41) (42)...(4k
), the addresses are sequentially changed in synchronization with Holding means for supplying multiple pixel data (
71)(72)...(7k), the shift amount is set based on the coordinate value in the direction perpendicular to the scan line in the source area, and the coordinate value in the direction perpendicular to the scan line in the destination area, and the pixel Shifting means (71b) (72b)...(7kb) for shifting read pixel data from the data temporary holding means by a set amount;
Linear interpolation calculator (41a) (42a)...(4ka)
selectively supplies the pixel data generated by the pixel data and the pixel data read out from the pixel data temporary holding means (11), (72), ... (7k) to the module,
Pixel data temporary holding means (71) (72)... (7k
) selection calculation means (81) (82) that performs raster calculation on the condition that pixel data read from
An image memory data processing control device characterized by comprising (8k) and (92). 2. A plurality of block memories are allocated to correspond to one linear interpolation calculator, and the timing control means sequentially supplies pixel data generated by one linear interpolation calculator to different block memories. An image memory data processing control device according to claim 1, which selects a state. 3. The image memory data processing control device according to claim 1, wherein the delay means is a FIFO memory (6b) that delays the read address data output from the linear interpolation calculator by a predetermined time. 4. The image memory data processing control device according to claim 1, wherein the delay means is a linear interpolation calculator that generates the read address data at a timing delayed by a predetermined time. 5. The pixel data temporary holding means includes static random access memories (71) (72)... (7k) and an up counter (71a) that sequentially increases address data.
)(72a)...(7ka). 6. The image memory data processing control device according to claim 1, wherein the pixel data temporary holding means is a FIFO memory. 7. The shifting means is a barrel bus shifter (71b) (72b)
)...(7kb) The image memory data processing control device according to claim 1. 8. The timing control means according to claim 1 or 2 above, wherein the timing control means generates a control signal for decoding the lower digits of the coordinate data in a direction perpendicular to the scanning direction to select the pixel register. Image memory data processing control device. 9. The image memory data processing control device according to claim 1 or 2, wherein the timing control means generates the control signal at a timing when a lower predetermined digit of the coordinate data changes. 10. The timing control means generates a control signal for coordinate data in the scan direction at the timing when a lower predetermined digit corresponding to the capacity of the pixel register changes, and for coordinate data in a direction perpendicular to the scan direction, generates a control signal at the timing when the lower predetermined digit changes. The image memory data processing control device according to claim 9, wherein the control signal is generated at the timing when the lower digit changes. 11. The image memory data processing control device according to claim 1, wherein the image memory is a dual port dynamic random access memory.